drivers/pinctrl/nomadik/pinctrl-nomadik.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
__nmk_gpio_set_mode
__nmk_gpio_set_slpm
__nmk_gpio_set_pull
__nmk_gpio_set_lowemi
__nmk_gpio_make_input
__nmk_gpio_set_output
__nmk_gpio_make_output
__nmk_gpio_set_mode_safe
nmk_gpio_disable_lazy_irq
nmk_write_masked
nmk_prcm_altcx_set_mode
nmk_gpio_glitch_slpm_init
nmk_gpio_glitch_slpm_restore
nmk_prcm_gpiocr_get_mode
nmk_gpio_irq_ack
__nmk_gpio_irq_modify
__nmk_gpio_set_wake
nmk_gpio_irq_maskunmask
nmk_gpio_irq_mask
nmk_gpio_irq_unmask
nmk_gpio_irq_set_wake
nmk_gpio_irq_set_type
nmk_gpio_irq_startup
nmk_gpio_irq_shutdown
__nmk_gpio_irq_handler
nmk_gpio_irq_handler
nmk_gpio_latent_irq_handler
nmk_gpio_get_dir
nmk_gpio_make_input
nmk_gpio_get_input
nmk_gpio_set_output
nmk_gpio_make_output
nmk_gpio_get_mode
nmk_gpio_dbg_show_one
nmk_gpio_dbg_show
nmk_gpio_dbg_show_one
nmk_gpio_populate_chip
nmk_gpio_probe
nmk_get_groups_cnt
nmk_get_group_name
nmk_get_group_pins
find_nmk_gpio_from_pin
find_gc_from_pin
nmk_pin_dbg_show
nmk_dt_add_map_mux
nmk_dt_add_map_configs
nmk_dt_pin_config
nmk_find_pin_name
nmk_pinctrl_dt_get_config
nmk_pinctrl_dt_subnode_to_map
nmk_pinctrl_dt_node_to_map
nmk_pmx_get_funcs_cnt
nmk_pmx_get_func_name
nmk_pmx_get_func_groups
nmk_pmx_set
nmk_gpio_request_enable
nmk_gpio_disable_free
nmk_pin_config_get
nmk_pin_config_set
nmk_pinctrl_suspend
nmk_pinctrl_resume
nmk_pinctrl_probe
nmk_gpio_init
nmk_pinctrl_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Generic GPIO driver for logic cells found in the Nomadik SoC
   4  *
   5  * Copyright (C) 2008,2009 STMicroelectronics
   6  * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
   7  *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
   8  * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/io.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/slab.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_address.h>
  23 #include <linux/bitops.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/pinctrl/pinconf.h>
  28 /* Since we request GPIOs from ourself */
  29 #include <linux/pinctrl/consumer.h>
  30 #include "pinctrl-nomadik.h"
  31 #include "../core.h"
  32 #include "../pinctrl-utils.h"
  33 
  34 /*
  35  * The GPIO module in the Nomadik family of Systems-on-Chip is an
  36  * AMBA device, managing 32 pins and alternate functions.  The logic block
  37  * is currently used in the Nomadik and ux500.
  38  *
  39  * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
  40  */
  41 
  42 /*
  43  * pin configurations are represented by 32-bit integers:
  44  *
  45  *      bit  0.. 8 - Pin Number (512 Pins Maximum)
  46  *      bit  9..10 - Alternate Function Selection
  47  *      bit 11..12 - Pull up/down state
  48  *      bit     13 - Sleep mode behaviour
  49  *      bit     14 - Direction
  50  *      bit     15 - Value (if output)
  51  *      bit 16..18 - SLPM pull up/down state
  52  *      bit 19..20 - SLPM direction
  53  *      bit 21..22 - SLPM Value (if output)
  54  *      bit 23..25 - PDIS value (if input)
  55  *      bit     26 - Gpio mode
  56  *      bit     27 - Sleep mode
  57  *
  58  * to facilitate the definition, the following macros are provided
  59  *
  60  * PIN_CFG_DEFAULT - default config (0):
  61  *                   pull up/down = disabled
  62  *                   sleep mode = input/wakeup
  63  *                   direction = input
  64  *                   value = low
  65  *                   SLPM direction = same as normal
  66  *                   SLPM pull = same as normal
  67  *                   SLPM value = same as normal
  68  *
  69  * PIN_CFG         - default config with alternate function
  70  */
  71 
  72 typedef unsigned long pin_cfg_t;
  73 
  74 #define PIN_NUM_MASK            0x1ff
  75 #define PIN_NUM(x)              ((x) & PIN_NUM_MASK)
  76 
  77 #define PIN_ALT_SHIFT           9
  78 #define PIN_ALT_MASK            (0x3 << PIN_ALT_SHIFT)
  79 #define PIN_ALT(x)              (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
  80 #define PIN_GPIO                (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
  81 #define PIN_ALT_A               (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
  82 #define PIN_ALT_B               (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
  83 #define PIN_ALT_C               (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
  84 
  85 #define PIN_PULL_SHIFT          11
  86 #define PIN_PULL_MASK           (0x3 << PIN_PULL_SHIFT)
  87 #define PIN_PULL(x)             (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
  88 #define PIN_PULL_NONE           (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
  89 #define PIN_PULL_UP             (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
  90 #define PIN_PULL_DOWN           (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
  91 
  92 #define PIN_SLPM_SHIFT          13
  93 #define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
  94 #define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
  95 #define PIN_SLPM_MAKE_INPUT     (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
  96 #define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
  97 /* These two replace the above in DB8500v2+ */
  98 #define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
  99 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
 100 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
 101 
 102 #define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
 103 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
 104 
 105 #define PIN_DIR_SHIFT           14
 106 #define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
 107 #define PIN_DIR(x)              (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
 108 #define PIN_DIR_INPUT           (0 << PIN_DIR_SHIFT)
 109 #define PIN_DIR_OUTPUT          (1 << PIN_DIR_SHIFT)
 110 
 111 #define PIN_VAL_SHIFT           15
 112 #define PIN_VAL_MASK            (0x1 << PIN_VAL_SHIFT)
 113 #define PIN_VAL(x)              (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
 114 #define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
 115 #define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
 116 
 117 #define PIN_SLPM_PULL_SHIFT     16
 118 #define PIN_SLPM_PULL_MASK      (0x7 << PIN_SLPM_PULL_SHIFT)
 119 #define PIN_SLPM_PULL(x)        \
 120         (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
 121 #define PIN_SLPM_PULL_NONE      \
 122         ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
 123 #define PIN_SLPM_PULL_UP        \
 124         ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
 125 #define PIN_SLPM_PULL_DOWN      \
 126         ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
 127 
 128 #define PIN_SLPM_DIR_SHIFT      19
 129 #define PIN_SLPM_DIR_MASK       (0x3 << PIN_SLPM_DIR_SHIFT)
 130 #define PIN_SLPM_DIR(x)         \
 131         (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
 132 #define PIN_SLPM_DIR_INPUT      ((1 + 0) << PIN_SLPM_DIR_SHIFT)
 133 #define PIN_SLPM_DIR_OUTPUT     ((1 + 1) << PIN_SLPM_DIR_SHIFT)
 134 
 135 #define PIN_SLPM_VAL_SHIFT      21
 136 #define PIN_SLPM_VAL_MASK       (0x3 << PIN_SLPM_VAL_SHIFT)
 137 #define PIN_SLPM_VAL(x)         \
 138         (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
 139 #define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
 140 #define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
 141 
 142 #define PIN_SLPM_PDIS_SHIFT             23
 143 #define PIN_SLPM_PDIS_MASK              (0x3 << PIN_SLPM_PDIS_SHIFT)
 144 #define PIN_SLPM_PDIS(x)        \
 145         (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
 146 #define PIN_SLPM_PDIS_NO_CHANGE         (0 << PIN_SLPM_PDIS_SHIFT)
 147 #define PIN_SLPM_PDIS_DISABLED          (1 << PIN_SLPM_PDIS_SHIFT)
 148 #define PIN_SLPM_PDIS_ENABLED           (2 << PIN_SLPM_PDIS_SHIFT)
 149 
 150 #define PIN_LOWEMI_SHIFT        25
 151 #define PIN_LOWEMI_MASK         (0x1 << PIN_LOWEMI_SHIFT)
 152 #define PIN_LOWEMI(x)           (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
 153 #define PIN_LOWEMI_DISABLED     (0 << PIN_LOWEMI_SHIFT)
 154 #define PIN_LOWEMI_ENABLED      (1 << PIN_LOWEMI_SHIFT)
 155 
 156 #define PIN_GPIOMODE_SHIFT      26
 157 #define PIN_GPIOMODE_MASK       (0x1 << PIN_GPIOMODE_SHIFT)
 158 #define PIN_GPIOMODE(x)         (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
 159 #define PIN_GPIOMODE_DISABLED   (0 << PIN_GPIOMODE_SHIFT)
 160 #define PIN_GPIOMODE_ENABLED    (1 << PIN_GPIOMODE_SHIFT)
 161 
 162 #define PIN_SLEEPMODE_SHIFT     27
 163 #define PIN_SLEEPMODE_MASK      (0x1 << PIN_SLEEPMODE_SHIFT)
 164 #define PIN_SLEEPMODE(x)        (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
 165 #define PIN_SLEEPMODE_DISABLED  (0 << PIN_SLEEPMODE_SHIFT)
 166 #define PIN_SLEEPMODE_ENABLED   (1 << PIN_SLEEPMODE_SHIFT)
 167 
 168 
 169 /* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
 170 #define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
 171 #define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
 172 #define PIN_INPUT_NOPULL        (PIN_DIR_INPUT | PIN_PULL_NONE)
 173 #define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
 174 #define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
 175 
 176 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
 177 #define PIN_SLPM_INPUT_PULLUP   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
 178 #define PIN_SLPM_INPUT_NOPULL   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
 179 #define PIN_SLPM_OUTPUT_LOW     (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
 180 #define PIN_SLPM_OUTPUT_HIGH    (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
 181 
 182 #define PIN_CFG_DEFAULT         (0)
 183 
 184 #define PIN_CFG(num, alt)               \
 185         (PIN_CFG_DEFAULT |\
 186          (PIN_NUM(num) | PIN_##alt))
 187 
 188 #define PIN_CFG_INPUT(num, alt, pull)           \
 189         (PIN_CFG_DEFAULT |\
 190          (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
 191 
 192 #define PIN_CFG_OUTPUT(num, alt, val)           \
 193         (PIN_CFG_DEFAULT |\
 194          (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
 195 
 196 /*
 197  * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
 198  * the "gpio" namespace for generic and cross-machine functions
 199  */
 200 
 201 #define GPIO_BLOCK_SHIFT 5
 202 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
 203 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
 204 
 205 /* Register in the logic block */
 206 #define NMK_GPIO_DAT    0x00
 207 #define NMK_GPIO_DATS   0x04
 208 #define NMK_GPIO_DATC   0x08
 209 #define NMK_GPIO_PDIS   0x0c
 210 #define NMK_GPIO_DIR    0x10
 211 #define NMK_GPIO_DIRS   0x14
 212 #define NMK_GPIO_DIRC   0x18
 213 #define NMK_GPIO_SLPC   0x1c
 214 #define NMK_GPIO_AFSLA  0x20
 215 #define NMK_GPIO_AFSLB  0x24
 216 #define NMK_GPIO_LOWEMI 0x28
 217 
 218 #define NMK_GPIO_RIMSC  0x40
 219 #define NMK_GPIO_FIMSC  0x44
 220 #define NMK_GPIO_IS     0x48
 221 #define NMK_GPIO_IC     0x4c
 222 #define NMK_GPIO_RWIMSC 0x50
 223 #define NMK_GPIO_FWIMSC 0x54
 224 #define NMK_GPIO_WKS    0x58
 225 /* These appear in DB8540 and later ASICs */
 226 #define NMK_GPIO_EDGELEVEL 0x5C
 227 #define NMK_GPIO_LEVEL  0x60
 228 
 229 
 230 /* Pull up/down values */
 231 enum nmk_gpio_pull {
 232         NMK_GPIO_PULL_NONE,
 233         NMK_GPIO_PULL_UP,
 234         NMK_GPIO_PULL_DOWN,
 235 };
 236 
 237 /* Sleep mode */
 238 enum nmk_gpio_slpm {
 239         NMK_GPIO_SLPM_INPUT,
 240         NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
 241         NMK_GPIO_SLPM_NOCHANGE,
 242         NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
 243 };
 244 
 245 struct nmk_gpio_chip {
 246         struct gpio_chip chip;
 247         struct irq_chip irqchip;
 248         void __iomem *addr;
 249         struct clk *clk;
 250         unsigned int bank;
 251         unsigned int parent_irq;
 252         int latent_parent_irq;
 253         u32 (*get_latent_status)(unsigned int bank);
 254         void (*set_ioforce)(bool enable);
 255         spinlock_t lock;
 256         bool sleepmode;
 257         /* Keep track of configured edges */
 258         u32 edge_rising;
 259         u32 edge_falling;
 260         u32 real_wake;
 261         u32 rwimsc;
 262         u32 fwimsc;
 263         u32 rimsc;
 264         u32 fimsc;
 265         u32 pull_up;
 266         u32 lowemi;
 267 };
 268 
 269 /**
 270  * struct nmk_pinctrl - state container for the Nomadik pin controller
 271  * @dev: containing device pointer
 272  * @pctl: corresponding pin controller device
 273  * @soc: SoC data for this specific chip
 274  * @prcm_base: PRCM register range virtual base
 275  */
 276 struct nmk_pinctrl {
 277         struct device *dev;
 278         struct pinctrl_dev *pctl;
 279         const struct nmk_pinctrl_soc_data *soc;
 280         void __iomem *prcm_base;
 281 };
 282 
 283 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
 284 
 285 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
 286 
 287 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
 288 
 289 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
 290                                 unsigned offset, int gpio_mode)
 291 {
 292         u32 afunc, bfunc;
 293 
 294         afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
 295         bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
 296         if (gpio_mode & NMK_GPIO_ALT_A)
 297                 afunc |= BIT(offset);
 298         if (gpio_mode & NMK_GPIO_ALT_B)
 299                 bfunc |= BIT(offset);
 300         writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
 301         writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
 302 }
 303 
 304 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
 305                                 unsigned offset, enum nmk_gpio_slpm mode)
 306 {
 307         u32 slpm;
 308 
 309         slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
 310         if (mode == NMK_GPIO_SLPM_NOCHANGE)
 311                 slpm |= BIT(offset);
 312         else
 313                 slpm &= ~BIT(offset);
 314         writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
 315 }
 316 
 317 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
 318                                 unsigned offset, enum nmk_gpio_pull pull)
 319 {
 320         u32 pdis;
 321 
 322         pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
 323         if (pull == NMK_GPIO_PULL_NONE) {
 324                 pdis |= BIT(offset);
 325                 nmk_chip->pull_up &= ~BIT(offset);
 326         } else {
 327                 pdis &= ~BIT(offset);
 328         }
 329 
 330         writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
 331 
 332         if (pull == NMK_GPIO_PULL_UP) {
 333                 nmk_chip->pull_up |= BIT(offset);
 334                 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
 335         } else if (pull == NMK_GPIO_PULL_DOWN) {
 336                 nmk_chip->pull_up &= ~BIT(offset);
 337                 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
 338         }
 339 }
 340 
 341 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
 342                                   unsigned offset, bool lowemi)
 343 {
 344         bool enabled = nmk_chip->lowemi & BIT(offset);
 345 
 346         if (lowemi == enabled)
 347                 return;
 348 
 349         if (lowemi)
 350                 nmk_chip->lowemi |= BIT(offset);
 351         else
 352                 nmk_chip->lowemi &= ~BIT(offset);
 353 
 354         writel_relaxed(nmk_chip->lowemi,
 355                        nmk_chip->addr + NMK_GPIO_LOWEMI);
 356 }
 357 
 358 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
 359                                   unsigned offset)
 360 {
 361         writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
 362 }
 363 
 364 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
 365                                   unsigned offset, int val)
 366 {
 367         if (val)
 368                 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
 369         else
 370                 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
 371 }
 372 
 373 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
 374                                   unsigned offset, int val)
 375 {
 376         writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
 377         __nmk_gpio_set_output(nmk_chip, offset, val);
 378 }
 379 
 380 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
 381                                      unsigned offset, int gpio_mode,
 382                                      bool glitch)
 383 {
 384         u32 rwimsc = nmk_chip->rwimsc;
 385         u32 fwimsc = nmk_chip->fwimsc;
 386 
 387         if (glitch && nmk_chip->set_ioforce) {
 388                 u32 bit = BIT(offset);
 389 
 390                 /* Prevent spurious wakeups */
 391                 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
 392                 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
 393 
 394                 nmk_chip->set_ioforce(true);
 395         }
 396 
 397         __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
 398 
 399         if (glitch && nmk_chip->set_ioforce) {
 400                 nmk_chip->set_ioforce(false);
 401 
 402                 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
 403                 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
 404         }
 405 }
 406 
 407 static void
 408 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
 409 {
 410         u32 falling = nmk_chip->fimsc & BIT(offset);
 411         u32 rising = nmk_chip->rimsc & BIT(offset);
 412         int gpio = nmk_chip->chip.base + offset;
 413         int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
 414         struct irq_data *d = irq_get_irq_data(irq);
 415 
 416         if (!rising && !falling)
 417                 return;
 418 
 419         if (!d || !irqd_irq_disabled(d))
 420                 return;
 421 
 422         if (rising) {
 423                 nmk_chip->rimsc &= ~BIT(offset);
 424                 writel_relaxed(nmk_chip->rimsc,
 425                                nmk_chip->addr + NMK_GPIO_RIMSC);
 426         }
 427 
 428         if (falling) {
 429                 nmk_chip->fimsc &= ~BIT(offset);
 430                 writel_relaxed(nmk_chip->fimsc,
 431                                nmk_chip->addr + NMK_GPIO_FIMSC);
 432         }
 433 
 434         dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
 435 }
 436 
 437 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
 438 {
 439         u32 val;
 440 
 441         val = readl(reg);
 442         val = ((val & ~mask) | (value & mask));
 443         writel(val, reg);
 444 }
 445 
 446 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
 447         unsigned offset, unsigned alt_num)
 448 {
 449         int i;
 450         u16 reg;
 451         u8 bit;
 452         u8 alt_index;
 453         const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 454         const u16 *gpiocr_regs;
 455 
 456         if (!npct->prcm_base)
 457                 return;
 458 
 459         if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
 460                 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
 461                         alt_num);
 462                 return;
 463         }
 464 
 465         for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
 466                 if (npct->soc->altcx_pins[i].pin == offset)
 467                         break;
 468         }
 469         if (i == npct->soc->npins_altcx) {
 470                 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
 471                         offset);
 472                 return;
 473         }
 474 
 475         pin_desc = npct->soc->altcx_pins + i;
 476         gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 477 
 478         /*
 479          * If alt_num is NULL, just clear current ALTCx selection
 480          * to make sure we come back to a pure ALTC selection
 481          */
 482         if (!alt_num) {
 483                 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 484                         if (pin_desc->altcx[i].used == true) {
 485                                 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 486                                 bit = pin_desc->altcx[i].control_bit;
 487                                 if (readl(npct->prcm_base + reg) & BIT(bit)) {
 488                                         nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
 489                                         dev_dbg(npct->dev,
 490                                                 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 491                                                 offset, i+1);
 492                                 }
 493                         }
 494                 }
 495                 return;
 496         }
 497 
 498         alt_index = alt_num - 1;
 499         if (pin_desc->altcx[alt_index].used == false) {
 500                 dev_warn(npct->dev,
 501                         "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
 502                         offset, alt_num);
 503                 return;
 504         }
 505 
 506         /*
 507          * Check if any other ALTCx functions are activated on this pin
 508          * and disable it first.
 509          */
 510         for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 511                 if (i == alt_index)
 512                         continue;
 513                 if (pin_desc->altcx[i].used == true) {
 514                         reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 515                         bit = pin_desc->altcx[i].control_bit;
 516                         if (readl(npct->prcm_base + reg) & BIT(bit)) {
 517                                 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
 518                                 dev_dbg(npct->dev,
 519                                         "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 520                                         offset, i+1);
 521                         }
 522                 }
 523         }
 524 
 525         reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
 526         bit = pin_desc->altcx[alt_index].control_bit;
 527         dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
 528                 offset, alt_index+1);
 529         nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
 530 }
 531 
 532 /*
 533  * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 534  *  - Save SLPM registers
 535  *  - Set SLPM=0 for the IOs you want to switch and others to 1
 536  *  - Configure the GPIO registers for the IOs that are being switched
 537  *  - Set IOFORCE=1
 538  *  - Modify the AFLSA/B registers for the IOs that are being switched
 539  *  - Set IOFORCE=0
 540  *  - Restore SLPM registers
 541  *  - Any spurious wake up event during switch sequence to be ignored and
 542  *    cleared
 543  */
 544 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
 545 {
 546         int i;
 547 
 548         for (i = 0; i < NUM_BANKS; i++) {
 549                 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 550                 unsigned int temp = slpm[i];
 551 
 552                 if (!chip)
 553                         break;
 554 
 555                 clk_enable(chip->clk);
 556 
 557                 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
 558                 writel(temp, chip->addr + NMK_GPIO_SLPC);
 559         }
 560 }
 561 
 562 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
 563 {
 564         int i;
 565 
 566         for (i = 0; i < NUM_BANKS; i++) {
 567                 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 568 
 569                 if (!chip)
 570                         break;
 571 
 572                 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
 573 
 574                 clk_disable(chip->clk);
 575         }
 576 }
 577 
 578 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
 579 {
 580         int i;
 581         u16 reg;
 582         u8 bit;
 583         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 584         const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 585         const u16 *gpiocr_regs;
 586 
 587         if (!npct->prcm_base)
 588                 return NMK_GPIO_ALT_C;
 589 
 590         for (i = 0; i < npct->soc->npins_altcx; i++) {
 591                 if (npct->soc->altcx_pins[i].pin == gpio)
 592                         break;
 593         }
 594         if (i == npct->soc->npins_altcx)
 595                 return NMK_GPIO_ALT_C;
 596 
 597         pin_desc = npct->soc->altcx_pins + i;
 598         gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 599         for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
 600                 if (pin_desc->altcx[i].used == true) {
 601                         reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 602                         bit = pin_desc->altcx[i].control_bit;
 603                         if (readl(npct->prcm_base + reg) & BIT(bit))
 604                                 return NMK_GPIO_ALT_C+i+1;
 605                 }
 606         }
 607         return NMK_GPIO_ALT_C;
 608 }
 609 
 610 /* IRQ functions */
 611 
 612 static void nmk_gpio_irq_ack(struct irq_data *d)
 613 {
 614         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 615         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 616 
 617         clk_enable(nmk_chip->clk);
 618         writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
 619         clk_disable(nmk_chip->clk);
 620 }
 621 
 622 enum nmk_gpio_irq_type {
 623         NORMAL,
 624         WAKE,
 625 };
 626 
 627 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
 628                                   int offset, enum nmk_gpio_irq_type which,
 629                                   bool enable)
 630 {
 631         u32 *rimscval;
 632         u32 *fimscval;
 633         u32 rimscreg;
 634         u32 fimscreg;
 635 
 636         if (which == NORMAL) {
 637                 rimscreg = NMK_GPIO_RIMSC;
 638                 fimscreg = NMK_GPIO_FIMSC;
 639                 rimscval = &nmk_chip->rimsc;
 640                 fimscval = &nmk_chip->fimsc;
 641         } else  {
 642                 rimscreg = NMK_GPIO_RWIMSC;
 643                 fimscreg = NMK_GPIO_FWIMSC;
 644                 rimscval = &nmk_chip->rwimsc;
 645                 fimscval = &nmk_chip->fwimsc;
 646         }
 647 
 648         /* we must individually set/clear the two edges */
 649         if (nmk_chip->edge_rising & BIT(offset)) {
 650                 if (enable)
 651                         *rimscval |= BIT(offset);
 652                 else
 653                         *rimscval &= ~BIT(offset);
 654                 writel(*rimscval, nmk_chip->addr + rimscreg);
 655         }
 656         if (nmk_chip->edge_falling & BIT(offset)) {
 657                 if (enable)
 658                         *fimscval |= BIT(offset);
 659                 else
 660                         *fimscval &= ~BIT(offset);
 661                 writel(*fimscval, nmk_chip->addr + fimscreg);
 662         }
 663 }
 664 
 665 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
 666                                 int offset, bool on)
 667 {
 668         /*
 669          * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
 670          * disabled, since setting SLPM to 1 increases power consumption, and
 671          * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
 672          */
 673         if (nmk_chip->sleepmode && on) {
 674                 __nmk_gpio_set_slpm(nmk_chip, offset,
 675                                     NMK_GPIO_SLPM_WAKEUP_ENABLE);
 676         }
 677 
 678         __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
 679 }
 680 
 681 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
 682 {
 683         struct nmk_gpio_chip *nmk_chip;
 684         unsigned long flags;
 685 
 686         nmk_chip = irq_data_get_irq_chip_data(d);
 687         if (!nmk_chip)
 688                 return -EINVAL;
 689 
 690         clk_enable(nmk_chip->clk);
 691         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 692         spin_lock(&nmk_chip->lock);
 693 
 694         __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
 695 
 696         if (!(nmk_chip->real_wake & BIT(d->hwirq)))
 697                 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
 698 
 699         spin_unlock(&nmk_chip->lock);
 700         spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 701         clk_disable(nmk_chip->clk);
 702 
 703         return 0;
 704 }
 705 
 706 static void nmk_gpio_irq_mask(struct irq_data *d)
 707 {
 708         nmk_gpio_irq_maskunmask(d, false);
 709 }
 710 
 711 static void nmk_gpio_irq_unmask(struct irq_data *d)
 712 {
 713         nmk_gpio_irq_maskunmask(d, true);
 714 }
 715 
 716 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 717 {
 718         struct nmk_gpio_chip *nmk_chip;
 719         unsigned long flags;
 720 
 721         nmk_chip = irq_data_get_irq_chip_data(d);
 722         if (!nmk_chip)
 723                 return -EINVAL;
 724 
 725         clk_enable(nmk_chip->clk);
 726         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 727         spin_lock(&nmk_chip->lock);
 728 
 729         if (irqd_irq_disabled(d))
 730                 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
 731 
 732         if (on)
 733                 nmk_chip->real_wake |= BIT(d->hwirq);
 734         else
 735                 nmk_chip->real_wake &= ~BIT(d->hwirq);
 736 
 737         spin_unlock(&nmk_chip->lock);
 738         spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 739         clk_disable(nmk_chip->clk);
 740 
 741         return 0;
 742 }
 743 
 744 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 745 {
 746         bool enabled = !irqd_irq_disabled(d);
 747         bool wake = irqd_is_wakeup_set(d);
 748         struct nmk_gpio_chip *nmk_chip;
 749         unsigned long flags;
 750 
 751         nmk_chip = irq_data_get_irq_chip_data(d);
 752         if (!nmk_chip)
 753                 return -EINVAL;
 754         if (type & IRQ_TYPE_LEVEL_HIGH)
 755                 return -EINVAL;
 756         if (type & IRQ_TYPE_LEVEL_LOW)
 757                 return -EINVAL;
 758 
 759         clk_enable(nmk_chip->clk);
 760         spin_lock_irqsave(&nmk_chip->lock, flags);
 761 
 762         if (enabled)
 763                 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
 764 
 765         if (enabled || wake)
 766                 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
 767 
 768         nmk_chip->edge_rising &= ~BIT(d->hwirq);
 769         if (type & IRQ_TYPE_EDGE_RISING)
 770                 nmk_chip->edge_rising |= BIT(d->hwirq);
 771 
 772         nmk_chip->edge_falling &= ~BIT(d->hwirq);
 773         if (type & IRQ_TYPE_EDGE_FALLING)
 774                 nmk_chip->edge_falling |= BIT(d->hwirq);
 775 
 776         if (enabled)
 777                 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
 778 
 779         if (enabled || wake)
 780                 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
 781 
 782         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 783         clk_disable(nmk_chip->clk);
 784 
 785         return 0;
 786 }
 787 
 788 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
 789 {
 790         struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
 791 
 792         clk_enable(nmk_chip->clk);
 793         nmk_gpio_irq_unmask(d);
 794         return 0;
 795 }
 796 
 797 static void nmk_gpio_irq_shutdown(struct irq_data *d)
 798 {
 799         struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
 800 
 801         nmk_gpio_irq_mask(d);
 802         clk_disable(nmk_chip->clk);
 803 }
 804 
 805 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
 806 {
 807         struct irq_chip *host_chip = irq_desc_get_chip(desc);
 808         struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 809 
 810         chained_irq_enter(host_chip, desc);
 811 
 812         while (status) {
 813                 int bit = __ffs(status);
 814 
 815                 generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
 816                 status &= ~BIT(bit);
 817         }
 818 
 819         chained_irq_exit(host_chip, desc);
 820 }
 821 
 822 static void nmk_gpio_irq_handler(struct irq_desc *desc)
 823 {
 824         struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 825         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 826         u32 status;
 827 
 828         clk_enable(nmk_chip->clk);
 829         status = readl(nmk_chip->addr + NMK_GPIO_IS);
 830         clk_disable(nmk_chip->clk);
 831 
 832         __nmk_gpio_irq_handler(desc, status);
 833 }
 834 
 835 static void nmk_gpio_latent_irq_handler(struct irq_desc *desc)
 836 {
 837         struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 838         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 839         u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
 840 
 841         __nmk_gpio_irq_handler(desc, status);
 842 }
 843 
 844 /* I/O Functions */
 845 
 846 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
 847 {
 848         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 849         int dir;
 850 
 851         clk_enable(nmk_chip->clk);
 852 
 853         dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
 854 
 855         clk_disable(nmk_chip->clk);
 856 
 857         return dir;
 858 }
 859 
 860 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
 861 {
 862         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 863 
 864         clk_enable(nmk_chip->clk);
 865 
 866         writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
 867 
 868         clk_disable(nmk_chip->clk);
 869 
 870         return 0;
 871 }
 872 
 873 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
 874 {
 875         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 876         int value;
 877 
 878         clk_enable(nmk_chip->clk);
 879 
 880         value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
 881 
 882         clk_disable(nmk_chip->clk);
 883 
 884         return value;
 885 }
 886 
 887 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
 888                                 int val)
 889 {
 890         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 891 
 892         clk_enable(nmk_chip->clk);
 893 
 894         __nmk_gpio_set_output(nmk_chip, offset, val);
 895 
 896         clk_disable(nmk_chip->clk);
 897 }
 898 
 899 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
 900                                 int val)
 901 {
 902         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 903 
 904         clk_enable(nmk_chip->clk);
 905 
 906         __nmk_gpio_make_output(nmk_chip, offset, val);
 907 
 908         clk_disable(nmk_chip->clk);
 909 
 910         return 0;
 911 }
 912 
 913 #ifdef CONFIG_DEBUG_FS
 914 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
 915 {
 916         u32 afunc, bfunc;
 917 
 918         clk_enable(nmk_chip->clk);
 919 
 920         afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
 921         bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
 922 
 923         clk_disable(nmk_chip->clk);
 924 
 925         return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
 926 }
 927 
 928 #include <linux/seq_file.h>
 929 
 930 static void nmk_gpio_dbg_show_one(struct seq_file *s,
 931         struct pinctrl_dev *pctldev, struct gpio_chip *chip,
 932         unsigned offset, unsigned gpio)
 933 {
 934         const char *label = gpiochip_is_requested(chip, offset);
 935         struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
 936         int mode;
 937         bool is_out;
 938         bool data_out;
 939         bool pull;
 940         const char *modes[] = {
 941                 [NMK_GPIO_ALT_GPIO]     = "gpio",
 942                 [NMK_GPIO_ALT_A]        = "altA",
 943                 [NMK_GPIO_ALT_B]        = "altB",
 944                 [NMK_GPIO_ALT_C]        = "altC",
 945                 [NMK_GPIO_ALT_C+1]      = "altC1",
 946                 [NMK_GPIO_ALT_C+2]      = "altC2",
 947                 [NMK_GPIO_ALT_C+3]      = "altC3",
 948                 [NMK_GPIO_ALT_C+4]      = "altC4",
 949         };
 950         const char *pulls[] = {
 951                 "none     ",
 952                 "pull down",
 953                 "pull up  ",
 954         };
 955 
 956         clk_enable(nmk_chip->clk);
 957         is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
 958         pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
 959         data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
 960         mode = nmk_gpio_get_mode(nmk_chip, offset);
 961         if ((mode == NMK_GPIO_ALT_C) && pctldev)
 962                 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
 963 
 964         if (is_out) {
 965                 seq_printf(s, " gpio-%-3d (%-20.20s) out %s        %s",
 966                            gpio,
 967                            label ?: "(none)",
 968                            data_out ? "hi" : "lo",
 969                            (mode < 0) ? "unknown" : modes[mode]);
 970         } else {
 971                 int irq = chip->to_irq(chip, offset);
 972                 struct irq_desc *desc = irq_to_desc(irq);
 973                 int pullidx = 0;
 974                 int val;
 975 
 976                 if (pull)
 977                         pullidx = data_out ? 2 : 1;
 978 
 979                 seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %s",
 980                            gpio,
 981                            label ?: "(none)",
 982                            pulls[pullidx],
 983                            (mode < 0) ? "unknown" : modes[mode]);
 984 
 985                 val = nmk_gpio_get_input(chip, offset);
 986                 seq_printf(s, " VAL %d", val);
 987 
 988                 /*
 989                  * This races with request_irq(), set_irq_type(),
 990                  * and set_irq_wake() ... but those are "rare".
 991                  */
 992                 if (irq > 0 && desc && desc->action) {
 993                         char *trigger;
 994 
 995                         if (nmk_chip->edge_rising & BIT(offset))
 996                                 trigger = "edge-rising";
 997                         else if (nmk_chip->edge_falling & BIT(offset))
 998                                 trigger = "edge-falling";
 999                         else
1000                                 trigger = "edge-undefined";
1001 
1002                         seq_printf(s, " irq-%d %s%s",
1003                                    irq, trigger,
1004                                    irqd_is_wakeup_set(&desc->irq_data)
1005                                    ? " wakeup" : "");
1006                 }
1007         }
1008         clk_disable(nmk_chip->clk);
1009 }
1010 
1011 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1012 {
1013         unsigned                i;
1014         unsigned                gpio = chip->base;
1015 
1016         for (i = 0; i < chip->ngpio; i++, gpio++) {
1017                 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1018                 seq_printf(s, "\n");
1019         }
1020 }
1021 
1022 #else
1023 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1024                                          struct pinctrl_dev *pctldev,
1025                                          struct gpio_chip *chip,
1026                                          unsigned offset, unsigned gpio)
1027 {
1028 }
1029 #define nmk_gpio_dbg_show       NULL
1030 #endif
1031 
1032 /*
1033  * We will allocate memory for the state container using devm* allocators
1034  * binding to the first device reaching this point, it doesn't matter if
1035  * it is the pin controller or GPIO driver. However we need to use the right
1036  * platform device when looking up resources so pay attention to pdev.
1037  */
1038 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1039                                                 struct platform_device *pdev)
1040 {
1041         struct nmk_gpio_chip *nmk_chip;
1042         struct platform_device *gpio_pdev;
1043         struct gpio_chip *chip;
1044         struct resource *res;
1045         struct clk *clk;
1046         void __iomem *base;
1047         u32 id;
1048 
1049         gpio_pdev = of_find_device_by_node(np);
1050         if (!gpio_pdev) {
1051                 pr_err("populate \"%pOFn\": device not found\n", np);
1052                 return ERR_PTR(-ENODEV);
1053         }
1054         if (of_property_read_u32(np, "gpio-bank", &id)) {
1055                 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1056                 platform_device_put(gpio_pdev);
1057                 return ERR_PTR(-EINVAL);
1058         }
1059 
1060         /* Already populated? */
1061         nmk_chip = nmk_gpio_chips[id];
1062         if (nmk_chip) {
1063                 platform_device_put(gpio_pdev);
1064                 return nmk_chip;
1065         }
1066 
1067         nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1068         if (!nmk_chip) {
1069                 platform_device_put(gpio_pdev);
1070                 return ERR_PTR(-ENOMEM);
1071         }
1072 
1073         nmk_chip->bank = id;
1074         chip = &nmk_chip->chip;
1075         chip->base = id * NMK_GPIO_PER_CHIP;
1076         chip->ngpio = NMK_GPIO_PER_CHIP;
1077         chip->label = dev_name(&gpio_pdev->dev);
1078         chip->parent = &gpio_pdev->dev;
1079 
1080         res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1081         base = devm_ioremap_resource(&pdev->dev, res);
1082         if (IS_ERR(base)) {
1083                 platform_device_put(gpio_pdev);
1084                 return ERR_CAST(base);
1085         }
1086         nmk_chip->addr = base;
1087 
1088         clk = clk_get(&gpio_pdev->dev, NULL);
1089         if (IS_ERR(clk)) {
1090                 platform_device_put(gpio_pdev);
1091                 return (void *) clk;
1092         }
1093         clk_prepare(clk);
1094         nmk_chip->clk = clk;
1095 
1096         BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1097         nmk_gpio_chips[id] = nmk_chip;
1098         return nmk_chip;
1099 }
1100 
1101 static int nmk_gpio_probe(struct platform_device *dev)
1102 {
1103         struct device_node *np = dev->dev.of_node;
1104         struct nmk_gpio_chip *nmk_chip;
1105         struct gpio_chip *chip;
1106         struct irq_chip *irqchip;
1107         int latent_irq;
1108         bool supports_sleepmode;
1109         int irq;
1110         int ret;
1111 
1112         nmk_chip = nmk_gpio_populate_chip(np, dev);
1113         if (IS_ERR(nmk_chip)) {
1114                 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1115                 return PTR_ERR(nmk_chip);
1116         }
1117 
1118         supports_sleepmode =
1119                 of_property_read_bool(np, "st,supports-sleepmode");
1120 
1121         /* Correct platform device ID */
1122         dev->id = nmk_chip->bank;
1123 
1124         irq = platform_get_irq(dev, 0);
1125         if (irq < 0)
1126                 return irq;
1127 
1128         /* It's OK for this IRQ not to be present */
1129         latent_irq = platform_get_irq(dev, 1);
1130 
1131         /*
1132          * The virt address in nmk_chip->addr is in the nomadik register space,
1133          * so we can simply convert the resource address, without remapping
1134          */
1135         nmk_chip->parent_irq = irq;
1136         nmk_chip->latent_parent_irq = latent_irq;
1137         nmk_chip->sleepmode = supports_sleepmode;
1138         spin_lock_init(&nmk_chip->lock);
1139 
1140         chip = &nmk_chip->chip;
1141         chip->request = gpiochip_generic_request;
1142         chip->free = gpiochip_generic_free;
1143         chip->get_direction = nmk_gpio_get_dir;
1144         chip->direction_input = nmk_gpio_make_input;
1145         chip->get = nmk_gpio_get_input;
1146         chip->direction_output = nmk_gpio_make_output;
1147         chip->set = nmk_gpio_set_output;
1148         chip->dbg_show = nmk_gpio_dbg_show;
1149         chip->can_sleep = false;
1150         chip->owner = THIS_MODULE;
1151 
1152         irqchip = &nmk_chip->irqchip;
1153         irqchip->irq_ack = nmk_gpio_irq_ack;
1154         irqchip->irq_mask = nmk_gpio_irq_mask;
1155         irqchip->irq_unmask = nmk_gpio_irq_unmask;
1156         irqchip->irq_set_type = nmk_gpio_irq_set_type;
1157         irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1158         irqchip->irq_startup = nmk_gpio_irq_startup;
1159         irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1160         irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1161         irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1162                                   dev->id,
1163                                   chip->base,
1164                                   chip->base + chip->ngpio - 1);
1165 
1166         clk_enable(nmk_chip->clk);
1167         nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1168         clk_disable(nmk_chip->clk);
1169         chip->of_node = np;
1170 
1171         ret = gpiochip_add_data(chip, nmk_chip);
1172         if (ret)
1173                 return ret;
1174 
1175         platform_set_drvdata(dev, nmk_chip);
1176 
1177         /*
1178          * Let the generic code handle this edge IRQ, the the chained
1179          * handler will perform the actual work of handling the parent
1180          * interrupt.
1181          */
1182         ret = gpiochip_irqchip_add(chip,
1183                                    irqchip,
1184                                    0,
1185                                    handle_edge_irq,
1186                                    IRQ_TYPE_NONE);
1187         if (ret) {
1188                 dev_err(&dev->dev, "could not add irqchip\n");
1189                 gpiochip_remove(&nmk_chip->chip);
1190                 return -ENODEV;
1191         }
1192         /* Then register the chain on the parent IRQ */
1193         gpiochip_set_chained_irqchip(chip,
1194                                      irqchip,
1195                                      nmk_chip->parent_irq,
1196                                      nmk_gpio_irq_handler);
1197         if (nmk_chip->latent_parent_irq > 0)
1198                 gpiochip_set_chained_irqchip(chip,
1199                                              irqchip,
1200                                              nmk_chip->latent_parent_irq,
1201                                              nmk_gpio_latent_irq_handler);
1202 
1203         dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1204 
1205         return 0;
1206 }
1207 
1208 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1209 {
1210         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1211 
1212         return npct->soc->ngroups;
1213 }
1214 
1215 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1216                                        unsigned selector)
1217 {
1218         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1219 
1220         return npct->soc->groups[selector].name;
1221 }
1222 
1223 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1224                               const unsigned **pins,
1225                               unsigned *num_pins)
1226 {
1227         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1228 
1229         *pins = npct->soc->groups[selector].pins;
1230         *num_pins = npct->soc->groups[selector].npins;
1231         return 0;
1232 }
1233 
1234 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1235 {
1236         int i;
1237         struct nmk_gpio_chip *nmk_gpio;
1238 
1239         for(i = 0; i < NMK_MAX_BANKS; i++) {
1240                 nmk_gpio = nmk_gpio_chips[i];
1241                 if (!nmk_gpio)
1242                         continue;
1243                 if (pin >= nmk_gpio->chip.base &&
1244                         pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1245                         return nmk_gpio;
1246         }
1247         return NULL;
1248 }
1249 
1250 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1251 {
1252         struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1253 
1254         if (nmk_gpio)
1255                 return &nmk_gpio->chip;
1256         return NULL;
1257 }
1258 
1259 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1260                    unsigned offset)
1261 {
1262         struct gpio_chip *chip = find_gc_from_pin(offset);
1263 
1264         if (!chip) {
1265                 seq_printf(s, "invalid pin offset");
1266                 return;
1267         }
1268         nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1269 }
1270 
1271 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1272                 unsigned *num_maps, const char *group,
1273                 const char *function)
1274 {
1275         if (*num_maps == *reserved_maps)
1276                 return -ENOSPC;
1277 
1278         (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1279         (*map)[*num_maps].data.mux.group = group;
1280         (*map)[*num_maps].data.mux.function = function;
1281         (*num_maps)++;
1282 
1283         return 0;
1284 }
1285 
1286 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1287                 unsigned *reserved_maps,
1288                 unsigned *num_maps, const char *group,
1289                 unsigned long *configs, unsigned num_configs)
1290 {
1291         unsigned long *dup_configs;
1292 
1293         if (*num_maps == *reserved_maps)
1294                 return -ENOSPC;
1295 
1296         dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1297                               GFP_KERNEL);
1298         if (!dup_configs)
1299                 return -ENOMEM;
1300 
1301         (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1302 
1303         (*map)[*num_maps].data.configs.group_or_pin = group;
1304         (*map)[*num_maps].data.configs.configs = dup_configs;
1305         (*map)[*num_maps].data.configs.num_configs = num_configs;
1306         (*num_maps)++;
1307 
1308         return 0;
1309 }
1310 
1311 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1312 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1313         .size = ARRAY_SIZE(y), }
1314 
1315 static const unsigned long nmk_pin_input_modes[] = {
1316         PIN_INPUT_NOPULL,
1317         PIN_INPUT_PULLUP,
1318         PIN_INPUT_PULLDOWN,
1319 };
1320 
1321 static const unsigned long nmk_pin_output_modes[] = {
1322         PIN_OUTPUT_LOW,
1323         PIN_OUTPUT_HIGH,
1324         PIN_DIR_OUTPUT,
1325 };
1326 
1327 static const unsigned long nmk_pin_sleep_modes[] = {
1328         PIN_SLEEPMODE_DISABLED,
1329         PIN_SLEEPMODE_ENABLED,
1330 };
1331 
1332 static const unsigned long nmk_pin_sleep_input_modes[] = {
1333         PIN_SLPM_INPUT_NOPULL,
1334         PIN_SLPM_INPUT_PULLUP,
1335         PIN_SLPM_INPUT_PULLDOWN,
1336         PIN_SLPM_DIR_INPUT,
1337 };
1338 
1339 static const unsigned long nmk_pin_sleep_output_modes[] = {
1340         PIN_SLPM_OUTPUT_LOW,
1341         PIN_SLPM_OUTPUT_HIGH,
1342         PIN_SLPM_DIR_OUTPUT,
1343 };
1344 
1345 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1346         PIN_SLPM_WAKEUP_DISABLE,
1347         PIN_SLPM_WAKEUP_ENABLE,
1348 };
1349 
1350 static const unsigned long nmk_pin_gpio_modes[] = {
1351         PIN_GPIOMODE_DISABLED,
1352         PIN_GPIOMODE_ENABLED,
1353 };
1354 
1355 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1356         PIN_SLPM_PDIS_DISABLED,
1357         PIN_SLPM_PDIS_ENABLED,
1358 };
1359 
1360 struct nmk_cfg_param {
1361         const char *property;
1362         unsigned long config;
1363         const unsigned long *choice;
1364         int size;
1365 };
1366 
1367 static const struct nmk_cfg_param nmk_cfg_params[] = {
1368         NMK_CONFIG_PIN_ARRAY("ste,input",               nmk_pin_input_modes),
1369         NMK_CONFIG_PIN_ARRAY("ste,output",              nmk_pin_output_modes),
1370         NMK_CONFIG_PIN_ARRAY("ste,sleep",               nmk_pin_sleep_modes),
1371         NMK_CONFIG_PIN_ARRAY("ste,sleep-input",         nmk_pin_sleep_input_modes),
1372         NMK_CONFIG_PIN_ARRAY("ste,sleep-output",        nmk_pin_sleep_output_modes),
1373         NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup",        nmk_pin_sleep_wakeup_modes),
1374         NMK_CONFIG_PIN_ARRAY("ste,gpio",                nmk_pin_gpio_modes),
1375         NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable",  nmk_pin_sleep_pdis_modes),
1376 };
1377 
1378 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1379 {
1380         int ret = 0;
1381 
1382         if (nmk_cfg_params[index].choice == NULL)
1383                 *config = nmk_cfg_params[index].config;
1384         else {
1385                 /* test if out of range */
1386                 if  (val < nmk_cfg_params[index].size) {
1387                         *config = nmk_cfg_params[index].config |
1388                                 nmk_cfg_params[index].choice[val];
1389                 }
1390         }
1391         return ret;
1392 }
1393 
1394 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1395 {
1396         int i, pin_number;
1397         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1398 
1399         if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1400                 for (i = 0; i < npct->soc->npins; i++)
1401                         if (npct->soc->pins[i].number == pin_number)
1402                                 return npct->soc->pins[i].name;
1403         return NULL;
1404 }
1405 
1406 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1407                 unsigned long *configs)
1408 {
1409         bool has_config = 0;
1410         unsigned long cfg = 0;
1411         int i, val, ret;
1412 
1413         for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1414                 ret = of_property_read_u32(np,
1415                                 nmk_cfg_params[i].property, &val);
1416                 if (ret != -EINVAL) {
1417                         if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1418                                 *configs |= cfg;
1419                                 has_config = 1;
1420                         }
1421                 }
1422         }
1423 
1424         return has_config;
1425 }
1426 
1427 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1428                 struct device_node *np,
1429                 struct pinctrl_map **map,
1430                 unsigned *reserved_maps,
1431                 unsigned *num_maps)
1432 {
1433         int ret;
1434         const char *function = NULL;
1435         unsigned long configs = 0;
1436         bool has_config = 0;
1437         struct property *prop;
1438         struct device_node *np_config;
1439 
1440         ret = of_property_read_string(np, "function", &function);
1441         if (ret >= 0) {
1442                 const char *group;
1443 
1444                 ret = of_property_count_strings(np, "groups");
1445                 if (ret < 0)
1446                         goto exit;
1447 
1448                 ret = pinctrl_utils_reserve_map(pctldev, map,
1449                                                 reserved_maps,
1450                                                 num_maps, ret);
1451                 if (ret < 0)
1452                         goto exit;
1453 
1454                 of_property_for_each_string(np, "groups", prop, group) {
1455                         ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1456                                           group, function);
1457                         if (ret < 0)
1458                                 goto exit;
1459                 }
1460         }
1461 
1462         has_config = nmk_pinctrl_dt_get_config(np, &configs);
1463         np_config = of_parse_phandle(np, "ste,config", 0);
1464         if (np_config)
1465                 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1466         if (has_config) {
1467                 const char *gpio_name;
1468                 const char *pin;
1469 
1470                 ret = of_property_count_strings(np, "pins");
1471                 if (ret < 0)
1472                         goto exit;
1473                 ret = pinctrl_utils_reserve_map(pctldev, map,
1474                                                 reserved_maps,
1475                                                 num_maps, ret);
1476                 if (ret < 0)
1477                         goto exit;
1478 
1479                 of_property_for_each_string(np, "pins", prop, pin) {
1480                         gpio_name = nmk_find_pin_name(pctldev, pin);
1481 
1482                         ret = nmk_dt_add_map_configs(map, reserved_maps,
1483                                                      num_maps,
1484                                                      gpio_name, &configs, 1);
1485                         if (ret < 0)
1486                                 goto exit;
1487                 }
1488         }
1489 
1490 exit:
1491         return ret;
1492 }
1493 
1494 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1495                                  struct device_node *np_config,
1496                                  struct pinctrl_map **map, unsigned *num_maps)
1497 {
1498         unsigned reserved_maps;
1499         struct device_node *np;
1500         int ret;
1501 
1502         reserved_maps = 0;
1503         *map = NULL;
1504         *num_maps = 0;
1505 
1506         for_each_child_of_node(np_config, np) {
1507                 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1508                                 &reserved_maps, num_maps);
1509                 if (ret < 0) {
1510                         pinctrl_utils_free_map(pctldev, *map, *num_maps);
1511                         of_node_put(np);
1512                         return ret;
1513                 }
1514         }
1515 
1516         return 0;
1517 }
1518 
1519 static const struct pinctrl_ops nmk_pinctrl_ops = {
1520         .get_groups_count = nmk_get_groups_cnt,
1521         .get_group_name = nmk_get_group_name,
1522         .get_group_pins = nmk_get_group_pins,
1523         .pin_dbg_show = nmk_pin_dbg_show,
1524         .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1525         .dt_free_map = pinctrl_utils_free_map,
1526 };
1527 
1528 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1529 {
1530         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1531 
1532         return npct->soc->nfunctions;
1533 }
1534 
1535 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1536                                          unsigned function)
1537 {
1538         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1539 
1540         return npct->soc->functions[function].name;
1541 }
1542 
1543 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1544                                    unsigned function,
1545                                    const char * const **groups,
1546                                    unsigned * const num_groups)
1547 {
1548         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1549 
1550         *groups = npct->soc->functions[function].groups;
1551         *num_groups = npct->soc->functions[function].ngroups;
1552 
1553         return 0;
1554 }
1555 
1556 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1557                        unsigned group)
1558 {
1559         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1560         const struct nmk_pingroup *g;
1561         static unsigned int slpm[NUM_BANKS];
1562         unsigned long flags = 0;
1563         bool glitch;
1564         int ret = -EINVAL;
1565         int i;
1566 
1567         g = &npct->soc->groups[group];
1568 
1569         if (g->altsetting < 0)
1570                 return -EINVAL;
1571 
1572         dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1573 
1574         /*
1575          * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1576          * we may pass through an undesired state. In this case we take
1577          * some extra care.
1578          *
1579          * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1580          *  - Save SLPM registers (since we have a shadow register in the
1581          *    nmk_chip we're using that as backup)
1582          *  - Set SLPM=0 for the IOs you want to switch and others to 1
1583          *  - Configure the GPIO registers for the IOs that are being switched
1584          *  - Set IOFORCE=1
1585          *  - Modify the AFLSA/B registers for the IOs that are being switched
1586          *  - Set IOFORCE=0
1587          *  - Restore SLPM registers
1588          *  - Any spurious wake up event during switch sequence to be ignored
1589          *    and cleared
1590          *
1591          * We REALLY need to save ALL slpm registers, because the external
1592          * IOFORCE will switch *all* ports to their sleepmode setting to as
1593          * to avoid glitches. (Not just one port!)
1594          */
1595         glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1596 
1597         if (glitch) {
1598                 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1599 
1600                 /* Initially don't put any pins to sleep when switching */
1601                 memset(slpm, 0xff, sizeof(slpm));
1602 
1603                 /*
1604                  * Then mask the pins that need to be sleeping now when we're
1605                  * switching to the ALT C function.
1606                  */
1607                 for (i = 0; i < g->npins; i++)
1608                         slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1609                 nmk_gpio_glitch_slpm_init(slpm);
1610         }
1611 
1612         for (i = 0; i < g->npins; i++) {
1613                 struct nmk_gpio_chip *nmk_chip;
1614                 unsigned bit;
1615 
1616                 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1617                 if (!nmk_chip) {
1618                         dev_err(npct->dev,
1619                                 "invalid pin offset %d in group %s at index %d\n",
1620                                 g->pins[i], g->name, i);
1621                         goto out_glitch;
1622                 }
1623                 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1624 
1625                 clk_enable(nmk_chip->clk);
1626                 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1627                 /*
1628                  * If the pin is switching to altfunc, and there was an
1629                  * interrupt installed on it which has been lazy disabled,
1630                  * actually mask the interrupt to prevent spurious interrupts
1631                  * that would occur while the pin is under control of the
1632                  * peripheral. Only SKE does this.
1633                  */
1634                 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1635 
1636                 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1637                         (g->altsetting & NMK_GPIO_ALT_C), glitch);
1638                 clk_disable(nmk_chip->clk);
1639 
1640                 /*
1641                  * Call PRCM GPIOCR config function in case ALTC
1642                  * has been selected:
1643                  * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1644                  *   must be set.
1645                  * - If selection is pure ALTC and previous selection was ALTCx,
1646                  *   then some bits in PRCM GPIOCR registers must be cleared.
1647                  */
1648                 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1649                         nmk_prcm_altcx_set_mode(npct, g->pins[i],
1650                                 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1651         }
1652 
1653         /* When all pins are successfully reconfigured we get here */
1654         ret = 0;
1655 
1656 out_glitch:
1657         if (glitch) {
1658                 nmk_gpio_glitch_slpm_restore(slpm);
1659                 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1660         }
1661 
1662         return ret;
1663 }
1664 
1665 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1666                                    struct pinctrl_gpio_range *range,
1667                                    unsigned offset)
1668 {
1669         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1670         struct nmk_gpio_chip *nmk_chip;
1671         struct gpio_chip *chip;
1672         unsigned bit;
1673 
1674         if (!range) {
1675                 dev_err(npct->dev, "invalid range\n");
1676                 return -EINVAL;
1677         }
1678         if (!range->gc) {
1679                 dev_err(npct->dev, "missing GPIO chip in range\n");
1680                 return -EINVAL;
1681         }
1682         chip = range->gc;
1683         nmk_chip = gpiochip_get_data(chip);
1684 
1685         dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1686 
1687         clk_enable(nmk_chip->clk);
1688         bit = offset % NMK_GPIO_PER_CHIP;
1689         /* There is no glitch when converting any pin to GPIO */
1690         __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1691         clk_disable(nmk_chip->clk);
1692 
1693         return 0;
1694 }
1695 
1696 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1697                                   struct pinctrl_gpio_range *range,
1698                                   unsigned offset)
1699 {
1700         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1701 
1702         dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1703         /* Set the pin to some default state, GPIO is usually default */
1704 }
1705 
1706 static const struct pinmux_ops nmk_pinmux_ops = {
1707         .get_functions_count = nmk_pmx_get_funcs_cnt,
1708         .get_function_name = nmk_pmx_get_func_name,
1709         .get_function_groups = nmk_pmx_get_func_groups,
1710         .set_mux = nmk_pmx_set,
1711         .gpio_request_enable = nmk_gpio_request_enable,
1712         .gpio_disable_free = nmk_gpio_disable_free,
1713         .strict = true,
1714 };
1715 
1716 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1717                               unsigned long *config)
1718 {
1719         /* Not implemented */
1720         return -EINVAL;
1721 }
1722 
1723 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1724                               unsigned long *configs, unsigned num_configs)
1725 {
1726         static const char *pullnames[] = {
1727                 [NMK_GPIO_PULL_NONE]    = "none",
1728                 [NMK_GPIO_PULL_UP]      = "up",
1729                 [NMK_GPIO_PULL_DOWN]    = "down",
1730                 [3] /* illegal */       = "??"
1731         };
1732         static const char *slpmnames[] = {
1733                 [NMK_GPIO_SLPM_INPUT]           = "input/wakeup",
1734                 [NMK_GPIO_SLPM_NOCHANGE]        = "no-change/no-wakeup",
1735         };
1736         struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1737         struct nmk_gpio_chip *nmk_chip;
1738         unsigned bit;
1739         pin_cfg_t cfg;
1740         int pull, slpm, output, val, i;
1741         bool lowemi, gpiomode, sleep;
1742 
1743         nmk_chip = find_nmk_gpio_from_pin(pin);
1744         if (!nmk_chip) {
1745                 dev_err(npct->dev,
1746                         "invalid pin offset %d\n", pin);
1747                 return -EINVAL;
1748         }
1749 
1750         for (i = 0; i < num_configs; i++) {
1751                 /*
1752                  * The pin config contains pin number and altfunction fields,
1753                  * here we just ignore that part. It's being handled by the
1754                  * framework and pinmux callback respectively.
1755                  */
1756                 cfg = (pin_cfg_t) configs[i];
1757                 pull = PIN_PULL(cfg);
1758                 slpm = PIN_SLPM(cfg);
1759                 output = PIN_DIR(cfg);
1760                 val = PIN_VAL(cfg);
1761                 lowemi = PIN_LOWEMI(cfg);
1762                 gpiomode = PIN_GPIOMODE(cfg);
1763                 sleep = PIN_SLEEPMODE(cfg);
1764 
1765                 if (sleep) {
1766                         int slpm_pull = PIN_SLPM_PULL(cfg);
1767                         int slpm_output = PIN_SLPM_DIR(cfg);
1768                         int slpm_val = PIN_SLPM_VAL(cfg);
1769 
1770                         /* All pins go into GPIO mode at sleep */
1771                         gpiomode = true;
1772 
1773                         /*
1774                          * The SLPM_* values are normal values + 1 to allow zero
1775                          * to mean "same as normal".
1776                          */
1777                         if (slpm_pull)
1778                                 pull = slpm_pull - 1;
1779                         if (slpm_output)
1780                                 output = slpm_output - 1;
1781                         if (slpm_val)
1782                                 val = slpm_val - 1;
1783 
1784                         dev_dbg(nmk_chip->chip.parent,
1785                                 "pin %d: sleep pull %s, dir %s, val %s\n",
1786                                 pin,
1787                                 slpm_pull ? pullnames[pull] : "same",
1788                                 slpm_output ? (output ? "output" : "input")
1789                                 : "same",
1790                                 slpm_val ? (val ? "high" : "low") : "same");
1791                 }
1792 
1793                 dev_dbg(nmk_chip->chip.parent,
1794                         "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1795                         pin, cfg, pullnames[pull], slpmnames[slpm],
1796                         output ? "output " : "input",
1797                         output ? (val ? "high" : "low") : "",
1798                         lowemi ? "on" : "off");
1799 
1800                 clk_enable(nmk_chip->clk);
1801                 bit = pin % NMK_GPIO_PER_CHIP;
1802                 if (gpiomode)
1803                         /* No glitch when going to GPIO mode */
1804                         __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1805                 if (output)
1806                         __nmk_gpio_make_output(nmk_chip, bit, val);
1807                 else {
1808                         __nmk_gpio_make_input(nmk_chip, bit);
1809                         __nmk_gpio_set_pull(nmk_chip, bit, pull);
1810                 }
1811                 /* TODO: isn't this only applicable on output pins? */
1812                 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1813 
1814                 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1815                 clk_disable(nmk_chip->clk);
1816         } /* for each config */
1817 
1818         return 0;
1819 }
1820 
1821 static const struct pinconf_ops nmk_pinconf_ops = {
1822         .pin_config_get = nmk_pin_config_get,
1823         .pin_config_set = nmk_pin_config_set,
1824 };
1825 
1826 static struct pinctrl_desc nmk_pinctrl_desc = {
1827         .name = "pinctrl-nomadik",
1828         .pctlops = &nmk_pinctrl_ops,
1829         .pmxops = &nmk_pinmux_ops,
1830         .confops = &nmk_pinconf_ops,
1831         .owner = THIS_MODULE,
1832 };
1833 
1834 static const struct of_device_id nmk_pinctrl_match[] = {
1835         {
1836                 .compatible = "stericsson,stn8815-pinctrl",
1837                 .data = (void *)PINCTRL_NMK_STN8815,
1838         },
1839         {
1840                 .compatible = "stericsson,db8500-pinctrl",
1841                 .data = (void *)PINCTRL_NMK_DB8500,
1842         },
1843         {
1844                 .compatible = "stericsson,db8540-pinctrl",
1845                 .data = (void *)PINCTRL_NMK_DB8540,
1846         },
1847         {},
1848 };
1849 
1850 #ifdef CONFIG_PM_SLEEP
1851 static int nmk_pinctrl_suspend(struct device *dev)
1852 {
1853         struct nmk_pinctrl *npct;
1854 
1855         npct = dev_get_drvdata(dev);
1856         if (!npct)
1857                 return -EINVAL;
1858 
1859         return pinctrl_force_sleep(npct->pctl);
1860 }
1861 
1862 static int nmk_pinctrl_resume(struct device *dev)
1863 {
1864         struct nmk_pinctrl *npct;
1865 
1866         npct = dev_get_drvdata(dev);
1867         if (!npct)
1868                 return -EINVAL;
1869 
1870         return pinctrl_force_default(npct->pctl);
1871 }
1872 #endif
1873 
1874 static int nmk_pinctrl_probe(struct platform_device *pdev)
1875 {
1876         const struct of_device_id *match;
1877         struct device_node *np = pdev->dev.of_node;
1878         struct device_node *prcm_np;
1879         struct nmk_pinctrl *npct;
1880         unsigned int version = 0;
1881         int i;
1882 
1883         npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1884         if (!npct)
1885                 return -ENOMEM;
1886 
1887         match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1888         if (!match)
1889                 return -ENODEV;
1890         version = (unsigned int) match->data;
1891 
1892         /* Poke in other ASIC variants here */
1893         if (version == PINCTRL_NMK_STN8815)
1894                 nmk_pinctrl_stn8815_init(&npct->soc);
1895         if (version == PINCTRL_NMK_DB8500)
1896                 nmk_pinctrl_db8500_init(&npct->soc);
1897         if (version == PINCTRL_NMK_DB8540)
1898                 nmk_pinctrl_db8540_init(&npct->soc);
1899 
1900         /*
1901          * Since we depend on the GPIO chips to provide clock and register base
1902          * for the pin control operations, make sure that we have these
1903          * populated before we continue. Follow the phandles to instantiate
1904          * them. The GPIO portion of the actual hardware may be probed before
1905          * or after this point: it shouldn't matter as the APIs are orthogonal.
1906          */
1907         for (i = 0; i < NMK_MAX_BANKS; i++) {
1908                 struct device_node *gpio_np;
1909                 struct nmk_gpio_chip *nmk_chip;
1910 
1911                 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1912                 if (gpio_np) {
1913                         dev_info(&pdev->dev,
1914                                  "populate NMK GPIO %d \"%pOFn\"\n",
1915                                  i, gpio_np);
1916                         nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1917                         if (IS_ERR(nmk_chip))
1918                                 dev_err(&pdev->dev,
1919                                         "could not populate nmk chip struct "
1920                                         "- continue anyway\n");
1921                         of_node_put(gpio_np);
1922                 }
1923         }
1924 
1925         prcm_np = of_parse_phandle(np, "prcm", 0);
1926         if (prcm_np)
1927                 npct->prcm_base = of_iomap(prcm_np, 0);
1928         if (!npct->prcm_base) {
1929                 if (version == PINCTRL_NMK_STN8815) {
1930                         dev_info(&pdev->dev,
1931                                  "No PRCM base, "
1932                                  "assuming no ALT-Cx control is available\n");
1933                 } else {
1934                         dev_err(&pdev->dev, "missing PRCM base address\n");
1935                         return -EINVAL;
1936                 }
1937         }
1938 
1939         nmk_pinctrl_desc.pins = npct->soc->pins;
1940         nmk_pinctrl_desc.npins = npct->soc->npins;
1941         npct->dev = &pdev->dev;
1942 
1943         npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1944         if (IS_ERR(npct->pctl)) {
1945                 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1946                 return PTR_ERR(npct->pctl);
1947         }
1948 
1949         platform_set_drvdata(pdev, npct);
1950         dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1951 
1952         return 0;
1953 }
1954 
1955 static const struct of_device_id nmk_gpio_match[] = {
1956         { .compatible = "st,nomadik-gpio", },
1957         {}
1958 };
1959 
1960 static struct platform_driver nmk_gpio_driver = {
1961         .driver = {
1962                 .name = "gpio",
1963                 .of_match_table = nmk_gpio_match,
1964         },
1965         .probe = nmk_gpio_probe,
1966 };
1967 
1968 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1969                         nmk_pinctrl_suspend,
1970                         nmk_pinctrl_resume);
1971 
1972 static struct platform_driver nmk_pinctrl_driver = {
1973         .driver = {
1974                 .name = "pinctrl-nomadik",
1975                 .of_match_table = nmk_pinctrl_match,
1976                 .pm = &nmk_pinctrl_pm_ops,
1977         },
1978         .probe = nmk_pinctrl_probe,
1979 };
1980 
1981 static int __init nmk_gpio_init(void)
1982 {
1983         return platform_driver_register(&nmk_gpio_driver);
1984 }
1985 subsys_initcall(nmk_gpio_init);
1986 
1987 static int __init nmk_pinctrl_init(void)
1988 {
1989         return platform_driver_register(&nmk_pinctrl_driver);
1990 }
1991 core_initcall(nmk_pinctrl_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pinctrl/nomadik/pinctrl-nomadik.c

DEFINITIONS
