drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c

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This source file includes following definitions.
sun9i_a80_pinctrl_probe
   1 /*
   2  * Allwinner A80 SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2014 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12 
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 
  19 #include "pinctrl-sunxi.h"
  20 
  21 static const struct sunxi_desc_pin sun9i_a80_pins[] = {
  22         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
  23                   SUNXI_FUNCTION(0x0, "gpio_in"),
  24                   SUNXI_FUNCTION(0x1, "gpio_out"),
  25                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXD3 */
  26                   SUNXI_FUNCTION(0x4, "uart1"),         /* TX */
  27                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
  28         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  29                   SUNXI_FUNCTION(0x0, "gpio_in"),
  30                   SUNXI_FUNCTION(0x1, "gpio_out"),
  31                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXD2 */
  32                   SUNXI_FUNCTION(0x4, "uart1"),         /* RX */
  33                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
  34         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  35                   SUNXI_FUNCTION(0x0, "gpio_in"),
  36                   SUNXI_FUNCTION(0x1, "gpio_out"),
  37                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXD1 */
  38                   SUNXI_FUNCTION(0x4, "uart1"),         /* RTS */
  39                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
  40         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
  41                   SUNXI_FUNCTION(0x0, "gpio_in"),
  42                   SUNXI_FUNCTION(0x1, "gpio_out"),
  43                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXD0 */
  44                   SUNXI_FUNCTION(0x4, "uart1"),         /* CTS */
  45                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
  46         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
  47                   SUNXI_FUNCTION(0x0, "gpio_in"),
  48                   SUNXI_FUNCTION(0x1, "gpio_out"),
  49                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXCK */
  50                   SUNXI_FUNCTION(0x4, "uart1"),         /* DTR */
  51                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
  52         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
  53                   SUNXI_FUNCTION(0x0, "gpio_in"),
  54                   SUNXI_FUNCTION(0x1, "gpio_out"),
  55                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXCTL */
  56                   SUNXI_FUNCTION(0x4, "uart1"),         /* DSR */
  57                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PA_EINT5 */
  58         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
  59                   SUNXI_FUNCTION(0x0, "gpio_in"),
  60                   SUNXI_FUNCTION(0x1, "gpio_out"),
  61                   SUNXI_FUNCTION(0x2, "gmac"),          /* RXERR */
  62                   SUNXI_FUNCTION(0x4, "uart1"),         /* DCD */
  63                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PA_EINT6 */
  64         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
  65                   SUNXI_FUNCTION(0x0, "gpio_in"),
  66                   SUNXI_FUNCTION(0x1, "gpio_out"),
  67                   SUNXI_FUNCTION(0x2, "gmac"),          /* TXD3 */
  68                   SUNXI_FUNCTION(0x4, "uart1"),         /* RING */
  69                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PA_EINT7 */
  70         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
  71                   SUNXI_FUNCTION(0x0, "gpio_in"),
  72                   SUNXI_FUNCTION(0x1, "gpio_out"),
  73                   SUNXI_FUNCTION(0x2, "gmac"),          /* TXD2 */
  74                   SUNXI_FUNCTION(0x4, "eclk"),          /* IN0 */
  75                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PA_EINT8 */
  76         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
  77                   SUNXI_FUNCTION(0x0, "gpio_in"),
  78                   SUNXI_FUNCTION(0x1, "gpio_out"),
  79                   SUNXI_FUNCTION(0x2, "gmac"),          /* TXEN */
  80                   SUNXI_FUNCTION(0x4, "eclk"),          /* IN1 */
  81                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PA_EINT9 */
  82         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
  83                   SUNXI_FUNCTION(0x0, "gpio_in"),
  84                   SUNXI_FUNCTION(0x1, "gpio_out"),
  85                   SUNXI_FUNCTION(0x2, "gmac"),          /* TXD0 */
  86                   SUNXI_FUNCTION(0x4, "clk_out_a"),
  87                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
  88         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
  89                   SUNXI_FUNCTION(0x0, "gpio_in"),
  90                   SUNXI_FUNCTION(0x1, "gpio_out"),
  91                   SUNXI_FUNCTION(0x2, "gmac"),          /* MII-CRS */
  92                   SUNXI_FUNCTION(0x4, "clk_out_b"),
  93                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
  94         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
  95                   SUNXI_FUNCTION(0x0, "gpio_in"),
  96                   SUNXI_FUNCTION(0x1, "gpio_out"),
  97                   SUNXI_FUNCTION(0x2, "gmac"),          /* TXCK */
  98                   SUNXI_FUNCTION(0x4, "pwm3"),          /* PWM_P */
  99                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
 100         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
 101                   SUNXI_FUNCTION(0x0, "gpio_in"),
 102                   SUNXI_FUNCTION(0x1, "gpio_out"),
 103                   SUNXI_FUNCTION(0x2, "gmac"),          /* RGMII-TXCK / GMII-TXEN */
 104                   SUNXI_FUNCTION(0x4, "pwm3"),          /* PWM_N */
 105                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
 106         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
 107                   SUNXI_FUNCTION(0x0, "gpio_in"),
 108                   SUNXI_FUNCTION(0x1, "gpio_out"),
 109                   SUNXI_FUNCTION(0x2, "gmac"),          /* MII-TXERR */
 110                   SUNXI_FUNCTION(0x4, "spi1"),          /* CS0 */
 111                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
 112         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
 113                   SUNXI_FUNCTION(0x0, "gpio_in"),
 114                   SUNXI_FUNCTION(0x1, "gpio_out"),
 115                   SUNXI_FUNCTION(0x2, "gmac"),          /* RGMII-CLKIN / MII-COL */
 116                   SUNXI_FUNCTION(0x4, "spi1"),          /* CLK */
 117                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
 118         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
 119                   SUNXI_FUNCTION(0x0, "gpio_in"),
 120                   SUNXI_FUNCTION(0x1, "gpio_out"),
 121                   SUNXI_FUNCTION(0x2, "gmac"),          /* EMDC */
 122                   SUNXI_FUNCTION(0x4, "spi1"),          /* MOSI */
 123                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
 124         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
 125                   SUNXI_FUNCTION(0x0, "gpio_in"),
 126                   SUNXI_FUNCTION(0x1, "gpio_out"),
 127                   SUNXI_FUNCTION(0x2, "gmac"),          /* EMDIO */
 128                   SUNXI_FUNCTION(0x4, "spi1"),          /* MISO */
 129                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
 130 
 131         /* Hole */
 132         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
 133                   SUNXI_FUNCTION(0x0, "gpio_in"),
 134                   SUNXI_FUNCTION(0x1, "gpio_out"),
 135                   SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
 136                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PB_EINT5 */
 137         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
 138                   SUNXI_FUNCTION(0x0, "gpio_in"),
 139                   SUNXI_FUNCTION(0x1, "gpio_out"),
 140                   SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
 141                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PB_EINT6 */
 142 
 143         /* Hole */
 144         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
 145                   SUNXI_FUNCTION(0x0, "gpio_in"),
 146                   SUNXI_FUNCTION(0x1, "gpio_out"),
 147                   SUNXI_FUNCTION(0x3, "mcsi"),          /* MCLK */
 148                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */
 149         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
 150                   SUNXI_FUNCTION(0x0, "gpio_in"),
 151                   SUNXI_FUNCTION(0x1, "gpio_out"),
 152                   SUNXI_FUNCTION(0x3, "mcsi"),          /* SCK */
 153                   SUNXI_FUNCTION(0x4, "i2c4"),          /* SCK */
 154                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */
 155         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
 156                   SUNXI_FUNCTION(0x0, "gpio_in"),
 157                   SUNXI_FUNCTION(0x1, "gpio_out"),
 158                   SUNXI_FUNCTION(0x3, "mcsi"),          /* SDA */
 159                   SUNXI_FUNCTION(0x4, "i2c4"),          /* SDA */
 160                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */
 161 
 162         /* Hole */
 163         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
 164                   SUNXI_FUNCTION(0x0, "gpio_in"),
 165                   SUNXI_FUNCTION(0x1, "gpio_out"),
 166                   SUNXI_FUNCTION(0x2, "nand0"),         /* WE */
 167                   SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
 168         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
 169                   SUNXI_FUNCTION(0x0, "gpio_in"),
 170                   SUNXI_FUNCTION(0x1, "gpio_out"),
 171                   SUNXI_FUNCTION(0x2, "nand0"),         /* ALE */
 172                   SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
 173         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
 174                   SUNXI_FUNCTION(0x0, "gpio_in"),
 175                   SUNXI_FUNCTION(0x1, "gpio_out"),
 176                   SUNXI_FUNCTION(0x2, "nand0"),         /* CLE */
 177                   SUNXI_FUNCTION(0x3, "spi0")),         /* CLK */
 178         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
 179                   SUNXI_FUNCTION(0x0, "gpio_in"),
 180                   SUNXI_FUNCTION(0x1, "gpio_out"),
 181                   SUNXI_FUNCTION(0x2, "nand0")),        /* CE1 */
 182         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
 183                   SUNXI_FUNCTION(0x0, "gpio_in"),
 184                   SUNXI_FUNCTION(0x1, "gpio_out"),
 185                   SUNXI_FUNCTION(0x2, "nand0")),        /* CE0 */
 186         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
 187                   SUNXI_FUNCTION(0x0, "gpio_in"),
 188                   SUNXI_FUNCTION(0x1, "gpio_out"),
 189                   SUNXI_FUNCTION(0x2, "nand0")),        /* RE */
 190         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
 191                   SUNXI_FUNCTION(0x0, "gpio_in"),
 192                   SUNXI_FUNCTION(0x1, "gpio_out"),
 193                   SUNXI_FUNCTION(0x2, "nand0"),         /* RB0 */
 194                   SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
 195         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
 196                   SUNXI_FUNCTION(0x0, "gpio_in"),
 197                   SUNXI_FUNCTION(0x1, "gpio_out"),
 198                   SUNXI_FUNCTION(0x2, "nand0"),         /* RB1 */
 199                   SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
 200         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
 201                   SUNXI_FUNCTION(0x0, "gpio_in"),
 202                   SUNXI_FUNCTION(0x1, "gpio_out"),
 203                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ0 */
 204                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
 205         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
 206                   SUNXI_FUNCTION(0x0, "gpio_in"),
 207                   SUNXI_FUNCTION(0x1, "gpio_out"),
 208                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ1 */
 209                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
 210         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
 211                   SUNXI_FUNCTION(0x0, "gpio_in"),
 212                   SUNXI_FUNCTION(0x1, "gpio_out"),
 213                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ2 */
 214                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
 215         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
 216                   SUNXI_FUNCTION(0x0, "gpio_in"),
 217                   SUNXI_FUNCTION(0x1, "gpio_out"),
 218                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ3 */
 219                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
 220         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
 221                   SUNXI_FUNCTION(0x0, "gpio_in"),
 222                   SUNXI_FUNCTION(0x1, "gpio_out"),
 223                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ4 */
 224                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
 225         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
 226                   SUNXI_FUNCTION(0x0, "gpio_in"),
 227                   SUNXI_FUNCTION(0x1, "gpio_out"),
 228                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ5 */
 229                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
 230         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
 231                   SUNXI_FUNCTION(0x0, "gpio_in"),
 232                   SUNXI_FUNCTION(0x1, "gpio_out"),
 233                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ6 */
 234                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
 235         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
 236                   SUNXI_FUNCTION(0x0, "gpio_in"),
 237                   SUNXI_FUNCTION(0x1, "gpio_out"),
 238                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ7 */
 239                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
 240         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
 241                   SUNXI_FUNCTION(0x0, "gpio_in"),
 242                   SUNXI_FUNCTION(0x1, "gpio_out"),
 243                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQS */
 244                   SUNXI_FUNCTION(0x3, "mmc2")),         /* RST */
 245         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
 246                   SUNXI_FUNCTION(0x0, "gpio_in"),
 247                   SUNXI_FUNCTION(0x1, "gpio_out"),
 248                   SUNXI_FUNCTION(0x2, "nand0"),         /* CE2 */
 249                   SUNXI_FUNCTION(0x3, "nand0_b")),      /* RE */
 250         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
 251                   SUNXI_FUNCTION(0x0, "gpio_in"),
 252                   SUNXI_FUNCTION(0x1, "gpio_out"),
 253                   SUNXI_FUNCTION(0x2, "nand0"),         /* CE3 */
 254                   SUNXI_FUNCTION(0x3, "nand0_b")),      /* DQS */
 255         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
 256                   SUNXI_FUNCTION(0x0, "gpio_in"),
 257                   SUNXI_FUNCTION(0x1, "gpio_out"),
 258                   SUNXI_FUNCTION(0x3, "spi0")),         /* CS0 */
 259 
 260         /* Hole */
 261         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
 262                   SUNXI_FUNCTION(0x0, "gpio_in"),
 263                   SUNXI_FUNCTION(0x1, "gpio_out"),
 264                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D0 */
 265                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VP0 */
 266         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
 267                   SUNXI_FUNCTION(0x0, "gpio_in"),
 268                   SUNXI_FUNCTION(0x1, "gpio_out"),
 269                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D1 */
 270                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VN0 */
 271         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
 272                   SUNXI_FUNCTION(0x0, "gpio_in"),
 273                   SUNXI_FUNCTION(0x1, "gpio_out"),
 274                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
 275                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VP1 */
 276         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
 277                   SUNXI_FUNCTION(0x0, "gpio_in"),
 278                   SUNXI_FUNCTION(0x1, "gpio_out"),
 279                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
 280                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VN1 */
 281         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
 282                   SUNXI_FUNCTION(0x0, "gpio_in"),
 283                   SUNXI_FUNCTION(0x1, "gpio_out"),
 284                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
 285                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VP2 */
 286         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
 287                   SUNXI_FUNCTION(0x0, "gpio_in"),
 288                   SUNXI_FUNCTION(0x1, "gpio_out"),
 289                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
 290                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VN2 */
 291         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
 292                   SUNXI_FUNCTION(0x0, "gpio_in"),
 293                   SUNXI_FUNCTION(0x1, "gpio_out"),
 294                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
 295                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VPC */
 296         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
 297                   SUNXI_FUNCTION(0x0, "gpio_in"),
 298                   SUNXI_FUNCTION(0x1, "gpio_out"),
 299                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
 300                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VNC */
 301         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
 302                   SUNXI_FUNCTION(0x0, "gpio_in"),
 303                   SUNXI_FUNCTION(0x1, "gpio_out"),
 304                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D8 */
 305                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VP3 */
 306         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
 307                   SUNXI_FUNCTION(0x0, "gpio_in"),
 308                   SUNXI_FUNCTION(0x1, "gpio_out"),
 309                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D9 */
 310                   SUNXI_FUNCTION(0x3, "lvds0")),        /* VN3 */
 311         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
 312                   SUNXI_FUNCTION(0x0, "gpio_in"),
 313                   SUNXI_FUNCTION(0x1, "gpio_out"),
 314                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
 315                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VP0 */
 316         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
 317                   SUNXI_FUNCTION(0x0, "gpio_in"),
 318                   SUNXI_FUNCTION(0x1, "gpio_out"),
 319                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
 320                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VN0 */
 321         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
 322                   SUNXI_FUNCTION(0x0, "gpio_in"),
 323                   SUNXI_FUNCTION(0x1, "gpio_out"),
 324                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
 325                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VP1 */
 326         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
 327                   SUNXI_FUNCTION(0x0, "gpio_in"),
 328                   SUNXI_FUNCTION(0x1, "gpio_out"),
 329                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
 330                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VN1 */
 331         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
 332                   SUNXI_FUNCTION(0x0, "gpio_in"),
 333                   SUNXI_FUNCTION(0x1, "gpio_out"),
 334                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
 335                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VP2 */
 336         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
 337                   SUNXI_FUNCTION(0x0, "gpio_in"),
 338                   SUNXI_FUNCTION(0x1, "gpio_out"),
 339                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
 340                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VN2 */
 341         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
 342                   SUNXI_FUNCTION(0x0, "gpio_in"),
 343                   SUNXI_FUNCTION(0x1, "gpio_out"),
 344                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D16 */
 345                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VPC */
 346         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
 347                   SUNXI_FUNCTION(0x0, "gpio_in"),
 348                   SUNXI_FUNCTION(0x1, "gpio_out"),
 349                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D17 */
 350                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VNC */
 351         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
 352                   SUNXI_FUNCTION(0x0, "gpio_in"),
 353                   SUNXI_FUNCTION(0x1, "gpio_out"),
 354                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
 355                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VP3 */
 356         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
 357                   SUNXI_FUNCTION(0x0, "gpio_in"),
 358                   SUNXI_FUNCTION(0x1, "gpio_out"),
 359                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
 360                   SUNXI_FUNCTION(0x3, "lvds1")),        /* VN3 */
 361         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
 362                   SUNXI_FUNCTION(0x0, "gpio_in"),
 363                   SUNXI_FUNCTION(0x1, "gpio_out"),
 364                   SUNXI_FUNCTION(0x2, "lcd0")),         /* D20 */
 365         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
 366                   SUNXI_FUNCTION(0x0, "gpio_in"),
 367                   SUNXI_FUNCTION(0x1, "gpio_out"),
 368                   SUNXI_FUNCTION(0x2, "lcd0")),         /* D21 */
 369         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
 370                   SUNXI_FUNCTION(0x0, "gpio_in"),
 371                   SUNXI_FUNCTION(0x1, "gpio_out"),
 372                   SUNXI_FUNCTION(0x2, "lcd0")),         /* D22 */
 373         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
 374                   SUNXI_FUNCTION(0x0, "gpio_in"),
 375                   SUNXI_FUNCTION(0x1, "gpio_out"),
 376                   SUNXI_FUNCTION(0x2, "lcd0")),         /* D23 */
 377         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
 378                   SUNXI_FUNCTION(0x0, "gpio_in"),
 379                   SUNXI_FUNCTION(0x1, "gpio_out"),
 380                   SUNXI_FUNCTION(0x2, "lcd0")),         /* CLK */
 381         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
 382                   SUNXI_FUNCTION(0x0, "gpio_in"),
 383                   SUNXI_FUNCTION(0x1, "gpio_out"),
 384                   SUNXI_FUNCTION(0x2, "lcd0")),         /* DE */
 385         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
 386                   SUNXI_FUNCTION(0x0, "gpio_in"),
 387                   SUNXI_FUNCTION(0x1, "gpio_out"),
 388                   SUNXI_FUNCTION(0x2, "lcd0")),         /* HSYNC */
 389         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
 390                   SUNXI_FUNCTION(0x0, "gpio_in"),
 391                   SUNXI_FUNCTION(0x1, "gpio_out"),
 392                   SUNXI_FUNCTION(0x2, "lcd0")),         /* VSYNC */
 393 
 394         /* Hole */
 395         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
 396                   SUNXI_FUNCTION(0x0, "gpio_in"),
 397                   SUNXI_FUNCTION(0x1, "gpio_out"),
 398                   SUNXI_FUNCTION(0x2, "csi"),           /* PCLK */
 399                   SUNXI_FUNCTION(0x3, "ts"),            /* CLK */
 400                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PE_EINT0 */
 401         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
 402                   SUNXI_FUNCTION(0x0, "gpio_in"),
 403                   SUNXI_FUNCTION(0x1, "gpio_out"),
 404                   SUNXI_FUNCTION(0x2, "csi"),           /* MCLK */
 405                   SUNXI_FUNCTION(0x3, "ts"),            /* ERR */
 406                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PE_EINT1 */
 407         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
 408                   SUNXI_FUNCTION(0x0, "gpio_in"),
 409                   SUNXI_FUNCTION(0x1, "gpio_out"),
 410                   SUNXI_FUNCTION(0x2, "csi"),           /* HSYNC */
 411                   SUNXI_FUNCTION(0x3, "ts"),            /* SYNC */
 412                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PE_EINT2 */
 413         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
 414                   SUNXI_FUNCTION(0x0, "gpio_in"),
 415                   SUNXI_FUNCTION(0x1, "gpio_out"),
 416                   SUNXI_FUNCTION(0x2, "csi"),           /* VSYNC */
 417                   SUNXI_FUNCTION(0x3, "ts"),            /* DVLD */
 418                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PE_EINT3 */
 419         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
 420                   SUNXI_FUNCTION(0x0, "gpio_in"),
 421                   SUNXI_FUNCTION(0x1, "gpio_out"),
 422                   SUNXI_FUNCTION(0x2, "csi"),           /* D0 */
 423                   SUNXI_FUNCTION(0x3, "spi2"),          /* CS0 */
 424                   SUNXI_FUNCTION(0x4, "uart5"),         /* TX */
 425                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PE_EINT4 */
 426         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
 427                   SUNXI_FUNCTION(0x0, "gpio_in"),
 428                   SUNXI_FUNCTION(0x1, "gpio_out"),
 429                   SUNXI_FUNCTION(0x2, "csi"),           /* D1 */
 430                   SUNXI_FUNCTION(0x3, "spi2"),          /* CLK */
 431                   SUNXI_FUNCTION(0x4, "uart5"),         /* RX */
 432                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PE_EINT5 */
 433         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
 434                   SUNXI_FUNCTION(0x0, "gpio_in"),
 435                   SUNXI_FUNCTION(0x1, "gpio_out"),
 436                   SUNXI_FUNCTION(0x2, "csi"),           /* D2 */
 437                   SUNXI_FUNCTION(0x3, "spi2"),          /* MOSI */
 438                   SUNXI_FUNCTION(0x4, "uart5"),         /* RTS */
 439                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PE_EINT6 */
 440         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
 441                   SUNXI_FUNCTION(0x0, "gpio_in"),
 442                   SUNXI_FUNCTION(0x1, "gpio_out"),
 443                   SUNXI_FUNCTION(0x2, "csi"),           /* D3 */
 444                   SUNXI_FUNCTION(0x3, "spi2"),          /* MISO */
 445                   SUNXI_FUNCTION(0x4, "uart5"),         /* CTS */
 446                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PE_EINT7 */
 447         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
 448                   SUNXI_FUNCTION(0x0, "gpio_in"),
 449                   SUNXI_FUNCTION(0x1, "gpio_out"),
 450                   SUNXI_FUNCTION(0x2, "csi"),           /* D4 */
 451                   SUNXI_FUNCTION(0x3, "ts"),            /* D0 */
 452                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PE_EINT8 */
 453         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
 454                   SUNXI_FUNCTION(0x0, "gpio_in"),
 455                   SUNXI_FUNCTION(0x1, "gpio_out"),
 456                   SUNXI_FUNCTION(0x2, "csi"),           /* D5 */
 457                   SUNXI_FUNCTION(0x3, "ts"),            /* D1 */
 458                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PE_EINT9 */
 459         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
 460                   SUNXI_FUNCTION(0x0, "gpio_in"),
 461                   SUNXI_FUNCTION(0x1, "gpio_out"),
 462                   SUNXI_FUNCTION(0x2, "csi"),           /* D6 */
 463                   SUNXI_FUNCTION(0x3, "ts"),            /* D2 */
 464                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
 465         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
 466                   SUNXI_FUNCTION(0x0, "gpio_in"),
 467                   SUNXI_FUNCTION(0x1, "gpio_out"),
 468                   SUNXI_FUNCTION(0x2, "csi"),           /* D7 */
 469                   SUNXI_FUNCTION(0x3, "ts"),            /* D3 */
 470                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
 471         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
 472                   SUNXI_FUNCTION(0x0, "gpio_in"),
 473                   SUNXI_FUNCTION(0x1, "gpio_out"),
 474                   SUNXI_FUNCTION(0x2, "csi"),           /* D8 */
 475                   SUNXI_FUNCTION(0x3, "ts"),            /* D4 */
 476                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
 477         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
 478                   SUNXI_FUNCTION(0x0, "gpio_in"),
 479                   SUNXI_FUNCTION(0x1, "gpio_out"),
 480                   SUNXI_FUNCTION(0x2, "csi"),           /* D9 */
 481                   SUNXI_FUNCTION(0x3, "ts"),            /* D5 */
 482                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
 483         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
 484                   SUNXI_FUNCTION(0x0, "gpio_in"),
 485                   SUNXI_FUNCTION(0x1, "gpio_out"),
 486                   SUNXI_FUNCTION(0x2, "csi"),           /* D10 */
 487                   SUNXI_FUNCTION(0x3, "ts"),            /* D6 */
 488                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
 489         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
 490                   SUNXI_FUNCTION(0x0, "gpio_in"),
 491                   SUNXI_FUNCTION(0x1, "gpio_out"),
 492                   SUNXI_FUNCTION(0x2, "csi"),           /* D11 */
 493                   SUNXI_FUNCTION(0x3, "ts"),            /* D7 */
 494                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
 495         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
 496                   SUNXI_FUNCTION(0x0, "gpio_in"),
 497                   SUNXI_FUNCTION(0x1, "gpio_out"),
 498                   SUNXI_FUNCTION(0x2, "csi"),           /* SCK */
 499                   SUNXI_FUNCTION(0x3, "i2c4"),          /* SCK */
 500                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
 501         SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
 502                   SUNXI_FUNCTION(0x0, "gpio_in"),
 503                   SUNXI_FUNCTION(0x1, "gpio_out"),
 504                   SUNXI_FUNCTION(0x2, "csi"),           /* SDA */
 505                   SUNXI_FUNCTION(0x3, "i2c4"),          /* SDA */
 506                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PE_EINT17 */
 507 
 508         /* Hole */
 509         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
 510                   SUNXI_FUNCTION(0x0, "gpio_in"),
 511                   SUNXI_FUNCTION(0x1, "gpio_out"),
 512                   SUNXI_FUNCTION(0x2, "mmc0")),         /* D1 */
 513         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
 514                   SUNXI_FUNCTION(0x0, "gpio_in"),
 515                   SUNXI_FUNCTION(0x1, "gpio_out"),
 516                   SUNXI_FUNCTION(0x2, "mmc0")),         /* D0 */
 517         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
 518                   SUNXI_FUNCTION(0x0, "gpio_in"),
 519                   SUNXI_FUNCTION(0x1, "gpio_out"),
 520                   SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
 521                   SUNXI_FUNCTION(0x4, "uart0")),        /* TX */
 522         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
 523                   SUNXI_FUNCTION(0x0, "gpio_in"),
 524                   SUNXI_FUNCTION(0x1, "gpio_out"),
 525                   SUNXI_FUNCTION(0x2, "mmc0")),         /* CMD */
 526         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
 527                   SUNXI_FUNCTION(0x0, "gpio_in"),
 528                   SUNXI_FUNCTION(0x1, "gpio_out"),
 529                   SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
 530                   SUNXI_FUNCTION(0x4, "uart0")),        /* RX */
 531         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
 532                   SUNXI_FUNCTION(0x0, "gpio_in"),
 533                   SUNXI_FUNCTION(0x1, "gpio_out"),
 534                   SUNXI_FUNCTION(0x2, "mmc0")),         /* D2 */
 535 
 536         /* Hole */
 537         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
 538                   SUNXI_FUNCTION(0x0, "gpio_in"),
 539                   SUNXI_FUNCTION(0x1, "gpio_out"),
 540                   SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
 541                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),  /* PG_EINT0 */
 542         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
 543                   SUNXI_FUNCTION(0x0, "gpio_in"),
 544                   SUNXI_FUNCTION(0x1, "gpio_out"),
 545                   SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
 546                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),  /* PG_EINT1 */
 547         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
 548                   SUNXI_FUNCTION(0x0, "gpio_in"),
 549                   SUNXI_FUNCTION(0x1, "gpio_out"),
 550                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D0 */
 551                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),  /* PG_EINT2 */
 552         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
 553                   SUNXI_FUNCTION(0x0, "gpio_in"),
 554                   SUNXI_FUNCTION(0x1, "gpio_out"),
 555                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
 556                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),  /* PG_EINT3 */
 557         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
 558                   SUNXI_FUNCTION(0x0, "gpio_in"),
 559                   SUNXI_FUNCTION(0x1, "gpio_out"),
 560                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
 561                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),  /* PG_EINT4 */
 562         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
 563                   SUNXI_FUNCTION(0x0, "gpio_in"),
 564                   SUNXI_FUNCTION(0x1, "gpio_out"),
 565                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
 566                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),  /* PG_EINT5 */
 567         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
 568                   SUNXI_FUNCTION(0x0, "gpio_in"),
 569                   SUNXI_FUNCTION(0x1, "gpio_out"),
 570                   SUNXI_FUNCTION(0x2, "uart2"),         /* TX */
 571                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),  /* PG_EINT6 */
 572         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
 573                   SUNXI_FUNCTION(0x0, "gpio_in"),
 574                   SUNXI_FUNCTION(0x1, "gpio_out"),
 575                   SUNXI_FUNCTION(0x2, "uart2"),         /* RX */
 576                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),  /* PG_EINT7 */
 577         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
 578                   SUNXI_FUNCTION(0x0, "gpio_in"),
 579                   SUNXI_FUNCTION(0x1, "gpio_out"),
 580                   SUNXI_FUNCTION(0x2, "uart2"),         /* RTS */
 581                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),  /* PG_EINT8 */
 582         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
 583                   SUNXI_FUNCTION(0x0, "gpio_in"),
 584                   SUNXI_FUNCTION(0x1, "gpio_out"),
 585                   SUNXI_FUNCTION(0x2, "uart2"),         /* CTS */
 586                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),  /* PG_EINT9 */
 587         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
 588                   SUNXI_FUNCTION(0x0, "gpio_in"),
 589                   SUNXI_FUNCTION(0x1, "gpio_out"),
 590                   SUNXI_FUNCTION(0x2, "i2c3"),          /* SCK */
 591                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
 592         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
 593                   SUNXI_FUNCTION(0x0, "gpio_in"),
 594                   SUNXI_FUNCTION(0x1, "gpio_out"),
 595                   SUNXI_FUNCTION(0x2, "i2c3"),          /* SDA */
 596                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
 597         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
 598                   SUNXI_FUNCTION(0x0, "gpio_in"),
 599                   SUNXI_FUNCTION(0x1, "gpio_out"),
 600                   SUNXI_FUNCTION(0x2, "uart4"),         /* TX */
 601                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
 602         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
 603                   SUNXI_FUNCTION(0x0, "gpio_in"),
 604                   SUNXI_FUNCTION(0x1, "gpio_out"),
 605                   SUNXI_FUNCTION(0x2, "uart4"),         /* RX */
 606                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
 607         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
 608                   SUNXI_FUNCTION(0x0, "gpio_in"),
 609                   SUNXI_FUNCTION(0x1, "gpio_out"),
 610                   SUNXI_FUNCTION(0x2, "uart4"),         /* RTS */
 611                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
 612         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
 613                   SUNXI_FUNCTION(0x0, "gpio_in"),
 614                   SUNXI_FUNCTION(0x1, "gpio_out"),
 615                   SUNXI_FUNCTION(0x2, "uart4"),         /* CTS */
 616                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
 617 
 618         /* Hole */
 619         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
 620                   SUNXI_FUNCTION(0x0, "gpio_in"),
 621                   SUNXI_FUNCTION(0x1, "gpio_out"),
 622                   SUNXI_FUNCTION(0x2, "i2c0")),         /* SCK */
 623         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
 624                   SUNXI_FUNCTION(0x0, "gpio_in"),
 625                   SUNXI_FUNCTION(0x1, "gpio_out"),
 626                   SUNXI_FUNCTION(0x2, "i2c0")),         /* SDA */
 627         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
 628                   SUNXI_FUNCTION(0x0, "gpio_in"),
 629                   SUNXI_FUNCTION(0x1, "gpio_out"),
 630                   SUNXI_FUNCTION(0x2, "i2c1")),         /* SCK */
 631         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
 632                   SUNXI_FUNCTION(0x0, "gpio_in"),
 633                   SUNXI_FUNCTION(0x1, "gpio_out"),
 634                   SUNXI_FUNCTION(0x2, "i2c1")),         /* SDA */
 635         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
 636                   SUNXI_FUNCTION(0x0, "gpio_in"),
 637                   SUNXI_FUNCTION(0x1, "gpio_out"),
 638                   SUNXI_FUNCTION(0x2, "i2c2")),         /* SCK */
 639         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
 640                   SUNXI_FUNCTION(0x0, "gpio_in"),
 641                   SUNXI_FUNCTION(0x1, "gpio_out"),
 642                   SUNXI_FUNCTION(0x2, "i2c2")),         /* SDA */
 643         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
 644                   SUNXI_FUNCTION(0x0, "gpio_in"),
 645                   SUNXI_FUNCTION(0x1, "gpio_out"),
 646                   SUNXI_FUNCTION(0x2, "pwm0")),
 647 
 648         /* Hole */
 649         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
 650                   SUNXI_FUNCTION(0x0, "gpio_in"),
 651                   SUNXI_FUNCTION(0x1, "gpio_out"),
 652                   SUNXI_FUNCTION(0x3, "pwm1"),          /* Positive */
 653                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 8)),  /* PH_EINT8 */
 654         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
 655                   SUNXI_FUNCTION(0x0, "gpio_in"),
 656                   SUNXI_FUNCTION(0x1, "gpio_out"),
 657                   SUNXI_FUNCTION(0x3, "pwm1"),          /* Negative */
 658                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 9)),  /* PH_EINT9 */
 659         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
 660                   SUNXI_FUNCTION(0x0, "gpio_in"),
 661                   SUNXI_FUNCTION(0x1, "gpio_out"),
 662                   SUNXI_FUNCTION(0x3, "pwm2"),          /* Positive */
 663                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 10)), /* PH_EINT10 */
 664         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
 665                   SUNXI_FUNCTION(0x0, "gpio_in"),
 666                   SUNXI_FUNCTION(0x1, "gpio_out"),
 667                   SUNXI_FUNCTION(0x3, "pwm2"),          /* Negative */
 668                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 11)), /* PH_EINT12 */
 669         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
 670                   SUNXI_FUNCTION(0x0, "gpio_in"),
 671                   SUNXI_FUNCTION(0x1, "gpio_out"),
 672                   SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
 673                   SUNXI_FUNCTION(0x3, "spi3"),          /* CS2 */
 674                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 12)), /* PH_EINT12 */
 675         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
 676                   SUNXI_FUNCTION(0x0, "gpio_in"),
 677                   SUNXI_FUNCTION(0x1, "gpio_out"),
 678                   SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
 679                   SUNXI_FUNCTION(0x3, "spi3"),          /* CS2 */
 680                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 13)), /* PH_EINT13 */
 681         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
 682                   SUNXI_FUNCTION(0x0, "gpio_in"),
 683                   SUNXI_FUNCTION(0x1, "gpio_out"),
 684                   SUNXI_FUNCTION(0x2, "spi3"),          /* CLK */
 685                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 14)), /* PH_EINT14 */
 686         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
 687                   SUNXI_FUNCTION(0x0, "gpio_in"),
 688                   SUNXI_FUNCTION(0x1, "gpio_out"),
 689                   SUNXI_FUNCTION(0x2, "spi3"),          /* MOSI */
 690                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 15)), /* PH_EINT15 */
 691         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
 692                   SUNXI_FUNCTION(0x0, "gpio_in"),
 693                   SUNXI_FUNCTION(0x1, "gpio_out"),
 694                   SUNXI_FUNCTION(0x2, "spi3"),          /* MISO */
 695                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 16)), /* PH_EINT16 */
 696         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
 697                   SUNXI_FUNCTION(0x0, "gpio_in"),
 698                   SUNXI_FUNCTION(0x1, "gpio_out"),
 699                   SUNXI_FUNCTION(0x2, "spi3"),          /* CS0 */
 700                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 17)), /* PH_EINT17 */
 701         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
 702                   SUNXI_FUNCTION(0x0, "gpio_in"),
 703                   SUNXI_FUNCTION(0x1, "gpio_out"),
 704                   SUNXI_FUNCTION(0x2, "spi3"),          /* CS1 */
 705                   SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 18)), /* PH_EINT18 */
 706         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
 707                   SUNXI_FUNCTION(0x0, "gpio_in"),
 708                   SUNXI_FUNCTION(0x1, "gpio_out"),
 709                   SUNXI_FUNCTION(0x2, "hdmi")),         /* SCL */
 710         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
 711                   SUNXI_FUNCTION(0x0, "gpio_in"),
 712                   SUNXI_FUNCTION(0x1, "gpio_out"),
 713                   SUNXI_FUNCTION(0x2, "hdmi")),         /* SDA */
 714         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
 715                   SUNXI_FUNCTION(0x0, "gpio_in"),
 716                   SUNXI_FUNCTION(0x1, "gpio_out"),
 717                   SUNXI_FUNCTION(0x2, "hdmi")),         /* CEC */
 718 };
 719 
 720 static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
 721         .pins = sun9i_a80_pins,
 722         .npins = ARRAY_SIZE(sun9i_a80_pins),
 723         .irq_banks = 5,
 724         .disable_strict_mode = true,
 725         .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
 726 };
 727 
 728 static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
 729 {
 730         return sunxi_pinctrl_init(pdev,
 731                                   &sun9i_a80_pinctrl_data);
 732 }
 733 
 734 static const struct of_device_id sun9i_a80_pinctrl_match[] = {
 735         { .compatible = "allwinner,sun9i-a80-pinctrl", },
 736         {}
 737 };
 738 
 739 static struct platform_driver sun9i_a80_pinctrl_driver = {
 740         .probe  = sun9i_a80_pinctrl_probe,
 741         .driver = {
 742                 .name           = "sun9i-a80-pinctrl",
 743                 .of_match_table = sun9i_a80_pinctrl_match,
 744         },
 745 };
 746 builtin_platform_driver(sun9i_a80_pinctrl_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c

DEFINITIONS
