This source file includes following definitions.
- ia64_pal_bus_get_features
- ia64_pal_bus_set_features
- ia64_pal_cache_config_info
- ia64_pal_cache_prot_info
- ia64_pal_cache_flush
- ia64_pal_cache_init
- ia64_pal_cache_line_init
- ia64_pal_cache_read
- ia64_pal_cache_summary
- ia64_pal_cache_write
- ia64_pal_copy_info
- ia64_pal_copy_pal
- ia64_pal_debug_info
- ia64_pal_enter_ia32_env
- ia64_pal_fixed_addr
- ia64_pal_freq_base
- ia64_pal_freq_ratios
- ia64_pal_get_hw_policy
- ia64_pal_halt
- ia64_pal_halt_info
- ia64_pal_get_pstate
- ia64_pal_set_pstate
- ia64_pal_get_brand_info
- ia64_pal_halt_light
- ia64_pal_mc_clear_log
- ia64_pal_mc_drain
- ia64_pal_mc_dynamic_state
- ia64_pal_mc_error_info
- ia64_pal_mc_error_inject_phys
- ia64_pal_mc_error_inject_virt
- ia64_pal_mc_expected
- ia64_pal_mc_hw_tracking
- ia64_pal_mc_register_mem
- ia64_pal_mc_resume
- ia64_pal_mem_attrib
- ia64_pal_mem_for_test
- ia64_pal_perf_mon_info
- ia64_pal_platform_addr
- ia64_pal_pmi_entrypoint
- ia64_pal_proc_get_features
- ia64_pal_proc_set_features
- ia64_get_ptce
- ia64_pal_register_info
- ia64_pal_rse_info
- ia64_pal_set_hw_policy
- ia64_pal_shutdown
- ia64_pal_test_proc
- ia64_pal_version
- ia64_pal_vm_info
- ia64_pal_vm_page_size
- ia64_pal_vm_summary
- ia64_pal_vp_info
- ia64_pal_tr_read
- ia64_pal_prefetch_visibility
- ia64_pal_logical_to_phys
- ia64_pal_cache_shared_info
1
2 #ifndef _ASM_IA64_PAL_H
3 #define _ASM_IA64_PAL_H
4
5
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31
32
33
34 #define PAL_CACHE_FLUSH 1
35 #define PAL_CACHE_INFO 2
36 #define PAL_CACHE_INIT 3
37 #define PAL_CACHE_SUMMARY 4
38 #define PAL_MEM_ATTRIB 5
39 #define PAL_PTCE_INFO 6
40 #define PAL_VM_INFO 7
41 #define PAL_VM_SUMMARY 8
42 #define PAL_BUS_GET_FEATURES 9
43 #define PAL_BUS_SET_FEATURES 10
44 #define PAL_DEBUG_INFO 11
45 #define PAL_FIXED_ADDR 12
46 #define PAL_FREQ_BASE 13
47 #define PAL_FREQ_RATIOS 14
48 #define PAL_PERF_MON_INFO 15
49 #define PAL_PLATFORM_ADDR 16
50 #define PAL_PROC_GET_FEATURES 17
51 #define PAL_PROC_SET_FEATURES 18
52 #define PAL_RSE_INFO 19
53 #define PAL_VERSION 20
54 #define PAL_MC_CLEAR_LOG 21
55 #define PAL_MC_DRAIN 22
56 #define PAL_MC_EXPECTED 23
57 #define PAL_MC_DYNAMIC_STATE 24
58 #define PAL_MC_ERROR_INFO 25
59 #define PAL_MC_RESUME 26
60 #define PAL_MC_REGISTER_MEM 27
61 #define PAL_HALT 28
62 #define PAL_HALT_LIGHT 29
63 #define PAL_COPY_INFO 30
64 #define PAL_CACHE_LINE_INIT 31
65 #define PAL_PMI_ENTRYPOINT 32
66 #define PAL_ENTER_IA_32_ENV 33
67 #define PAL_VM_PAGE_SIZE 34
68
69 #define PAL_MEM_FOR_TEST 37
70 #define PAL_CACHE_PROT_INFO 38
71 #define PAL_REGISTER_INFO 39
72 #define PAL_SHUTDOWN 40
73 #define PAL_PREFETCH_VISIBILITY 41
74 #define PAL_LOGICAL_TO_PHYSICAL 42
75 #define PAL_CACHE_SHARED_INFO 43
76 #define PAL_GET_HW_POLICY 48
77 #define PAL_SET_HW_POLICY 49
78 #define PAL_VP_INFO 50
79 #define PAL_MC_HW_TRACKING 51
80
81 #define PAL_COPY_PAL 256
82 #define PAL_HALT_INFO 257
83 #define PAL_TEST_PROC 258
84 #define PAL_CACHE_READ 259
85 #define PAL_CACHE_WRITE 260
86 #define PAL_VM_TR_READ 261
87 #define PAL_GET_PSTATE 262
88 #define PAL_SET_PSTATE 263
89 #define PAL_BRAND_INFO 274
90
91 #define PAL_GET_PSTATE_TYPE_LASTSET 0
92 #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
93 #define PAL_GET_PSTATE_TYPE_AVGNORESET 2
94 #define PAL_GET_PSTATE_TYPE_INSTANT 3
95
96 #define PAL_MC_ERROR_INJECT 276
97
98 #ifndef __ASSEMBLY__
99
100 #include <linux/types.h>
101 #include <asm/fpu.h>
102
103
104
105
106
107
108
109 typedef s64 pal_status_t;
110
111 #define PAL_STATUS_SUCCESS 0
112 #define PAL_STATUS_UNIMPLEMENTED (-1)
113 #define PAL_STATUS_EINVAL (-2)
114 #define PAL_STATUS_ERROR (-3)
115 #define PAL_STATUS_CACHE_INIT_FAIL (-4)
116
117
118
119
120 #define PAL_STATUS_REQUIRES_MEMORY (-9)
121
122
123 typedef u64 pal_cache_level_t;
124 #define PAL_CACHE_LEVEL_L0 0
125 #define PAL_CACHE_LEVEL_L1 1
126 #define PAL_CACHE_LEVEL_L2 2
127
128
129
130
131 typedef u64 pal_cache_type_t;
132 #define PAL_CACHE_TYPE_INSTRUCTION 1
133 #define PAL_CACHE_TYPE_DATA 2
134 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3
135
136
137 #define PAL_CACHE_FLUSH_INVALIDATE 1
138 #define PAL_CACHE_FLUSH_CHK_INTRS 2
139
140
141 typedef int pal_cache_line_size_t;
142
143
144 typedef u64 pal_cache_line_state_t;
145 #define PAL_CACHE_LINE_STATE_INVALID 0
146 #define PAL_CACHE_LINE_STATE_SHARED 1
147 #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2
148 #define PAL_CACHE_LINE_STATE_MODIFIED 3
149
150 typedef struct pal_freq_ratio {
151 u32 den, num;
152 } itc_ratio, proc_ratio;
153
154 typedef union pal_cache_config_info_1_s {
155 struct {
156 u64 u : 1,
157 at : 2,
158 reserved : 5,
159 associativity : 8,
160 line_size : 8,
161 stride : 8,
162 store_latency : 8,
163 load_latency : 8,
164 store_hints : 8,
165 load_hints : 8;
166 } pcci1_bits;
167 u64 pcci1_data;
168 } pal_cache_config_info_1_t;
169
170 typedef union pal_cache_config_info_2_s {
171 struct {
172 u32 cache_size;
173
174
175 u32 alias_boundary : 8,
176
177
178
179 tag_ls_bit : 8,
180 tag_ms_bit : 8,
181 reserved : 8;
182 } pcci2_bits;
183 u64 pcci2_data;
184 } pal_cache_config_info_2_t;
185
186
187 typedef struct pal_cache_config_info_s {
188 pal_status_t pcci_status;
189 pal_cache_config_info_1_t pcci_info_1;
190 pal_cache_config_info_2_t pcci_info_2;
191 u64 pcci_reserved;
192 } pal_cache_config_info_t;
193
194 #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
195 #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
196 #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
197 #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
198 #define pcci_stride pcci_info_1.pcci1_bits.stride
199 #define pcci_line_size pcci_info_1.pcci1_bits.line_size
200 #define pcci_assoc pcci_info_1.pcci1_bits.associativity
201 #define pcci_cache_attr pcci_info_1.pcci1_bits.at
202 #define pcci_unified pcci_info_1.pcci1_bits.u
203 #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
204 #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
205 #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
206 #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
207
208
209
210
211
212 #define PAL_CACHE_ATTR_WT 0
213 #define PAL_CACHE_ATTR_WB 1
214 #define PAL_CACHE_ATTR_WT_OR_WB 2
215
216
217
218
219
220
221
222 #define PAL_CACHE_HINT_TEMP_1 0
223 #define PAL_CACHE_HINT_NTEMP_1 1
224 #define PAL_CACHE_HINT_NTEMP_ALL 3
225
226
227 typedef union pal_cache_protection_element_u {
228 u32 pcpi_data;
229 struct {
230 u32 data_bits : 8,
231
232
233
234 tagprot_lsb : 6,
235 tagprot_msb : 6,
236
237
238
239 prot_bits : 6,
240 method : 4,
241 t_d : 2;
242
243
244
245
246 } pcp_info;
247 } pal_cache_protection_element_t;
248
249 #define pcpi_cache_prot_part pcp_info.t_d
250 #define pcpi_prot_method pcp_info.method
251 #define pcpi_prot_bits pcp_info.prot_bits
252 #define pcpi_tagprot_msb pcp_info.tagprot_msb
253 #define pcpi_tagprot_lsb pcp_info.tagprot_lsb
254 #define pcpi_data_bits pcp_info.data_bits
255
256
257 #define PAL_CACHE_PROT_PART_DATA 0
258 #define PAL_CACHE_PROT_PART_TAG 1
259 #define PAL_CACHE_PROT_PART_TAG_DATA 2
260
261
262 #define PAL_CACHE_PROT_PART_DATA_TAG 3
263
264
265 #define PAL_CACHE_PROT_PART_MAX 6
266
267
268 typedef struct pal_cache_protection_info_s {
269 pal_status_t pcpi_status;
270 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
271 } pal_cache_protection_info_t;
272
273
274
275 #define PAL_CACHE_PROT_METHOD_NONE 0
276 #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1
277 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2
278 #define PAL_CACHE_PROT_METHOD_ECC 3
279
280
281
282 typedef union pal_cache_line_id_u {
283 u64 pclid_data;
284 struct {
285 u64 cache_type : 8,
286 level : 8,
287
288
289
290 way : 8,
291
292 part : 8,
293
294
295 reserved : 32;
296 } pclid_info_read;
297 struct {
298 u64 cache_type : 8,
299 level : 8,
300
301
302
303 way : 8,
304
305 part : 8,
306
307
308 mesi : 8,
309
310
311 start : 8,
312
313
314 length : 8,
315
316
317 trigger : 8;
318
319
320
321
322 } pclid_info_write;
323 } pal_cache_line_id_u_t;
324
325 #define pclid_read_part pclid_info_read.part
326 #define pclid_read_way pclid_info_read.way
327 #define pclid_read_level pclid_info_read.level
328 #define pclid_read_cache_type pclid_info_read.cache_type
329
330 #define pclid_write_trigger pclid_info_write.trigger
331 #define pclid_write_length pclid_info_write.length
332 #define pclid_write_start pclid_info_write.start
333 #define pclid_write_mesi pclid_info_write.mesi
334 #define pclid_write_part pclid_info_write.part
335 #define pclid_write_way pclid_info_write.way
336 #define pclid_write_level pclid_info_write.level
337 #define pclid_write_cache_type pclid_info_write.cache_type
338
339
340 #define PAL_CACHE_LINE_ID_PART_DATA 0
341 #define PAL_CACHE_LINE_ID_PART_TAG 1
342 #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2
343 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3
344 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4
345
346
347 typedef struct pal_cache_line_info_s {
348 pal_status_t pcli_status;
349
350
351 u64 pcli_data;
352 u64 pcli_data_len;
353 pal_cache_line_state_t pcli_cache_line_state;
354
355 } pal_cache_line_info_t;
356
357
358
359
360
361 typedef u64 pal_mc_pending_events_t;
362
363 #define PAL_MC_PENDING_MCA (1 << 0)
364 #define PAL_MC_PENDING_INIT (1 << 1)
365
366
367 typedef u64 pal_mc_info_index_t;
368
369 #define PAL_MC_INFO_PROCESSOR 0
370 #define PAL_MC_INFO_CACHE_CHECK 1
371 #define PAL_MC_INFO_TLB_CHECK 2
372 #define PAL_MC_INFO_BUS_CHECK 3
373 #define PAL_MC_INFO_REQ_ADDR 4
374 #define PAL_MC_INFO_RESP_ADDR 5
375 #define PAL_MC_INFO_TARGET_ADDR 6
376 #define PAL_MC_INFO_IMPL_DEP 7
377
378
379
380 #define PAL_TLB_CHECK_OP_PURGE 8
381
382 typedef struct pal_process_state_info_s {
383 u64 reserved1 : 2,
384 rz : 1,
385
386
387
388
389 ra : 1,
390
391
392 me : 1,
393
394
395
396 mn : 1,
397
398
399
400
401 sy : 1,
402
403
404
405
406 co : 1,
407 ci : 1,
408 us : 1,
409
410
411
412
413 hd : 1,
414
415
416
417
418
419
420
421 tl : 1,
422
423
424
425
426
427
428
429
430 mi : 1,
431
432
433 pi : 1,
434 pm : 1,
435
436 dy : 1,
437
438
439
440
441 in : 1,
442 rs : 1,
443 cm : 1,
444 ex : 1,
445 cr : 1,
446 pc : 1,
447 dr : 1,
448 tr : 1,
449
450
451 rr : 1,
452 ar : 1,
453 br : 1,
454 pr : 1,
455
456
457
458 fp : 1,
459 b1 : 1,
460
461
462
463 b0 : 1,
464
465
466
467 gr : 1,
468
469
470
471 dsize : 16,
472
473
474
475
476 se : 1,
477
478 reserved2 : 10,
479 cc : 1,
480 tc : 1,
481 bc : 1,
482 rc : 1,
483 uc : 1;
484
485 } pal_processor_state_info_t;
486
487 typedef struct pal_cache_check_info_s {
488 u64 op : 4,
489
490
491
492
493 level : 2,
494 reserved1 : 2,
495 dl : 1,
496
497
498 tl : 1,
499
500
501 dc : 1,
502 ic : 1,
503 mesi : 3,
504 mv : 1,
505 way : 5,
506
507
508 wiv : 1,
509 reserved2 : 1,
510 dp : 1,
511 reserved3 : 6,
512 hlth : 2,
513
514 index : 20,
515 reserved4 : 2,
516
517 is : 1,
518 iv : 1,
519 pl : 2,
520 pv : 1,
521 mcc : 1,
522 tv : 1,
523
524
525 rq : 1,
526
527
528 rp : 1,
529
530
531 pi : 1;
532
533
534 } pal_cache_check_info_t;
535
536 typedef struct pal_tlb_check_info_s {
537
538 u64 tr_slot : 8,
539
540
541 trv : 1,
542 reserved1 : 1,
543 level : 2,
544 reserved2 : 4,
545 dtr : 1,
546 itr : 1,
547 dtc : 1,
548 itc : 1,
549 op : 4,
550 reserved3 : 6,
551 hlth : 2,
552 reserved4 : 22,
553
554 is : 1,
555 iv : 1,
556 pl : 2,
557 pv : 1,
558 mcc : 1,
559 tv : 1,
560
561
562 rq : 1,
563
564
565 rp : 1,
566
567
568 pi : 1;
569
570
571 } pal_tlb_check_info_t;
572
573 typedef struct pal_bus_check_info_s {
574 u64 size : 5,
575 ib : 1,
576 eb : 1,
577 cc : 1,
578
579
580
581 type : 8,
582 sev : 5,
583 hier : 2,
584 dp : 1,
585 bsi : 8,
586
587
588 reserved2 : 22,
589
590 is : 1,
591 iv : 1,
592 pl : 2,
593 pv : 1,
594 mcc : 1,
595 tv : 1,
596
597
598 rq : 1,
599
600
601 rp : 1,
602
603
604 pi : 1;
605
606
607 } pal_bus_check_info_t;
608
609 typedef struct pal_reg_file_check_info_s {
610 u64 id : 4,
611 op : 4,
612
613
614
615
616 reg_num : 7,
617 rnv : 1,
618 reserved2 : 38,
619
620 is : 1,
621 iv : 1,
622 pl : 2,
623 pv : 1,
624 mcc : 1,
625 reserved3 : 3,
626 pi : 1;
627
628
629 } pal_reg_file_check_info_t;
630
631 typedef struct pal_uarch_check_info_s {
632 u64 sid : 5,
633 level : 3,
634 array_id : 4,
635 op : 4,
636
637
638
639
640 way : 6,
641 wv : 1,
642 xv : 1,
643 reserved1 : 6,
644 hlth : 2,
645 index : 8,
646
647
648 reserved2 : 24,
649
650 is : 1,
651 iv : 1,
652 pl : 2,
653 pv : 1,
654 mcc : 1,
655 tv : 1,
656
657
658 rq : 1,
659
660
661 rp : 1,
662
663
664 pi : 1;
665
666
667 } pal_uarch_check_info_t;
668
669 typedef union pal_mc_error_info_u {
670 u64 pmei_data;
671 pal_processor_state_info_t pme_processor;
672 pal_cache_check_info_t pme_cache;
673 pal_tlb_check_info_t pme_tlb;
674 pal_bus_check_info_t pme_bus;
675 pal_reg_file_check_info_t pme_reg_file;
676 pal_uarch_check_info_t pme_uarch;
677 } pal_mc_error_info_t;
678
679 #define pmci_proc_unknown_check pme_processor.uc
680 #define pmci_proc_bus_check pme_processor.bc
681 #define pmci_proc_tlb_check pme_processor.tc
682 #define pmci_proc_cache_check pme_processor.cc
683 #define pmci_proc_dynamic_state_size pme_processor.dsize
684 #define pmci_proc_gpr_valid pme_processor.gr
685 #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
686 #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
687 #define pmci_proc_fp_valid pme_processor.fp
688 #define pmci_proc_predicate_regs_valid pme_processor.pr
689 #define pmci_proc_branch_regs_valid pme_processor.br
690 #define pmci_proc_app_regs_valid pme_processor.ar
691 #define pmci_proc_region_regs_valid pme_processor.rr
692 #define pmci_proc_translation_regs_valid pme_processor.tr
693 #define pmci_proc_debug_regs_valid pme_processor.dr
694 #define pmci_proc_perf_counters_valid pme_processor.pc
695 #define pmci_proc_control_regs_valid pme_processor.cr
696 #define pmci_proc_machine_check_expected pme_processor.ex
697 #define pmci_proc_machine_check_corrected pme_processor.cm
698 #define pmci_proc_rse_valid pme_processor.rs
699 #define pmci_proc_machine_check_or_init pme_processor.in
700 #define pmci_proc_dynamic_state_valid pme_processor.dy
701 #define pmci_proc_operation pme_processor.op
702 #define pmci_proc_trap_lost pme_processor.tl
703 #define pmci_proc_hardware_damage pme_processor.hd
704 #define pmci_proc_uncontained_storage_damage pme_processor.us
705 #define pmci_proc_machine_check_isolated pme_processor.ci
706 #define pmci_proc_continuable pme_processor.co
707 #define pmci_proc_storage_intergrity_synced pme_processor.sy
708 #define pmci_proc_min_state_save_area_regd pme_processor.mn
709 #define pmci_proc_distinct_multiple_errors pme_processor.me
710 #define pmci_proc_pal_attempted_rendezvous pme_processor.ra
711 #define pmci_proc_pal_rendezvous_complete pme_processor.rz
712
713
714 #define pmci_cache_level pme_cache.level
715 #define pmci_cache_line_state pme_cache.mesi
716 #define pmci_cache_line_state_valid pme_cache.mv
717 #define pmci_cache_line_index pme_cache.index
718 #define pmci_cache_instr_cache_fail pme_cache.ic
719 #define pmci_cache_data_cache_fail pme_cache.dc
720 #define pmci_cache_line_tag_fail pme_cache.tl
721 #define pmci_cache_line_data_fail pme_cache.dl
722 #define pmci_cache_operation pme_cache.op
723 #define pmci_cache_way_valid pme_cache.wv
724 #define pmci_cache_target_address_valid pme_cache.tv
725 #define pmci_cache_way pme_cache.way
726 #define pmci_cache_mc pme_cache.mc
727
728 #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
729 #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
730 #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
731 #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
732 #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
733 #define pmci_tlb_mc pme_tlb.mc
734
735 #define pmci_bus_status_info pme_bus.bsi
736 #define pmci_bus_req_address_valid pme_bus.rq
737 #define pmci_bus_resp_address_valid pme_bus.rp
738 #define pmci_bus_target_address_valid pme_bus.tv
739 #define pmci_bus_error_severity pme_bus.sev
740 #define pmci_bus_transaction_type pme_bus.type
741 #define pmci_bus_cache_cache_transfer pme_bus.cc
742 #define pmci_bus_transaction_size pme_bus.size
743 #define pmci_bus_internal_error pme_bus.ib
744 #define pmci_bus_external_error pme_bus.eb
745 #define pmci_bus_mc pme_bus.mc
746
747
748
749
750
751
752
753 typedef struct pal_min_state_area_s {
754 u64 pmsa_nat_bits;
755 u64 pmsa_gr[15];
756 u64 pmsa_bank0_gr[16];
757 u64 pmsa_bank1_gr[16];
758 u64 pmsa_pr;
759 u64 pmsa_br0;
760 u64 pmsa_rsc;
761 u64 pmsa_iip;
762 u64 pmsa_ipsr;
763 u64 pmsa_ifs;
764 u64 pmsa_xip;
765 u64 pmsa_xpsr;
766 u64 pmsa_xfs;
767 u64 pmsa_br1;
768 u64 pmsa_reserved[70];
769 } pal_min_state_area_t;
770
771
772 struct ia64_pal_retval {
773
774
775
776
777
778
779
780 s64 status;
781 u64 v0;
782 u64 v1;
783 u64 v2;
784 };
785
786
787
788
789
790
791
792 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
793 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
794 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
795 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
796 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
797 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
798
799 #define PAL_CALL(iprv,a0,a1,a2,a3) do { \
800 struct ia64_fpreg fr[6]; \
801 ia64_save_scratch_fpregs(fr); \
802 iprv = ia64_pal_call_static(a0, a1, a2, a3); \
803 ia64_load_scratch_fpregs(fr); \
804 } while (0)
805
806 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
807 struct ia64_fpreg fr[6]; \
808 ia64_save_scratch_fpregs(fr); \
809 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
810 ia64_load_scratch_fpregs(fr); \
811 } while (0)
812
813 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
814 struct ia64_fpreg fr[6]; \
815 ia64_save_scratch_fpregs(fr); \
816 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
817 ia64_load_scratch_fpregs(fr); \
818 } while (0)
819
820 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
821 struct ia64_fpreg fr[6]; \
822 ia64_save_scratch_fpregs(fr); \
823 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
824 ia64_load_scratch_fpregs(fr); \
825 } while (0)
826
827 typedef int (*ia64_pal_handler) (u64, ...);
828 extern ia64_pal_handler ia64_pal;
829 extern void ia64_pal_handler_init (void *);
830
831 extern ia64_pal_handler ia64_pal;
832
833 extern pal_cache_config_info_t l0d_cache_config_info;
834 extern pal_cache_config_info_t l0i_cache_config_info;
835 extern pal_cache_config_info_t l1_cache_config_info;
836 extern pal_cache_config_info_t l2_cache_config_info;
837
838 extern pal_cache_protection_info_t l0d_cache_protection_info;
839 extern pal_cache_protection_info_t l0i_cache_protection_info;
840 extern pal_cache_protection_info_t l1_cache_protection_info;
841 extern pal_cache_protection_info_t l2_cache_protection_info;
842
843 extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
844 pal_cache_type_t);
845
846 extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
847 pal_cache_type_t);
848
849
850 extern void pal_error(int);
851
852
853
854
855 typedef union pal_bus_features_u {
856 u64 pal_bus_features_val;
857 struct {
858 u64 pbf_reserved1 : 29;
859 u64 pbf_req_bus_parking : 1;
860 u64 pbf_bus_lock_mask : 1;
861 u64 pbf_enable_half_xfer_rate : 1;
862 u64 pbf_reserved2 : 20;
863 u64 pbf_enable_shared_line_replace : 1;
864 u64 pbf_enable_exclusive_line_replace : 1;
865 u64 pbf_disable_xaction_queueing : 1;
866 u64 pbf_disable_resp_err_check : 1;
867 u64 pbf_disable_berr_check : 1;
868 u64 pbf_disable_bus_req_internal_err_signal : 1;
869 u64 pbf_disable_bus_req_berr_signal : 1;
870 u64 pbf_disable_bus_init_event_check : 1;
871 u64 pbf_disable_bus_init_event_signal : 1;
872 u64 pbf_disable_bus_addr_err_check : 1;
873 u64 pbf_disable_bus_addr_err_signal : 1;
874 u64 pbf_disable_bus_data_err_check : 1;
875 } pal_bus_features_s;
876 } pal_bus_features_u_t;
877
878 extern void pal_bus_features_print (u64);
879
880
881 static inline s64
882 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
883 pal_bus_features_u_t *features_status,
884 pal_bus_features_u_t *features_control)
885 {
886 struct ia64_pal_retval iprv;
887 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
888 if (features_avail)
889 features_avail->pal_bus_features_val = iprv.v0;
890 if (features_status)
891 features_status->pal_bus_features_val = iprv.v1;
892 if (features_control)
893 features_control->pal_bus_features_val = iprv.v2;
894 return iprv.status;
895 }
896
897
898 static inline s64
899 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
900 {
901 struct ia64_pal_retval iprv;
902 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
903 return iprv.status;
904 }
905
906
907 static inline s64
908 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
909 {
910 struct ia64_pal_retval iprv;
911
912 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
913
914 if (iprv.status == 0) {
915 conf->pcci_status = iprv.status;
916 conf->pcci_info_1.pcci1_data = iprv.v0;
917 conf->pcci_info_2.pcci2_data = iprv.v1;
918 conf->pcci_reserved = iprv.v2;
919 }
920 return iprv.status;
921
922 }
923
924
925 static inline s64
926 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
927 {
928 struct ia64_pal_retval iprv;
929
930 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
931
932 if (iprv.status == 0) {
933 prot->pcpi_status = iprv.status;
934 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
935 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
936 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
937 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
938 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
939 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
940 }
941 return iprv.status;
942 }
943
944
945
946
947
948 static inline s64
949 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
950 {
951 struct ia64_pal_retval iprv;
952 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
953 if (vector)
954 *vector = iprv.v0;
955 *progress = iprv.v1;
956 return iprv.status;
957 }
958
959
960
961 static inline s64
962 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
963 {
964 struct ia64_pal_retval iprv;
965 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
966 return iprv.status;
967 }
968
969
970
971
972
973 static inline s64
974 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
975 {
976 struct ia64_pal_retval iprv;
977 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
978 return iprv.status;
979 }
980
981
982
983 static inline s64
984 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
985 {
986 struct ia64_pal_retval iprv;
987 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
988 physical_addr, 0);
989 return iprv.status;
990 }
991
992
993 static inline long ia64_pal_cache_summary(unsigned long *cache_levels,
994 unsigned long *unique_caches)
995 {
996 struct ia64_pal_retval iprv;
997 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
998 if (cache_levels)
999 *cache_levels = iprv.v0;
1000 if (unique_caches)
1001 *unique_caches = iprv.v1;
1002 return iprv.status;
1003 }
1004
1005
1006 static inline s64
1007 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
1008 {
1009 struct ia64_pal_retval iprv;
1010 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1011 physical_addr, data);
1012 return iprv.status;
1013 }
1014
1015
1016
1017 static inline s64
1018 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1019 u64 *buffer_size, u64 *buffer_align)
1020 {
1021 struct ia64_pal_retval iprv;
1022 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1023 if (buffer_size)
1024 *buffer_size = iprv.v0;
1025 if (buffer_align)
1026 *buffer_align = iprv.v1;
1027 return iprv.status;
1028 }
1029
1030
1031 static inline s64
1032 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1033 {
1034 struct ia64_pal_retval iprv;
1035 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1036 if (pal_proc_offset)
1037 *pal_proc_offset = iprv.v0;
1038 return iprv.status;
1039 }
1040
1041
1042 static inline long ia64_pal_debug_info(unsigned long *inst_regs,
1043 unsigned long *data_regs)
1044 {
1045 struct ia64_pal_retval iprv;
1046 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1047 if (inst_regs)
1048 *inst_regs = iprv.v0;
1049 if (data_regs)
1050 *data_regs = iprv.v1;
1051
1052 return iprv.status;
1053 }
1054
1055 #ifdef TBD
1056
1057 static inline s64
1058 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1059 {
1060 struct ia64_pal_retval iprv;
1061 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1062 return iprv.status;
1063 }
1064 #endif
1065
1066
1067 static inline s64
1068 ia64_pal_fixed_addr (u64 *global_unique_addr)
1069 {
1070 struct ia64_pal_retval iprv;
1071 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1072 if (global_unique_addr)
1073 *global_unique_addr = iprv.v0;
1074 return iprv.status;
1075 }
1076
1077
1078 static inline long ia64_pal_freq_base(unsigned long *platform_base_freq)
1079 {
1080 struct ia64_pal_retval iprv;
1081 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1082 if (platform_base_freq)
1083 *platform_base_freq = iprv.v0;
1084 return iprv.status;
1085 }
1086
1087
1088
1089
1090
1091 static inline s64
1092 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1093 struct pal_freq_ratio *itc_ratio)
1094 {
1095 struct ia64_pal_retval iprv;
1096 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1097 if (proc_ratio)
1098 *(u64 *)proc_ratio = iprv.v0;
1099 if (bus_ratio)
1100 *(u64 *)bus_ratio = iprv.v1;
1101 if (itc_ratio)
1102 *(u64 *)itc_ratio = iprv.v2;
1103 return iprv.status;
1104 }
1105
1106
1107
1108
1109 static inline s64
1110 ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1111 u64 *la)
1112 {
1113 struct ia64_pal_retval iprv;
1114 PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1115 if (cur_policy)
1116 *cur_policy = iprv.v0;
1117 if (num_impacted)
1118 *num_impacted = iprv.v1;
1119 if (la)
1120 *la = iprv.v2;
1121 return iprv.status;
1122 }
1123
1124
1125
1126
1127
1128 static inline s64
1129 ia64_pal_halt (u64 halt_state)
1130 {
1131 struct ia64_pal_retval iprv;
1132 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1133 return iprv.status;
1134 }
1135
1136 typedef union pal_power_mgmt_info_u {
1137 u64 ppmi_data;
1138 struct {
1139 u64 exit_latency : 16,
1140 entry_latency : 16,
1141 power_consumption : 28,
1142 im : 1,
1143 co : 1,
1144 reserved : 2;
1145 } pal_power_mgmt_info_s;
1146 } pal_power_mgmt_info_u_t;
1147
1148
1149 static inline s64
1150 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1151 {
1152 struct ia64_pal_retval iprv;
1153 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1154 return iprv.status;
1155 }
1156
1157
1158 static inline s64
1159 ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1160 {
1161 struct ia64_pal_retval iprv;
1162 PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1163 *pstate_index = iprv.v0;
1164 return iprv.status;
1165 }
1166
1167
1168 static inline s64
1169 ia64_pal_set_pstate (u64 pstate_index)
1170 {
1171 struct ia64_pal_retval iprv;
1172 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1173 return iprv.status;
1174 }
1175
1176
1177 static inline s64
1178 ia64_pal_get_brand_info (char *brand_info)
1179 {
1180 struct ia64_pal_retval iprv;
1181 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1182 return iprv.status;
1183 }
1184
1185
1186
1187
1188 static inline s64
1189 ia64_pal_halt_light (void)
1190 {
1191 struct ia64_pal_retval iprv;
1192 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1193 return iprv.status;
1194 }
1195
1196
1197
1198
1199
1200 static inline s64
1201 ia64_pal_mc_clear_log (u64 *pending_vector)
1202 {
1203 struct ia64_pal_retval iprv;
1204 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1205 if (pending_vector)
1206 *pending_vector = iprv.v0;
1207 return iprv.status;
1208 }
1209
1210
1211
1212
1213 static inline s64
1214 ia64_pal_mc_drain (void)
1215 {
1216 struct ia64_pal_retval iprv;
1217 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1218 return iprv.status;
1219 }
1220
1221
1222 static inline s64
1223 ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
1224 {
1225 struct ia64_pal_retval iprv;
1226 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
1227 if (size)
1228 *size = iprv.v0;
1229 return iprv.status;
1230 }
1231
1232
1233 static inline s64
1234 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1235 {
1236 struct ia64_pal_retval iprv;
1237 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1238 if (size)
1239 *size = iprv.v0;
1240 if (error_info)
1241 *error_info = iprv.v1;
1242 return iprv.status;
1243 }
1244
1245
1246
1247
1248 static inline s64
1249 ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
1250 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1251 {
1252 struct ia64_pal_retval iprv;
1253 PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1254 err_struct_info, err_data_buffer);
1255 if (capabilities)
1256 *capabilities= iprv.v0;
1257 if (resources)
1258 *resources= iprv.v1;
1259 return iprv.status;
1260 }
1261
1262 static inline s64
1263 ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
1264 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1265 {
1266 struct ia64_pal_retval iprv;
1267 PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1268 err_struct_info, err_data_buffer);
1269 if (capabilities)
1270 *capabilities= iprv.v0;
1271 if (resources)
1272 *resources= iprv.v1;
1273 return iprv.status;
1274 }
1275
1276
1277
1278
1279 static inline s64
1280 ia64_pal_mc_expected (u64 expected, u64 *previous)
1281 {
1282 struct ia64_pal_retval iprv;
1283 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1284 if (previous)
1285 *previous = iprv.v0;
1286 return iprv.status;
1287 }
1288
1289 typedef union pal_hw_tracking_u {
1290 u64 pht_data;
1291 struct {
1292 u64 itc :4,
1293 dct :4,
1294 itt :4,
1295 ddt :4,
1296 reserved:48;
1297 } pal_hw_tracking_s;
1298 } pal_hw_tracking_u_t;
1299
1300
1301
1302
1303 static inline s64
1304 ia64_pal_mc_hw_tracking (u64 *status)
1305 {
1306 struct ia64_pal_retval iprv;
1307 PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
1308 if (status)
1309 *status = iprv.v0;
1310 return iprv.status;
1311 }
1312
1313
1314
1315
1316
1317 static inline s64
1318 ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
1319 {
1320 struct ia64_pal_retval iprv;
1321 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
1322 if (req_size)
1323 *req_size = iprv.v0;
1324 return iprv.status;
1325 }
1326
1327
1328
1329
1330 static inline s64
1331 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1332 {
1333 struct ia64_pal_retval iprv;
1334 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1335 return iprv.status;
1336 }
1337
1338
1339 static inline s64
1340 ia64_pal_mem_attrib (u64 *mem_attrib)
1341 {
1342 struct ia64_pal_retval iprv;
1343 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1344 if (mem_attrib)
1345 *mem_attrib = iprv.v0 & 0xff;
1346 return iprv.status;
1347 }
1348
1349
1350
1351
1352 static inline s64
1353 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1354 {
1355 struct ia64_pal_retval iprv;
1356 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1357 if (bytes_needed)
1358 *bytes_needed = iprv.v0;
1359 if (alignment)
1360 *alignment = iprv.v1;
1361 return iprv.status;
1362 }
1363
1364 typedef union pal_perf_mon_info_u {
1365 u64 ppmi_data;
1366 struct {
1367 u64 generic : 8,
1368 width : 8,
1369 cycles : 8,
1370 retired : 8,
1371 reserved : 32;
1372 } pal_perf_mon_info_s;
1373 } pal_perf_mon_info_u_t;
1374
1375
1376
1377
1378 static inline s64
1379 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1380 {
1381 struct ia64_pal_retval iprv;
1382 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1383 if (pm_info)
1384 pm_info->ppmi_data = iprv.v0;
1385 return iprv.status;
1386 }
1387
1388
1389
1390
1391 static inline s64
1392 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1393 {
1394 struct ia64_pal_retval iprv;
1395 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1396 return iprv.status;
1397 }
1398
1399
1400 static inline s64
1401 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1402 {
1403 struct ia64_pal_retval iprv;
1404 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1405 return iprv.status;
1406 }
1407
1408 struct pal_features_s;
1409
1410 static inline s64
1411 ia64_pal_proc_get_features (u64 *features_avail,
1412 u64 *features_status,
1413 u64 *features_control,
1414 u64 features_set)
1415 {
1416 struct ia64_pal_retval iprv;
1417 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0);
1418 if (iprv.status == 0) {
1419 *features_avail = iprv.v0;
1420 *features_status = iprv.v1;
1421 *features_control = iprv.v2;
1422 }
1423 return iprv.status;
1424 }
1425
1426
1427 static inline s64
1428 ia64_pal_proc_set_features (u64 feature_select)
1429 {
1430 struct ia64_pal_retval iprv;
1431 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1432 return iprv.status;
1433 }
1434
1435
1436
1437
1438
1439 typedef struct ia64_ptce_info_s {
1440 unsigned long base;
1441 u32 count[2];
1442 u32 stride[2];
1443 } ia64_ptce_info_t;
1444
1445
1446
1447
1448 static inline s64
1449 ia64_get_ptce (ia64_ptce_info_t *ptce)
1450 {
1451 struct ia64_pal_retval iprv;
1452
1453 if (!ptce)
1454 return -1;
1455
1456 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1457 if (iprv.status == 0) {
1458 ptce->base = iprv.v0;
1459 ptce->count[0] = iprv.v1 >> 32;
1460 ptce->count[1] = iprv.v1 & 0xffffffff;
1461 ptce->stride[0] = iprv.v2 >> 32;
1462 ptce->stride[1] = iprv.v2 & 0xffffffff;
1463 }
1464 return iprv.status;
1465 }
1466
1467
1468 static inline s64
1469 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1470 {
1471 struct ia64_pal_retval iprv;
1472 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1473 if (reg_info_1)
1474 *reg_info_1 = iprv.v0;
1475 if (reg_info_2)
1476 *reg_info_2 = iprv.v1;
1477 return iprv.status;
1478 }
1479
1480 typedef union pal_hints_u {
1481 unsigned long ph_data;
1482 struct {
1483 unsigned long si : 1,
1484 li : 1,
1485 reserved : 62;
1486 } pal_hints_s;
1487 } pal_hints_u_t;
1488
1489
1490
1491
1492 static inline long ia64_pal_rse_info(unsigned long *num_phys_stacked,
1493 pal_hints_u_t *hints)
1494 {
1495 struct ia64_pal_retval iprv;
1496 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1497 if (num_phys_stacked)
1498 *num_phys_stacked = iprv.v0;
1499 if (hints)
1500 hints->ph_data = iprv.v1;
1501 return iprv.status;
1502 }
1503
1504
1505
1506
1507 static inline s64
1508 ia64_pal_set_hw_policy (u64 policy)
1509 {
1510 struct ia64_pal_retval iprv;
1511 PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1512 return iprv.status;
1513 }
1514
1515
1516
1517
1518
1519 static inline s64
1520 ia64_pal_shutdown (void)
1521 {
1522 struct ia64_pal_retval iprv;
1523 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1524 return iprv.status;
1525 }
1526
1527
1528 static inline s64
1529 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1530 {
1531 struct ia64_pal_retval iprv;
1532 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1533 if (self_test_state)
1534 *self_test_state = iprv.v0;
1535 return iprv.status;
1536 }
1537
1538 typedef union pal_version_u {
1539 u64 pal_version_val;
1540 struct {
1541 u64 pv_pal_b_rev : 8;
1542 u64 pv_pal_b_model : 8;
1543 u64 pv_reserved1 : 8;
1544 u64 pv_pal_vendor : 8;
1545 u64 pv_pal_a_rev : 8;
1546 u64 pv_pal_a_model : 8;
1547 u64 pv_reserved2 : 16;
1548 } pal_version_s;
1549 } pal_version_u_t;
1550
1551
1552
1553
1554
1555
1556
1557
1558 static inline s64
1559 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1560 {
1561 struct ia64_pal_retval iprv;
1562 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1563 if (pal_min_version)
1564 pal_min_version->pal_version_val = iprv.v0;
1565
1566 if (pal_cur_version)
1567 pal_cur_version->pal_version_val = iprv.v1;
1568
1569 return iprv.status;
1570 }
1571
1572 typedef union pal_tc_info_u {
1573 u64 pti_val;
1574 struct {
1575 u64 num_sets : 8,
1576 associativity : 8,
1577 num_entries : 16,
1578 pf : 1,
1579 unified : 1,
1580 reduce_tr : 1,
1581 reserved : 29;
1582 } pal_tc_info_s;
1583 } pal_tc_info_u_t;
1584
1585 #define tc_reduce_tr pal_tc_info_s.reduce_tr
1586 #define tc_unified pal_tc_info_s.unified
1587 #define tc_pf pal_tc_info_s.pf
1588 #define tc_num_entries pal_tc_info_s.num_entries
1589 #define tc_associativity pal_tc_info_s.associativity
1590 #define tc_num_sets pal_tc_info_s.num_sets
1591
1592
1593
1594
1595
1596 static inline s64
1597 ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1598 {
1599 struct ia64_pal_retval iprv;
1600 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1601 if (tc_info)
1602 tc_info->pti_val = iprv.v0;
1603 if (tc_pages)
1604 *tc_pages = iprv.v1;
1605 return iprv.status;
1606 }
1607
1608
1609
1610
1611 static inline s64 ia64_pal_vm_page_size(u64 *tr_pages, u64 *vw_pages)
1612 {
1613 struct ia64_pal_retval iprv;
1614 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1615 if (tr_pages)
1616 *tr_pages = iprv.v0;
1617 if (vw_pages)
1618 *vw_pages = iprv.v1;
1619 return iprv.status;
1620 }
1621
1622 typedef union pal_vm_info_1_u {
1623 u64 pvi1_val;
1624 struct {
1625 u64 vw : 1,
1626 phys_add_size : 7,
1627 key_size : 8,
1628 max_pkr : 8,
1629 hash_tag_id : 8,
1630 max_dtr_entry : 8,
1631 max_itr_entry : 8,
1632 max_unique_tcs : 8,
1633 num_tc_levels : 8;
1634 } pal_vm_info_1_s;
1635 } pal_vm_info_1_u_t;
1636
1637 #define PAL_MAX_PURGES 0xFFFF
1638
1639 typedef union pal_vm_info_2_u {
1640 u64 pvi2_val;
1641 struct {
1642 u64 impl_va_msb : 8,
1643 rid_size : 8,
1644 max_purges : 16,
1645 reserved : 32;
1646 } pal_vm_info_2_s;
1647 } pal_vm_info_2_u_t;
1648
1649
1650
1651
1652 static inline s64
1653 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1654 {
1655 struct ia64_pal_retval iprv;
1656 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1657 if (vm_info_1)
1658 vm_info_1->pvi1_val = iprv.v0;
1659 if (vm_info_2)
1660 vm_info_2->pvi2_val = iprv.v1;
1661 return iprv.status;
1662 }
1663
1664 typedef union pal_vp_info_u {
1665 u64 pvi_val;
1666 struct {
1667 u64 index: 48,
1668 vmm_id: 16;
1669 } pal_vp_info_s;
1670 } pal_vp_info_u_t;
1671
1672
1673
1674
1675 static inline s64
1676 ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
1677 {
1678 struct ia64_pal_retval iprv;
1679 PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
1680 if (vp_info)
1681 *vp_info = iprv.v0;
1682 if (vmm_id)
1683 *vmm_id = iprv.v1;
1684 return iprv.status;
1685 }
1686
1687 typedef union pal_itr_valid_u {
1688 u64 piv_val;
1689 struct {
1690 u64 access_rights_valid : 1,
1691 priv_level_valid : 1,
1692 dirty_bit_valid : 1,
1693 mem_attr_valid : 1,
1694 reserved : 60;
1695 } pal_tr_valid_s;
1696 } pal_tr_valid_u_t;
1697
1698
1699 static inline s64
1700 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1701 {
1702 struct ia64_pal_retval iprv;
1703 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1704 if (tr_valid)
1705 tr_valid->piv_val = iprv.v0;
1706 return iprv.status;
1707 }
1708
1709
1710
1711
1712 #define PAL_VISIBILITY_VIRTUAL 0
1713 #define PAL_VISIBILITY_PHYSICAL 1
1714
1715
1716
1717
1718 #define PAL_VISIBILITY_OK 1
1719 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1720 #define PAL_VISIBILITY_INVAL_ARG -2
1721 #define PAL_VISIBILITY_ERROR -3
1722
1723 static inline s64
1724 ia64_pal_prefetch_visibility (s64 trans_type)
1725 {
1726 struct ia64_pal_retval iprv;
1727 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1728 return iprv.status;
1729 }
1730
1731
1732 typedef union pal_log_overview_u {
1733 struct {
1734 u64 num_log :16,
1735
1736
1737 tpc :8,
1738 reserved3 :8,
1739 cpp :8,
1740 reserved2 :8,
1741 ppid :8,
1742 reserved1 :8;
1743 } overview_bits;
1744 u64 overview_data;
1745 } pal_log_overview_t;
1746
1747 typedef union pal_proc_n_log_info1_u{
1748 struct {
1749 u64 tid :16,
1750 reserved2 :16,
1751 cid :16,
1752 reserved1 :16;
1753 } ppli1_bits;
1754 u64 ppli1_data;
1755 } pal_proc_n_log_info1_t;
1756
1757 typedef union pal_proc_n_log_info2_u {
1758 struct {
1759 u64 la :16,
1760 reserved :48;
1761 } ppli2_bits;
1762 u64 ppli2_data;
1763 } pal_proc_n_log_info2_t;
1764
1765 typedef struct pal_logical_to_physical_s
1766 {
1767 pal_log_overview_t overview;
1768 pal_proc_n_log_info1_t ppli1;
1769 pal_proc_n_log_info2_t ppli2;
1770 } pal_logical_to_physical_t;
1771
1772 #define overview_num_log overview.overview_bits.num_log
1773 #define overview_tpc overview.overview_bits.tpc
1774 #define overview_cpp overview.overview_bits.cpp
1775 #define overview_ppid overview.overview_bits.ppid
1776 #define log1_tid ppli1.ppli1_bits.tid
1777 #define log1_cid ppli1.ppli1_bits.cid
1778 #define log2_la ppli2.ppli2_bits.la
1779
1780
1781 static inline s64
1782 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1783 {
1784 struct ia64_pal_retval iprv;
1785
1786 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1787
1788 if (iprv.status == PAL_STATUS_SUCCESS)
1789 {
1790 mapping->overview.overview_data = iprv.v0;
1791 mapping->ppli1.ppli1_data = iprv.v1;
1792 mapping->ppli2.ppli2_data = iprv.v2;
1793 }
1794
1795 return iprv.status;
1796 }
1797
1798 typedef struct pal_cache_shared_info_s
1799 {
1800 u64 num_shared;
1801 pal_proc_n_log_info1_t ppli1;
1802 pal_proc_n_log_info2_t ppli2;
1803 } pal_cache_shared_info_t;
1804
1805
1806 static inline s64
1807 ia64_pal_cache_shared_info(u64 level,
1808 u64 type,
1809 u64 proc_number,
1810 pal_cache_shared_info_t *info)
1811 {
1812 struct ia64_pal_retval iprv;
1813
1814 PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1815
1816 if (iprv.status == PAL_STATUS_SUCCESS) {
1817 info->num_shared = iprv.v0;
1818 info->ppli1.ppli1_data = iprv.v1;
1819 info->ppli2.ppli2_data = iprv.v2;
1820 }
1821
1822 return iprv.status;
1823 }
1824 #endif
1825
1826 #endif