arch/ia64/include/asm/pgtable.h

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
ia64_phys_addr_valid
set_pte
pgd_index
pgd_offset
ptep_test_and_clear_young
ptep_get_and_clear
ptep_set_wrprotect
pte_same
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_IA64_PGTABLE_H
   3 #define _ASM_IA64_PGTABLE_H
   4 
   5 /*
   6  * This file contains the functions and defines necessary to modify and use
   7  * the IA-64 page table tree.
   8  *
   9  * This hopefully works with any (fixed) IA-64 page-size, as defined
  10  * in <asm/page.h>.
  11  *
  12  * Copyright (C) 1998-2005 Hewlett-Packard Co
  13  *      David Mosberger-Tang <davidm@hpl.hp.com>
  14  */
  15 
  16 
  17 #include <asm/mman.h>
  18 #include <asm/page.h>
  19 #include <asm/processor.h>
  20 #include <asm/types.h>
  21 
  22 #define IA64_MAX_PHYS_BITS      50      /* max. number of physical address bits (architected) */
  23 
  24 /*
  25  * First, define the various bits in a PTE.  Note that the PTE format
  26  * matches the VHPT short format, the firt doubleword of the VHPD long
  27  * format, and the first doubleword of the TLB insertion format.
  28  */
  29 #define _PAGE_P_BIT             0
  30 #define _PAGE_A_BIT             5
  31 #define _PAGE_D_BIT             6
  32 
  33 #define _PAGE_P                 (1 << _PAGE_P_BIT)      /* page present bit */
  34 #define _PAGE_MA_WB             (0x0 <<  2)     /* write back memory attribute */
  35 #define _PAGE_MA_UC             (0x4 <<  2)     /* uncacheable memory attribute */
  36 #define _PAGE_MA_UCE            (0x5 <<  2)     /* UC exported attribute */
  37 #define _PAGE_MA_WC             (0x6 <<  2)     /* write coalescing memory attribute */
  38 #define _PAGE_MA_NAT            (0x7 <<  2)     /* not-a-thing attribute */
  39 #define _PAGE_MA_MASK           (0x7 <<  2)
  40 #define _PAGE_PL_0              (0 <<  7)       /* privilege level 0 (kernel) */
  41 #define _PAGE_PL_1              (1 <<  7)       /* privilege level 1 (unused) */
  42 #define _PAGE_PL_2              (2 <<  7)       /* privilege level 2 (unused) */
  43 #define _PAGE_PL_3              (3 <<  7)       /* privilege level 3 (user) */
  44 #define _PAGE_PL_MASK           (3 <<  7)
  45 #define _PAGE_AR_R              (0 <<  9)       /* read only */
  46 #define _PAGE_AR_RX             (1 <<  9)       /* read & execute */
  47 #define _PAGE_AR_RW             (2 <<  9)       /* read & write */
  48 #define _PAGE_AR_RWX            (3 <<  9)       /* read, write & execute */
  49 #define _PAGE_AR_R_RW           (4 <<  9)       /* read / read & write */
  50 #define _PAGE_AR_RX_RWX         (5 <<  9)       /* read & exec / read, write & exec */
  51 #define _PAGE_AR_RWX_RW         (6 <<  9)       /* read, write & exec / read & write */
  52 #define _PAGE_AR_X_RX           (7 <<  9)       /* exec & promote / read & exec */
  53 #define _PAGE_AR_MASK           (7 <<  9)
  54 #define _PAGE_AR_SHIFT          9
  55 #define _PAGE_A                 (1 << _PAGE_A_BIT)      /* page accessed bit */
  56 #define _PAGE_D                 (1 << _PAGE_D_BIT)      /* page dirty bit */
  57 #define _PAGE_PPN_MASK          (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
  58 #define _PAGE_ED                (__IA64_UL(1) << 52)    /* exception deferral */
  59 #define _PAGE_PROTNONE          (__IA64_UL(1) << 63)
  60 
  61 #define _PFN_MASK               _PAGE_PPN_MASK
  62 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
  63 #define _PAGE_CHG_MASK  (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
  64 
  65 #define _PAGE_SIZE_4K   12
  66 #define _PAGE_SIZE_8K   13
  67 #define _PAGE_SIZE_16K  14
  68 #define _PAGE_SIZE_64K  16
  69 #define _PAGE_SIZE_256K 18
  70 #define _PAGE_SIZE_1M   20
  71 #define _PAGE_SIZE_4M   22
  72 #define _PAGE_SIZE_16M  24
  73 #define _PAGE_SIZE_64M  26
  74 #define _PAGE_SIZE_256M 28
  75 #define _PAGE_SIZE_1G   30
  76 #define _PAGE_SIZE_4G   32
  77 
  78 #define __ACCESS_BITS           _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
  79 #define __DIRTY_BITS_NO_ED      _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
  80 #define __DIRTY_BITS            _PAGE_ED | __DIRTY_BITS_NO_ED
  81 
  82 /*
  83  * How many pointers will a page table level hold expressed in shift
  84  */
  85 #define PTRS_PER_PTD_SHIFT      (PAGE_SHIFT-3)
  86 
  87 /*
  88  * Definitions for fourth level:
  89  */
  90 #define PTRS_PER_PTE    (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
  91 
  92 /*
  93  * Definitions for third level:
  94  *
  95  * PMD_SHIFT determines the size of the area a third-level page table
  96  * can map.
  97  */
  98 #define PMD_SHIFT       (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
  99 #define PMD_SIZE        (1UL << PMD_SHIFT)
 100 #define PMD_MASK        (~(PMD_SIZE-1))
 101 #define PTRS_PER_PMD    (1UL << (PTRS_PER_PTD_SHIFT))
 102 
 103 #if CONFIG_PGTABLE_LEVELS == 4
 104 /*
 105  * Definitions for second level:
 106  *
 107  * PUD_SHIFT determines the size of the area a second-level page table
 108  * can map.
 109  */
 110 #define PUD_SHIFT       (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
 111 #define PUD_SIZE        (1UL << PUD_SHIFT)
 112 #define PUD_MASK        (~(PUD_SIZE-1))
 113 #define PTRS_PER_PUD    (1UL << (PTRS_PER_PTD_SHIFT))
 114 #endif
 115 
 116 /*
 117  * Definitions for first level:
 118  *
 119  * PGDIR_SHIFT determines what a first-level page table entry can map.
 120  */
 121 #if CONFIG_PGTABLE_LEVELS == 4
 122 #define PGDIR_SHIFT             (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
 123 #else
 124 #define PGDIR_SHIFT             (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
 125 #endif
 126 #define PGDIR_SIZE              (__IA64_UL(1) << PGDIR_SHIFT)
 127 #define PGDIR_MASK              (~(PGDIR_SIZE-1))
 128 #define PTRS_PER_PGD_SHIFT      PTRS_PER_PTD_SHIFT
 129 #define PTRS_PER_PGD            (1UL << PTRS_PER_PGD_SHIFT)
 130 #define USER_PTRS_PER_PGD       (5*PTRS_PER_PGD/8)      /* regions 0-4 are user regions */
 131 #define FIRST_USER_ADDRESS      0UL
 132 
 133 /*
 134  * All the normal masks have the "page accessed" bits on, as any time
 135  * they are used, the page is accessed. They are cleared only by the
 136  * page-out routines.
 137  */
 138 #define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_A)
 139 #define PAGE_SHARED     __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
 140 #define PAGE_READONLY   __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
 141 #define PAGE_COPY       __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
 142 #define PAGE_COPY_EXEC  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 143 #define PAGE_GATE       __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
 144 #define PAGE_KERNEL     __pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX)
 145 #define PAGE_KERNELRX   __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
 146 #define PAGE_KERNEL_UC  __pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX | \
 147                                  _PAGE_MA_UC)
 148 
 149 # ifndef __ASSEMBLY__
 150 
 151 #include <linux/sched/mm.h>     /* for mm_struct */
 152 #include <linux/bitops.h>
 153 #include <asm/cacheflush.h>
 154 #include <asm/mmu_context.h>
 155 
 156 /*
 157  * Next come the mappings that determine how mmap() protection bits
 158  * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented.  The
 159  * _P version gets used for a private shared memory segment, the _S
 160  * version gets used for a shared memory segment with MAP_SHARED on.
 161  * In a private shared memory segment, we do a copy-on-write if a task
 162  * attempts to write to the page.
 163  */
 164         /* xwr */
 165 #define __P000  PAGE_NONE
 166 #define __P001  PAGE_READONLY
 167 #define __P010  PAGE_READONLY   /* write to priv pg -> copy & make writable */
 168 #define __P011  PAGE_READONLY   /* ditto */
 169 #define __P100  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
 170 #define __P101  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 171 #define __P110  PAGE_COPY_EXEC
 172 #define __P111  PAGE_COPY_EXEC
 173 
 174 #define __S000  PAGE_NONE
 175 #define __S001  PAGE_READONLY
 176 #define __S010  PAGE_SHARED     /* we don't have (and don't need) write-only */
 177 #define __S011  PAGE_SHARED
 178 #define __S100  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
 179 #define __S101  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 180 #define __S110  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
 181 #define __S111  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
 182 
 183 #define pgd_ERROR(e)    printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
 184 #if CONFIG_PGTABLE_LEVELS == 4
 185 #define pud_ERROR(e)    printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
 186 #endif
 187 #define pmd_ERROR(e)    printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
 188 #define pte_ERROR(e)    printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
 189 
 190 
 191 /*
 192  * Some definitions to translate between mem_map, PTEs, and page addresses:
 193  */
 194 
 195 
 196 /* Quick test to see if ADDR is a (potentially) valid physical address. */
 197 static inline long
 198 ia64_phys_addr_valid (unsigned long addr)
 199 {
 200         return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
 201 }
 202 
 203 /*
 204  * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
 205  * memory.  For the return value to be meaningful, ADDR must be >=
 206  * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
 207  * require a hash-, or multi-level tree-lookup or something of that
 208  * sort) but it guarantees to return TRUE only if accessing the page
 209  * at that address does not cause an error.  Note that there may be
 210  * addresses for which kern_addr_valid() returns FALSE even though an
 211  * access would not cause an error (e.g., this is typically true for
 212  * memory mapped I/O regions.
 213  *
 214  * XXX Need to implement this for IA-64.
 215  */
 216 #define kern_addr_valid(addr)   (1)
 217 
 218 
 219 /*
 220  * Now come the defines and routines to manage and access the three-level
 221  * page table.
 222  */
 223 
 224 
 225 #define VMALLOC_START           (RGN_BASE(RGN_GATE) + 0x200000000UL)
 226 #ifdef CONFIG_VIRTUAL_MEM_MAP
 227 # define VMALLOC_END_INIT       (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
 228 extern unsigned long VMALLOC_END;
 229 #else
 230 #if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
 231 /* SPARSEMEM_VMEMMAP uses half of vmalloc... */
 232 # define VMALLOC_END            (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
 233 # define vmemmap                ((struct page *)VMALLOC_END)
 234 #else
 235 # define VMALLOC_END            (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
 236 #endif
 237 #endif
 238 
 239 /* fs/proc/kcore.c */
 240 #define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
 241 #define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
 242 
 243 #define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
 244 #define RGN_MAP_LIMIT   ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE)    /* per region addr limit */
 245 
 246 /*
 247  * Conversion functions: convert page frame number (pfn) and a protection value to a page
 248  * table entry (pte).
 249  */
 250 #define pfn_pte(pfn, pgprot) \
 251 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
 252 
 253 /* Extract pfn from pte.  */
 254 #define pte_pfn(_pte)           ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
 255 
 256 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 257 
 258 /* This takes a physical page address that is used by the remapping functions */
 259 #define mk_pte_phys(physpage, pgprot) \
 260 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
 261 
 262 #define pte_modify(_pte, newprot) \
 263         (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
 264 
 265 #define pte_none(pte)                   (!pte_val(pte))
 266 #define pte_present(pte)                (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
 267 #define pte_clear(mm,addr,pte)          (pte_val(*(pte)) = 0UL)
 268 /* pte_page() returns the "struct page *" corresponding to the PTE: */
 269 #define pte_page(pte)                   virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
 270 
 271 #define pmd_none(pmd)                   (!pmd_val(pmd))
 272 #define pmd_bad(pmd)                    (!ia64_phys_addr_valid(pmd_val(pmd)))
 273 #define pmd_present(pmd)                (pmd_val(pmd) != 0UL)
 274 #define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0UL)
 275 #define pmd_page_vaddr(pmd)             ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
 276 #define pmd_page(pmd)                   virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
 277 
 278 #define pud_none(pud)                   (!pud_val(pud))
 279 #define pud_bad(pud)                    (!ia64_phys_addr_valid(pud_val(pud)))
 280 #define pud_present(pud)                (pud_val(pud) != 0UL)
 281 #define pud_clear(pudp)                 (pud_val(*(pudp)) = 0UL)
 282 #define pud_page_vaddr(pud)             ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
 283 #define pud_page(pud)                   virt_to_page((pud_val(pud) + PAGE_OFFSET))
 284 
 285 #if CONFIG_PGTABLE_LEVELS == 4
 286 #define pgd_none(pgd)                   (!pgd_val(pgd))
 287 #define pgd_bad(pgd)                    (!ia64_phys_addr_valid(pgd_val(pgd)))
 288 #define pgd_present(pgd)                (pgd_val(pgd) != 0UL)
 289 #define pgd_clear(pgdp)                 (pgd_val(*(pgdp)) = 0UL)
 290 #define pgd_page_vaddr(pgd)             ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
 291 #define pgd_page(pgd)                   virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
 292 #endif
 293 
 294 /*
 295  * The following have defined behavior only work if pte_present() is true.
 296  */
 297 #define pte_write(pte)  ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
 298 #define pte_exec(pte)           ((pte_val(pte) & _PAGE_AR_RX) != 0)
 299 #define pte_dirty(pte)          ((pte_val(pte) & _PAGE_D) != 0)
 300 #define pte_young(pte)          ((pte_val(pte) & _PAGE_A) != 0)
 301 #define pte_special(pte)        0
 302 
 303 /*
 304  * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
 305  * access rights:
 306  */
 307 #define pte_wrprotect(pte)      (__pte(pte_val(pte) & ~_PAGE_AR_RW))
 308 #define pte_mkwrite(pte)        (__pte(pte_val(pte) | _PAGE_AR_RW))
 309 #define pte_mkold(pte)          (__pte(pte_val(pte) & ~_PAGE_A))
 310 #define pte_mkyoung(pte)        (__pte(pte_val(pte) | _PAGE_A))
 311 #define pte_mkclean(pte)        (__pte(pte_val(pte) & ~_PAGE_D))
 312 #define pte_mkdirty(pte)        (__pte(pte_val(pte) | _PAGE_D))
 313 #define pte_mkhuge(pte)         (__pte(pte_val(pte)))
 314 #define pte_mkspecial(pte)      (pte)
 315 
 316 /*
 317  * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
 318  * sync icache and dcache when we insert *new* executable page.
 319  *  __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
 320  * if necessary.
 321  *
 322  *  set_pte() is also called by the kernel, but we can expect that the kernel
 323  *  flushes icache explicitly if necessary.
 324  */
 325 #define pte_present_exec_user(pte)\
 326         ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
 327                 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
 328 
 329 extern void __ia64_sync_icache_dcache(pte_t pteval);
 330 static inline void set_pte(pte_t *ptep, pte_t pteval)
 331 {
 332         /* page is present && page is user  && page is executable
 333          * && (page swapin or new page or page migraton
 334          *      || copy_on_write with page copying.)
 335          */
 336         if (pte_present_exec_user(pteval) &&
 337             (!pte_present(*ptep) ||
 338                 pte_pfn(*ptep) != pte_pfn(pteval)))
 339                 /* load_module() calles flush_icache_range() explicitly*/
 340                 __ia64_sync_icache_dcache(pteval);
 341         *ptep = pteval;
 342 }
 343 
 344 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 345 
 346 /*
 347  * Make page protection values cacheable, uncacheable, or write-
 348  * combining.  Note that "protection" is really a misnomer here as the
 349  * protection value contains the memory attribute bits, dirty bits, and
 350  * various other bits as well.
 351  */
 352 #define pgprot_cacheable(prot)          __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
 353 #define pgprot_noncached(prot)          __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
 354 #define pgprot_writecombine(prot)       __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
 355 
 356 struct file;
 357 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 358                                      unsigned long size, pgprot_t vma_prot);
 359 #define __HAVE_PHYS_MEM_ACCESS_PROT
 360 
 361 static inline unsigned long
 362 pgd_index (unsigned long address)
 363 {
 364         unsigned long region = address >> 61;
 365         unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
 366 
 367         return (region << (PAGE_SHIFT - 6)) | l1index;
 368 }
 369 
 370 /* The offset in the 1-level directory is given by the 3 region bits
 371    (61..63) and the level-1 bits.  */
 372 static inline pgd_t*
 373 pgd_offset (const struct mm_struct *mm, unsigned long address)
 374 {
 375         return mm->pgd + pgd_index(address);
 376 }
 377 
 378 /* In the kernel's mapped region we completely ignore the region number
 379    (since we know it's in region number 5). */
 380 #define pgd_offset_k(addr) \
 381         (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
 382 
 383 /* Look up a pgd entry in the gate area.  On IA-64, the gate-area
 384    resides in the kernel-mapped segment, hence we use pgd_offset_k()
 385    here.  */
 386 #define pgd_offset_gate(mm, addr)       pgd_offset_k(addr)
 387 
 388 #if CONFIG_PGTABLE_LEVELS == 4
 389 /* Find an entry in the second-level page table.. */
 390 #define pud_offset(dir,addr) \
 391         ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
 392 #endif
 393 
 394 /* Find an entry in the third-level page table.. */
 395 #define pmd_offset(dir,addr) \
 396         ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 397 
 398 /*
 399  * Find an entry in the third-level page table.  This looks more complicated than it
 400  * should be because some platforms place page tables in high memory.
 401  */
 402 #define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 403 #define pte_offset_kernel(dir,addr)     ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 404 #define pte_offset_map(dir,addr)        pte_offset_kernel(dir, addr)
 405 #define pte_unmap(pte)                  do { } while (0)
 406 
 407 /* atomic versions of the some PTE manipulations: */
 408 
 409 static inline int
 410 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 411 {
 412 #ifdef CONFIG_SMP
 413         if (!pte_young(*ptep))
 414                 return 0;
 415         return test_and_clear_bit(_PAGE_A_BIT, ptep);
 416 #else
 417         pte_t pte = *ptep;
 418         if (!pte_young(pte))
 419                 return 0;
 420         set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
 421         return 1;
 422 #endif
 423 }
 424 
 425 static inline pte_t
 426 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 427 {
 428 #ifdef CONFIG_SMP
 429         return __pte(xchg((long *) ptep, 0));
 430 #else
 431         pte_t pte = *ptep;
 432         pte_clear(mm, addr, ptep);
 433         return pte;
 434 #endif
 435 }
 436 
 437 static inline void
 438 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 439 {
 440 #ifdef CONFIG_SMP
 441         unsigned long new, old;
 442 
 443         do {
 444                 old = pte_val(*ptep);
 445                 new = pte_val(pte_wrprotect(__pte (old)));
 446         } while (cmpxchg((unsigned long *) ptep, old, new) != old);
 447 #else
 448         pte_t old_pte = *ptep;
 449         set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
 450 #endif
 451 }
 452 
 453 static inline int
 454 pte_same (pte_t a, pte_t b)
 455 {
 456         return pte_val(a) == pte_val(b);
 457 }
 458 
 459 #define update_mmu_cache(vma, address, ptep) do { } while (0)
 460 
 461 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 462 extern void paging_init (void);
 463 
 464 /*
 465  * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
 466  *       bits in the swap-type field of the swap pte.  It would be nice to
 467  *       enforce that, but we can't easily include <linux/swap.h> here.
 468  *       (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
 469  *
 470  * Format of swap pte:
 471  *      bit   0   : present bit (must be zero)
 472  *      bits  1- 7: swap-type
 473  *      bits  8-62: swap offset
 474  *      bit  63   : _PAGE_PROTNONE bit
 475  */
 476 #define __swp_type(entry)               (((entry).val >> 1) & 0x7f)
 477 #define __swp_offset(entry)             (((entry).val << 1) >> 9)
 478 #define __swp_entry(type,offset)        ((swp_entry_t) { ((type) << 1) | ((long) (offset) << 8) })
 479 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 480 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 481 
 482 /*
 483  * ZERO_PAGE is a global shared page that is always zero: used
 484  * for zero-mapped memory areas etc..
 485  */
 486 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 487 extern struct page *zero_page_memmap_ptr;
 488 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
 489 
 490 /* We provide our own get_unmapped_area to cope with VA holes for userland */
 491 #define HAVE_ARCH_UNMAPPED_AREA
 492 
 493 #ifdef CONFIG_HUGETLB_PAGE
 494 #define HUGETLB_PGDIR_SHIFT     (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
 495 #define HUGETLB_PGDIR_SIZE      (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
 496 #define HUGETLB_PGDIR_MASK      (~(HUGETLB_PGDIR_SIZE-1))
 497 #endif
 498 
 499 
 500 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 501 /*
 502  * Update PTEP with ENTRY, which is guaranteed to be a less
 503  * restrictive PTE.  That is, ENTRY may have the ACCESSED, DIRTY, and
 504  * WRITABLE bits turned on, when the value at PTEP did not.  The
 505  * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
 506  *
 507  * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
 508  * having to worry about races.  On SMP machines, there are only two
 509  * cases where this is true:
 510  *
 511  *      (1) *PTEP has the PRESENT bit turned OFF
 512  *      (2) ENTRY has the DIRTY bit turned ON
 513  *
 514  * On ia64, we could implement this routine with a cmpxchg()-loop
 515  * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
 516  * However, like on x86, we can get a more streamlined version by
 517  * observing that it is OK to drop ACCESSED bit updates when
 518  * SAFELY_WRITABLE is FALSE.  Besides being rare, all that would do is
 519  * result in an extra Access-bit fault, which would then turn on the
 520  * ACCESSED bit in the low-level fault handler (iaccess_bit or
 521  * daccess_bit in ivt.S).
 522  */
 523 #ifdef CONFIG_SMP
 524 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
 525 ({                                                                      \
 526         int __changed = !pte_same(*(__ptep), __entry);                  \
 527         if (__changed && __safely_writable) {                           \
 528                 set_pte(__ptep, __entry);                               \
 529                 flush_tlb_page(__vma, __addr);                          \
 530         }                                                               \
 531         __changed;                                                      \
 532 })
 533 #else
 534 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
 535 ({                                                                      \
 536         int __changed = !pte_same(*(__ptep), __entry);                  \
 537         if (__changed) {                                                \
 538                 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry);  \
 539                 flush_tlb_page(__vma, __addr);                          \
 540         }                                                               \
 541         __changed;                                                      \
 542 })
 543 #endif
 544 
 545 #  ifdef CONFIG_VIRTUAL_MEM_MAP
 546   /* arch mem_map init routine is needed due to holes in a virtual mem_map */
 547     extern void memmap_init (unsigned long size, int nid, unsigned long zone,
 548                              unsigned long start_pfn);
 549 #  endif /* CONFIG_VIRTUAL_MEM_MAP */
 550 # endif /* !__ASSEMBLY__ */
 551 
 552 /*
 553  * Identity-mapped regions use a large page size.  We'll call such large pages
 554  * "granules".  If you can think of a better name that's unambiguous, let me
 555  * know...
 556  */
 557 #if defined(CONFIG_IA64_GRANULE_64MB)
 558 # define IA64_GRANULE_SHIFT     _PAGE_SIZE_64M
 559 #elif defined(CONFIG_IA64_GRANULE_16MB)
 560 # define IA64_GRANULE_SHIFT     _PAGE_SIZE_16M
 561 #endif
 562 #define IA64_GRANULE_SIZE       (1 << IA64_GRANULE_SHIFT)
 563 /*
 564  * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
 565  */
 566 #define KERNEL_TR_PAGE_SHIFT    _PAGE_SIZE_64M
 567 #define KERNEL_TR_PAGE_SIZE     (1 << KERNEL_TR_PAGE_SHIFT)
 568 
 569 /* These tell get_user_pages() that the first gate page is accessible from user-level.  */
 570 #define FIXADDR_USER_START      GATE_ADDR
 571 #ifdef HAVE_BUGGY_SEGREL
 572 # define FIXADDR_USER_END       (GATE_ADDR + 2*PAGE_SIZE)
 573 #else
 574 # define FIXADDR_USER_END       (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
 575 #endif
 576 
 577 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 578 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 579 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 580 #define __HAVE_ARCH_PTE_SAME
 581 #define __HAVE_ARCH_PGD_OFFSET_GATE
 582 
 583 
 584 #if CONFIG_PGTABLE_LEVELS == 3
 585 #define __ARCH_USE_5LEVEL_HACK
 586 #include <asm-generic/pgtable-nopud.h>
 587 #endif
 588 #include <asm-generic/5level-fixup.h>
 589 #include <asm-generic/pgtable.h>
 590 
 591 #endif /* _ASM_IA64_PGTABLE_H */
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root/arch/ia64/include/asm/pgtable.h

INCLUDED FROM

DEFINITIONS
