root/drivers/misc/mic/host/mic_x100.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Intel MIC Platform Software Stack (MPSS)
   4  *
   5  * Copyright(c) 2013 Intel Corporation.
   6  *
   7  * Intel MIC Host driver.
   8  */
   9 #ifndef _MIC_X100_HW_H_
  10 #define _MIC_X100_HW_H_
  11 
  12 #define MIC_X100_PCI_DEVICE_2250 0x2250
  13 #define MIC_X100_PCI_DEVICE_2251 0x2251
  14 #define MIC_X100_PCI_DEVICE_2252 0x2252
  15 #define MIC_X100_PCI_DEVICE_2253 0x2253
  16 #define MIC_X100_PCI_DEVICE_2254 0x2254
  17 #define MIC_X100_PCI_DEVICE_2255 0x2255
  18 #define MIC_X100_PCI_DEVICE_2256 0x2256
  19 #define MIC_X100_PCI_DEVICE_2257 0x2257
  20 #define MIC_X100_PCI_DEVICE_2258 0x2258
  21 #define MIC_X100_PCI_DEVICE_2259 0x2259
  22 #define MIC_X100_PCI_DEVICE_225a 0x225a
  23 #define MIC_X100_PCI_DEVICE_225b 0x225b
  24 #define MIC_X100_PCI_DEVICE_225c 0x225c
  25 #define MIC_X100_PCI_DEVICE_225d 0x225d
  26 #define MIC_X100_PCI_DEVICE_225e 0x225e
  27 
  28 #define MIC_X100_APER_BAR 0
  29 #define MIC_X100_MMIO_BAR 4
  30 
  31 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000
  32 #define MIC_X100_SBOX_SPAD0 0x0000AB20
  33 #define MIC_X100_SBOX_SICR0_DBR(x) ((x) & 0xf)
  34 #define MIC_X100_SBOX_SICR0_DMA(x) (((x) >> 8) & 0xff)
  35 #define MIC_X100_SBOX_SICE0_DBR(x) ((x) & 0xf)
  36 #define MIC_X100_SBOX_DBR_BITS(x) ((x) & 0xf)
  37 #define MIC_X100_SBOX_SICE0_DMA(x) (((x) >> 8) & 0xff)
  38 #define MIC_X100_SBOX_DMA_BITS(x) (((x) & 0xff) << 8)
  39 
  40 #define MIC_X100_SBOX_APICICR0 0x0000A9D0
  41 #define MIC_X100_SBOX_SICR0 0x00009004
  42 #define MIC_X100_SBOX_SICE0 0x0000900C
  43 #define MIC_X100_SBOX_SICC0 0x00009010
  44 #define MIC_X100_SBOX_SIAC0 0x00009014
  45 #define MIC_X100_SBOX_MSIXPBACR 0x00009084
  46 #define MIC_X100_SBOX_MXAR0 0x00009044
  47 #define MIC_X100_SBOX_SMPT00 0x00003100
  48 #define MIC_X100_SBOX_RDMASR0 0x0000B180
  49 
  50 #define MIC_X100_DOORBELL_IDX_START 0
  51 #define MIC_X100_NUM_DOORBELL 4
  52 #define MIC_X100_DMA_IDX_START 8
  53 #define MIC_X100_NUM_DMA 8
  54 #define MIC_X100_ERR_IDX_START 30
  55 #define MIC_X100_NUM_ERR 1
  56 
  57 #define MIC_X100_NUM_SBOX_IRQ 8
  58 #define MIC_X100_NUM_RDMASR_IRQ 8
  59 #define MIC_X100_RDMASR_IRQ_BASE 17
  60 #define MIC_X100_SPAD2_DOWNLOAD_STATUS(x) ((x) & 0x1)
  61 #define MIC_X100_SPAD2_APIC_ID(x)       (((x) >> 1) & 0x1ff)
  62 #define MIC_X100_SPAD2_DOWNLOAD_ADDR(x) ((x) & 0xfffff000)
  63 #define MIC_X100_SBOX_APICICR7 0x0000AA08
  64 #define MIC_X100_SBOX_RGCR 0x00004010
  65 #define MIC_X100_SBOX_SDBIC0 0x0000CC90
  66 #define MIC_X100_DOWNLOAD_INFO 2
  67 #define MIC_X100_FW_SIZE 5
  68 #define MIC_X100_POSTCODE 0x242c
  69 
  70 static const u16 mic_x100_intr_init[] = {
  71                 MIC_X100_DOORBELL_IDX_START,
  72                 MIC_X100_DMA_IDX_START,
  73                 MIC_X100_ERR_IDX_START,
  74                 MIC_X100_NUM_DOORBELL,
  75                 MIC_X100_NUM_DMA,
  76                 MIC_X100_NUM_ERR,
  77 };
  78 
  79 /* Host->Card(bootstrap) Interrupt Vector */
  80 #define MIC_X100_BSP_INTERRUPT_VECTOR 229
  81 
  82 extern struct mic_hw_ops mic_x100_ops;
  83 extern struct mic_smpt_ops mic_x100_smpt_ops;
  84 extern struct mic_hw_intr_ops mic_x100_intr_ops;
  85 
  86 #endif