1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2012-2018, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7 #ifndef _MEI_INTERFACE_H_
8 #define _MEI_INTERFACE_H_
9
10 #include <linux/irqreturn.h>
11 #include <linux/pci.h>
12 #include <linux/mei.h>
13
14 #include "mei_dev.h"
15 #include "client.h"
16
17 /*
18 * mei_cfg - mei device configuration
19 *
20 * @fw_status: FW status
21 * @quirk_probe: device exclusion quirk
22 * @dma_size: device DMA buffers size
23 * @fw_ver_supported: is fw version retrievable from FW
24 */
25 struct mei_cfg {
26 const struct mei_fw_status fw_status;
27 bool (*quirk_probe)(struct pci_dev *pdev);
28 size_t dma_size[DMA_DSCR_NUM];
29 u32 fw_ver_supported:1;
30 };
31
32
33 #define MEI_PCI_DEVICE(dev, cfg) \
34 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
35 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
36 .driver_data = (kernel_ulong_t)(cfg),
37
38 #define MEI_ME_RPM_TIMEOUT 500 /* ms */
39
40 /**
41 * struct mei_me_hw - me hw specific data
42 *
43 * @cfg: per device generation config and ops
44 * @mem_addr: io memory address
45 * @pg_state: power gating state
46 * @d0i3_supported: di03 support
47 * @hbuf_depth: depth of hardware host/write buffer in slots
48 */
49 struct mei_me_hw {
50 const struct mei_cfg *cfg;
51 void __iomem *mem_addr;
52 enum mei_pg_state pg_state;
53 bool d0i3_supported;
54 u8 hbuf_depth;
55 };
56
57 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
58
59 /**
60 * enum mei_cfg_idx - indices to platform specific configurations.
61 *
62 * Note: has to be synchronized with mei_cfg_list[]
63 *
64 * @MEI_ME_UNDEF_CFG: Lower sentinel.
65 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices.
66 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10
67 * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6).
68 * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7).
69 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
70 * with quirk for Node Manager exclusion.
71 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
72 * client platforms.
73 * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer
74 * servers platforms with quirk for
75 * SPS firmware exclusion.
76 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
77 * @MEI_ME_NUM_CFG: Upper Sentinel.
78 */
79 enum mei_cfg_idx {
80 MEI_ME_UNDEF_CFG,
81 MEI_ME_ICH_CFG,
82 MEI_ME_ICH10_CFG,
83 MEI_ME_PCH6_CFG,
84 MEI_ME_PCH7_CFG,
85 MEI_ME_PCH_CPT_PBG_CFG,
86 MEI_ME_PCH8_CFG,
87 MEI_ME_PCH8_SPS_CFG,
88 MEI_ME_PCH12_CFG,
89 MEI_ME_NUM_CFG,
90 };
91
92 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
93
94 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
95 const struct mei_cfg *cfg);
96
97 int mei_me_pg_enter_sync(struct mei_device *dev);
98 int mei_me_pg_exit_sync(struct mei_device *dev);
99
100 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
101 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
102
103 #endif /* _MEI_INTERFACE_H_ */