1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2019 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8 #ifndef HABANALABSP_H_
9 #define HABANALABSP_H_
10
11 #include "include/armcp_if.h"
12 #include "include/qman_if.h"
13
14 #include <linux/cdev.h>
15 #include <linux/iopoll.h>
16 #include <linux/irqreturn.h>
17 #include <linux/dma-fence.h>
18 #include <linux/dma-direction.h>
19 #include <linux/scatterlist.h>
20 #include <linux/hashtable.h>
21
22 #define HL_NAME "habanalabs"
23
24 #define HL_MMAP_CB_MASK (0x8000000000000000ull >> PAGE_SHIFT)
25
26 #define HL_PENDING_RESET_PER_SEC 5
27
28 #define HL_DEVICE_TIMEOUT_USEC 1000000 /* 1 s */
29
30 #define HL_HEARTBEAT_PER_USEC 5000000 /* 5 s */
31
32 #define HL_PLL_LOW_JOB_FREQ_USEC 5000000 /* 5 s */
33
34 #define HL_ARMCP_INFO_TIMEOUT_USEC 10000000 /* 10s */
35 #define HL_ARMCP_EEPROM_TIMEOUT_USEC 10000000 /* 10s */
36
37 #define HL_PCI_ELBI_TIMEOUT_MSEC 10 /* 10ms */
38
39 #define HL_SIM_MAX_TIMEOUT_US 10000000 /* 10s */
40
41 #define HL_MAX_QUEUES 128
42
43 #define HL_MAX_JOBS_PER_CS 64
44
45 /* MUST BE POWER OF 2 and larger than 1 */
46 #define HL_MAX_PENDING_CS 64
47
48 #define HL_IDLE_BUSY_TS_ARR_SIZE 4096
49
50 /* Memory */
51 #define MEM_HASH_TABLE_BITS 7 /* 1 << 7 buckets */
52
53 /* MMU */
54 #define MMU_HASH_TABLE_BITS 7 /* 1 << 7 buckets */
55
56 /**
57 * struct pgt_info - MMU hop page info.
58 * @node: hash linked-list node for the pgts shadow hash of pgts.
59 * @phys_addr: physical address of the pgt.
60 * @shadow_addr: shadow hop in the host.
61 * @ctx: pointer to the owner ctx.
62 * @num_of_ptes: indicates how many ptes are used in the pgt.
63 *
64 * The MMU page tables hierarchy is placed on the DRAM. When a new level (hop)
65 * is needed during mapping, a new page is allocated and this structure holds
66 * its essential information. During unmapping, if no valid PTEs remained in the
67 * page, it is freed with its pgt_info structure.
68 */
69 struct pgt_info {
70 struct hlist_node node;
71 u64 phys_addr;
72 u64 shadow_addr;
73 struct hl_ctx *ctx;
74 int num_of_ptes;
75 };
76
77 struct hl_device;
78 struct hl_fpriv;
79
80 /**
81 * enum hl_queue_type - Supported QUEUE types.
82 * @QUEUE_TYPE_NA: queue is not available.
83 * @QUEUE_TYPE_EXT: external queue which is a DMA channel that may access the
84 * host.
85 * @QUEUE_TYPE_INT: internal queue that performs DMA inside the device's
86 * memories and/or operates the compute engines.
87 * @QUEUE_TYPE_CPU: S/W queue for communication with the device's CPU.
88 */
89 enum hl_queue_type {
90 QUEUE_TYPE_NA,
91 QUEUE_TYPE_EXT,
92 QUEUE_TYPE_INT,
93 QUEUE_TYPE_CPU
94 };
95
96 /**
97 * struct hw_queue_properties - queue information.
98 * @type: queue type.
99 * @driver_only: true if only the driver is allowed to send a job to this queue,
100 * false otherwise.
101 */
102 struct hw_queue_properties {
103 enum hl_queue_type type;
104 u8 driver_only;
105 };
106
107 /**
108 * enum vm_type_t - virtual memory mapping request information.
109 * @VM_TYPE_USERPTR: mapping of user memory to device virtual address.
110 * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address.
111 */
112 enum vm_type_t {
113 VM_TYPE_USERPTR,
114 VM_TYPE_PHYS_PACK
115 };
116
117 /**
118 * enum hl_device_hw_state - H/W device state. use this to understand whether
119 * to do reset before hw_init or not
120 * @HL_DEVICE_HW_STATE_CLEAN: H/W state is clean. i.e. after hard reset
121 * @HL_DEVICE_HW_STATE_DIRTY: H/W state is dirty. i.e. we started to execute
122 * hw_init
123 */
124 enum hl_device_hw_state {
125 HL_DEVICE_HW_STATE_CLEAN = 0,
126 HL_DEVICE_HW_STATE_DIRTY
127 };
128
129 /**
130 * struct asic_fixed_properties - ASIC specific immutable properties.
131 * @hw_queues_props: H/W queues properties.
132 * @armcp_info: received various information from ArmCP regarding the H/W, e.g.
133 * available sensors.
134 * @uboot_ver: F/W U-boot version.
135 * @preboot_ver: F/W Preboot version.
136 * @sram_base_address: SRAM physical start address.
137 * @sram_end_address: SRAM physical end address.
138 * @sram_user_base_address - SRAM physical start address for user access.
139 * @dram_base_address: DRAM physical start address.
140 * @dram_end_address: DRAM physical end address.
141 * @dram_user_base_address: DRAM physical start address for user access.
142 * @dram_size: DRAM total size.
143 * @dram_pci_bar_size: size of PCI bar towards DRAM.
144 * @max_power_default: max power of the device after reset
145 * @va_space_host_start_address: base address of virtual memory range for
146 * mapping host memory.
147 * @va_space_host_end_address: end address of virtual memory range for
148 * mapping host memory.
149 * @va_space_dram_start_address: base address of virtual memory range for
150 * mapping DRAM memory.
151 * @va_space_dram_end_address: end address of virtual memory range for
152 * mapping DRAM memory.
153 * @dram_size_for_default_page_mapping: DRAM size needed to map to avoid page
154 * fault.
155 * @pcie_dbi_base_address: Base address of the PCIE_DBI block.
156 * @pcie_aux_dbi_reg_addr: Address of the PCIE_AUX DBI register.
157 * @mmu_pgt_addr: base physical address in DRAM of MMU page tables.
158 * @mmu_dram_default_page_addr: DRAM default page physical address.
159 * @mmu_pgt_size: MMU page tables total size.
160 * @mmu_pte_size: PTE size in MMU page tables.
161 * @mmu_hop_table_size: MMU hop table size.
162 * @mmu_hop0_tables_total_size: total size of MMU hop0 tables.
163 * @dram_page_size: page size for MMU DRAM allocation.
164 * @cfg_size: configuration space size on SRAM.
165 * @sram_size: total size of SRAM.
166 * @max_asid: maximum number of open contexts (ASIDs).
167 * @num_of_events: number of possible internal H/W IRQs.
168 * @psoc_pci_pll_nr: PCI PLL NR value.
169 * @psoc_pci_pll_nf: PCI PLL NF value.
170 * @psoc_pci_pll_od: PCI PLL OD value.
171 * @psoc_pci_pll_div_factor: PCI PLL DIV FACTOR 1 value.
172 * @completion_queues_count: number of completion queues.
173 * @high_pll: high PLL frequency used by the device.
174 * @cb_pool_cb_cnt: number of CBs in the CB pool.
175 * @cb_pool_cb_size: size of each CB in the CB pool.
176 * @tpc_enabled_mask: which TPCs are enabled.
177 */
178 struct asic_fixed_properties {
179 struct hw_queue_properties hw_queues_props[HL_MAX_QUEUES];
180 struct armcp_info armcp_info;
181 char uboot_ver[VERSION_MAX_LEN];
182 char preboot_ver[VERSION_MAX_LEN];
183 u64 sram_base_address;
184 u64 sram_end_address;
185 u64 sram_user_base_address;
186 u64 dram_base_address;
187 u64 dram_end_address;
188 u64 dram_user_base_address;
189 u64 dram_size;
190 u64 dram_pci_bar_size;
191 u64 max_power_default;
192 u64 va_space_host_start_address;
193 u64 va_space_host_end_address;
194 u64 va_space_dram_start_address;
195 u64 va_space_dram_end_address;
196 u64 dram_size_for_default_page_mapping;
197 u64 pcie_dbi_base_address;
198 u64 pcie_aux_dbi_reg_addr;
199 u64 mmu_pgt_addr;
200 u64 mmu_dram_default_page_addr;
201 u32 mmu_pgt_size;
202 u32 mmu_pte_size;
203 u32 mmu_hop_table_size;
204 u32 mmu_hop0_tables_total_size;
205 u32 dram_page_size;
206 u32 cfg_size;
207 u32 sram_size;
208 u32 max_asid;
209 u32 num_of_events;
210 u32 psoc_pci_pll_nr;
211 u32 psoc_pci_pll_nf;
212 u32 psoc_pci_pll_od;
213 u32 psoc_pci_pll_div_factor;
214 u32 high_pll;
215 u32 cb_pool_cb_cnt;
216 u32 cb_pool_cb_size;
217 u8 completion_queues_count;
218 u8 tpc_enabled_mask;
219 };
220
221 /**
222 * struct hl_dma_fence - wrapper for fence object used by command submissions.
223 * @base_fence: kernel fence object.
224 * @lock: spinlock to protect fence.
225 * @hdev: habanalabs device structure.
226 * @cs_seq: command submission sequence number.
227 */
228 struct hl_dma_fence {
229 struct dma_fence base_fence;
230 spinlock_t lock;
231 struct hl_device *hdev;
232 u64 cs_seq;
233 };
234
235 /*
236 * Command Buffers
237 */
238
239 #define HL_MAX_CB_SIZE 0x200000 /* 2MB */
240
241 /**
242 * struct hl_cb_mgr - describes a Command Buffer Manager.
243 * @cb_lock: protects cb_handles.
244 * @cb_handles: an idr to hold all command buffer handles.
245 */
246 struct hl_cb_mgr {
247 spinlock_t cb_lock;
248 struct idr cb_handles; /* protected by cb_lock */
249 };
250
251 /**
252 * struct hl_cb - describes a Command Buffer.
253 * @refcount: reference counter for usage of the CB.
254 * @hdev: pointer to device this CB belongs to.
255 * @lock: spinlock to protect mmap/cs flows.
256 * @debugfs_list: node in debugfs list of command buffers.
257 * @pool_list: node in pool list of command buffers.
258 * @kernel_address: Holds the CB's kernel virtual address.
259 * @bus_address: Holds the CB's DMA address.
260 * @mmap_size: Holds the CB's size that was mmaped.
261 * @size: holds the CB's size.
262 * @id: the CB's ID.
263 * @cs_cnt: holds number of CS that this CB participates in.
264 * @ctx_id: holds the ID of the owner's context.
265 * @mmap: true if the CB is currently mmaped to user.
266 * @is_pool: true if CB was acquired from the pool, false otherwise.
267 */
268 struct hl_cb {
269 struct kref refcount;
270 struct hl_device *hdev;
271 spinlock_t lock;
272 struct list_head debugfs_list;
273 struct list_head pool_list;
274 u64 kernel_address;
275 dma_addr_t bus_address;
276 u32 mmap_size;
277 u32 size;
278 u32 id;
279 u32 cs_cnt;
280 u32 ctx_id;
281 u8 mmap;
282 u8 is_pool;
283 };
284
285
286 /*
287 * QUEUES
288 */
289
290 struct hl_cs_job;
291
292 /*
293 * Currently, there are two limitations on the maximum length of a queue:
294 *
295 * 1. The memory footprint of the queue. The current allocated space for the
296 * queue is PAGE_SIZE. Because each entry in the queue is HL_BD_SIZE,
297 * the maximum length of the queue can be PAGE_SIZE / HL_BD_SIZE,
298 * which currently is 4096/16 = 256 entries.
299 *
300 * To increase that, we need either to decrease the size of the
301 * BD (difficult), or allocate more than a single page (easier).
302 *
303 * 2. Because the size of the JOB handle field in the BD CTL / completion queue
304 * is 10-bit, we can have up to 1024 open jobs per hardware queue.
305 * Therefore, each queue can hold up to 1024 entries.
306 *
307 * HL_QUEUE_LENGTH is in units of struct hl_bd.
308 * HL_QUEUE_LENGTH * sizeof(struct hl_bd) should be <= HL_PAGE_SIZE
309 */
310
311 #define HL_PAGE_SIZE 4096 /* minimum page size */
312 /* Must be power of 2 (HL_PAGE_SIZE / HL_BD_SIZE) */
313 #define HL_QUEUE_LENGTH 256
314 #define HL_QUEUE_SIZE_IN_BYTES (HL_QUEUE_LENGTH * HL_BD_SIZE)
315
316 /*
317 * HL_CQ_LENGTH is in units of struct hl_cq_entry.
318 * HL_CQ_LENGTH should be <= HL_PAGE_SIZE
319 */
320 #define HL_CQ_LENGTH HL_QUEUE_LENGTH
321 #define HL_CQ_SIZE_IN_BYTES (HL_CQ_LENGTH * HL_CQ_ENTRY_SIZE)
322
323 /* Must be power of 2 (HL_PAGE_SIZE / HL_EQ_ENTRY_SIZE) */
324 #define HL_EQ_LENGTH 64
325 #define HL_EQ_SIZE_IN_BYTES (HL_EQ_LENGTH * HL_EQ_ENTRY_SIZE)
326
327 /* Host <-> ArmCP shared memory size */
328 #define HL_CPU_ACCESSIBLE_MEM_SIZE SZ_2M
329
330 /**
331 * struct hl_hw_queue - describes a H/W transport queue.
332 * @shadow_queue: pointer to a shadow queue that holds pointers to jobs.
333 * @queue_type: type of queue.
334 * @kernel_address: holds the queue's kernel virtual address.
335 * @bus_address: holds the queue's DMA address.
336 * @pi: holds the queue's pi value.
337 * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci).
338 * @hw_queue_id: the id of the H/W queue.
339 * @int_queue_len: length of internal queue (number of entries).
340 * @valid: is the queue valid (we have array of 32 queues, not all of them
341 * exists).
342 */
343 struct hl_hw_queue {
344 struct hl_cs_job **shadow_queue;
345 enum hl_queue_type queue_type;
346 u64 kernel_address;
347 dma_addr_t bus_address;
348 u32 pi;
349 u32 ci;
350 u32 hw_queue_id;
351 u16 int_queue_len;
352 u8 valid;
353 };
354
355 /**
356 * struct hl_cq - describes a completion queue
357 * @hdev: pointer to the device structure
358 * @kernel_address: holds the queue's kernel virtual address
359 * @bus_address: holds the queue's DMA address
360 * @hw_queue_id: the id of the matching H/W queue
361 * @ci: ci inside the queue
362 * @pi: pi inside the queue
363 * @free_slots_cnt: counter of free slots in queue
364 */
365 struct hl_cq {
366 struct hl_device *hdev;
367 u64 kernel_address;
368 dma_addr_t bus_address;
369 u32 hw_queue_id;
370 u32 ci;
371 u32 pi;
372 atomic_t free_slots_cnt;
373 };
374
375 /**
376 * struct hl_eq - describes the event queue (single one per device)
377 * @hdev: pointer to the device structure
378 * @kernel_address: holds the queue's kernel virtual address
379 * @bus_address: holds the queue's DMA address
380 * @ci: ci inside the queue
381 */
382 struct hl_eq {
383 struct hl_device *hdev;
384 u64 kernel_address;
385 dma_addr_t bus_address;
386 u32 ci;
387 };
388
389
390 /*
391 * ASICs
392 */
393
394 /**
395 * enum hl_asic_type - supported ASIC types.
396 * @ASIC_INVALID: Invalid ASIC type.
397 * @ASIC_GOYA: Goya device.
398 */
399 enum hl_asic_type {
400 ASIC_INVALID,
401 ASIC_GOYA
402 };
403
404 struct hl_cs_parser;
405
406 /**
407 * enum hl_pm_mng_profile - power management profile.
408 * @PM_AUTO: internal clock is set by the Linux driver.
409 * @PM_MANUAL: internal clock is set by the user.
410 * @PM_LAST: last power management type.
411 */
412 enum hl_pm_mng_profile {
413 PM_AUTO = 1,
414 PM_MANUAL,
415 PM_LAST
416 };
417
418 /**
419 * enum hl_pll_frequency - PLL frequency.
420 * @PLL_HIGH: high frequency.
421 * @PLL_LOW: low frequency.
422 * @PLL_LAST: last frequency values that were configured by the user.
423 */
424 enum hl_pll_frequency {
425 PLL_HIGH = 1,
426 PLL_LOW,
427 PLL_LAST
428 };
429
430 /**
431 * struct hl_asic_funcs - ASIC specific functions that are can be called from
432 * common code.
433 * @early_init: sets up early driver state (pre sw_init), doesn't configure H/W.
434 * @early_fini: tears down what was done in early_init.
435 * @late_init: sets up late driver/hw state (post hw_init) - Optional.
436 * @late_fini: tears down what was done in late_init (pre hw_fini) - Optional.
437 * @sw_init: sets up driver state, does not configure H/W.
438 * @sw_fini: tears down driver state, does not configure H/W.
439 * @hw_init: sets up the H/W state.
440 * @hw_fini: tears down the H/W state.
441 * @halt_engines: halt engines, needed for reset sequence. This also disables
442 * interrupts from the device. Should be called before
443 * hw_fini and before CS rollback.
444 * @suspend: handles IP specific H/W or SW changes for suspend.
445 * @resume: handles IP specific H/W or SW changes for resume.
446 * @cb_mmap: maps a CB.
447 * @ring_doorbell: increment PI on a given QMAN.
448 * @pqe_write: Write the PQ entry to the PQ. This is ASIC-specific
449 * function because the PQs are located in different memory areas
450 * per ASIC (SRAM, DRAM, Host memory) and therefore, the method of
451 * writing the PQE must match the destination memory area
452 * properties.
453 * @asic_dma_alloc_coherent: Allocate coherent DMA memory by calling
454 * dma_alloc_coherent(). This is ASIC function because
455 * its implementation is not trivial when the driver
456 * is loaded in simulation mode (not upstreamed).
457 * @asic_dma_free_coherent: Free coherent DMA memory by calling
458 * dma_free_coherent(). This is ASIC function because
459 * its implementation is not trivial when the driver
460 * is loaded in simulation mode (not upstreamed).
461 * @get_int_queue_base: get the internal queue base address.
462 * @test_queues: run simple test on all queues for sanity check.
463 * @asic_dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool.
464 * size of allocation is HL_DMA_POOL_BLK_SIZE.
465 * @asic_dma_pool_free: free small DMA allocation from pool.
466 * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool.
467 * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool.
468 * @hl_dma_unmap_sg: DMA unmap scatter-gather list.
469 * @cs_parser: parse Command Submission.
470 * @asic_dma_map_sg: DMA map scatter-gather list.
471 * @get_dma_desc_list_size: get number of LIN_DMA packets required for CB.
472 * @add_end_of_cb_packets: Add packets to the end of CB, if device requires it.
473 * @update_eq_ci: update event queue CI.
474 * @context_switch: called upon ASID context switch.
475 * @restore_phase_topology: clear all SOBs amd MONs.
476 * @debugfs_read32: debug interface for reading u32 from DRAM/SRAM.
477 * @debugfs_write32: debug interface for writing u32 to DRAM/SRAM.
478 * @add_device_attr: add ASIC specific device attributes.
479 * @handle_eqe: handle event queue entry (IRQ) from ArmCP.
480 * @set_pll_profile: change PLL profile (manual/automatic).
481 * @get_events_stat: retrieve event queue entries histogram.
482 * @read_pte: read MMU page table entry from DRAM.
483 * @write_pte: write MMU page table entry to DRAM.
484 * @mmu_invalidate_cache: flush MMU STLB cache, either with soft (L1 only) or
485 * hard (L0 & L1) flush.
486 * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
487 * ASID-VA-size mask.
488 * @send_heartbeat: send is-alive packet to ArmCP and verify response.
489 * @debug_coresight: perform certain actions on Coresight for debugging.
490 * @is_device_idle: return true if device is idle, false otherwise.
491 * @soft_reset_late_init: perform certain actions needed after soft reset.
492 * @hw_queues_lock: acquire H/W queues lock.
493 * @hw_queues_unlock: release H/W queues lock.
494 * @get_pci_id: retrieve PCI ID.
495 * @get_eeprom_data: retrieve EEPROM data from F/W.
496 * @send_cpu_message: send buffer to ArmCP.
497 * @get_hw_state: retrieve the H/W state
498 * @pci_bars_map: Map PCI BARs.
499 * @set_dram_bar_base: Set DRAM BAR to map specific device address. Returns
500 * old address the bar pointed to or U64_MAX for failure
501 * @init_iatu: Initialize the iATU unit inside the PCI controller.
502 * @rreg: Read a register. Needed for simulator support.
503 * @wreg: Write a register. Needed for simulator support.
504 * @halt_coresight: stop the ETF and ETR traces.
505 */
506 struct hl_asic_funcs {
507 int (*early_init)(struct hl_device *hdev);
508 int (*early_fini)(struct hl_device *hdev);
509 int (*late_init)(struct hl_device *hdev);
510 void (*late_fini)(struct hl_device *hdev);
511 int (*sw_init)(struct hl_device *hdev);
512 int (*sw_fini)(struct hl_device *hdev);
513 int (*hw_init)(struct hl_device *hdev);
514 void (*hw_fini)(struct hl_device *hdev, bool hard_reset);
515 void (*halt_engines)(struct hl_device *hdev, bool hard_reset);
516 int (*suspend)(struct hl_device *hdev);
517 int (*resume)(struct hl_device *hdev);
518 int (*cb_mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
519 u64 kaddress, phys_addr_t paddress, u32 size);
520 void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
521 void (*pqe_write)(struct hl_device *hdev, __le64 *pqe,
522 struct hl_bd *bd);
523 void* (*asic_dma_alloc_coherent)(struct hl_device *hdev, size_t size,
524 dma_addr_t *dma_handle, gfp_t flag);
525 void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size,
526 void *cpu_addr, dma_addr_t dma_handle);
527 void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id,
528 dma_addr_t *dma_handle, u16 *queue_len);
529 int (*test_queues)(struct hl_device *hdev);
530 void* (*asic_dma_pool_zalloc)(struct hl_device *hdev, size_t size,
531 gfp_t mem_flags, dma_addr_t *dma_handle);
532 void (*asic_dma_pool_free)(struct hl_device *hdev, void *vaddr,
533 dma_addr_t dma_addr);
534 void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev,
535 size_t size, dma_addr_t *dma_handle);
536 void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev,
537 size_t size, void *vaddr);
538 void (*hl_dma_unmap_sg)(struct hl_device *hdev,
539 struct scatterlist *sgl, int nents,
540 enum dma_data_direction dir);
541 int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser);
542 int (*asic_dma_map_sg)(struct hl_device *hdev,
543 struct scatterlist *sgl, int nents,
544 enum dma_data_direction dir);
545 u32 (*get_dma_desc_list_size)(struct hl_device *hdev,
546 struct sg_table *sgt);
547 void (*add_end_of_cb_packets)(struct hl_device *hdev,
548 u64 kernel_address, u32 len,
549 u64 cq_addr, u32 cq_val, u32 msix_num);
550 void (*update_eq_ci)(struct hl_device *hdev, u32 val);
551 int (*context_switch)(struct hl_device *hdev, u32 asid);
552 void (*restore_phase_topology)(struct hl_device *hdev);
553 int (*debugfs_read32)(struct hl_device *hdev, u64 addr, u32 *val);
554 int (*debugfs_write32)(struct hl_device *hdev, u64 addr, u32 val);
555 void (*add_device_attr)(struct hl_device *hdev,
556 struct attribute_group *dev_attr_grp);
557 void (*handle_eqe)(struct hl_device *hdev,
558 struct hl_eq_entry *eq_entry);
559 void (*set_pll_profile)(struct hl_device *hdev,
560 enum hl_pll_frequency freq);
561 void* (*get_events_stat)(struct hl_device *hdev, bool aggregate,
562 u32 *size);
563 u64 (*read_pte)(struct hl_device *hdev, u64 addr);
564 void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val);
565 void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard);
566 void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
567 u32 asid, u64 va, u64 size);
568 int (*send_heartbeat)(struct hl_device *hdev);
569 int (*debug_coresight)(struct hl_device *hdev, void *data);
570 bool (*is_device_idle)(struct hl_device *hdev, u32 *mask,
571 struct seq_file *s);
572 int (*soft_reset_late_init)(struct hl_device *hdev);
573 void (*hw_queues_lock)(struct hl_device *hdev);
574 void (*hw_queues_unlock)(struct hl_device *hdev);
575 u32 (*get_pci_id)(struct hl_device *hdev);
576 int (*get_eeprom_data)(struct hl_device *hdev, void *data,
577 size_t max_size);
578 int (*send_cpu_message)(struct hl_device *hdev, u32 *msg,
579 u16 len, u32 timeout, long *result);
580 enum hl_device_hw_state (*get_hw_state)(struct hl_device *hdev);
581 int (*pci_bars_map)(struct hl_device *hdev);
582 u64 (*set_dram_bar_base)(struct hl_device *hdev, u64 addr);
583 int (*init_iatu)(struct hl_device *hdev);
584 u32 (*rreg)(struct hl_device *hdev, u32 reg);
585 void (*wreg)(struct hl_device *hdev, u32 reg, u32 val);
586 void (*halt_coresight)(struct hl_device *hdev);
587 };
588
589
590 /*
591 * CONTEXTS
592 */
593
594 #define HL_KERNEL_ASID_ID 0
595
596 /**
597 * struct hl_va_range - virtual addresses range.
598 * @lock: protects the virtual addresses list.
599 * @list: list of virtual addresses blocks available for mappings.
600 * @start_addr: range start address.
601 * @end_addr: range end address.
602 */
603 struct hl_va_range {
604 struct mutex lock;
605 struct list_head list;
606 u64 start_addr;
607 u64 end_addr;
608 };
609
610 /**
611 * struct hl_ctx - user/kernel context.
612 * @mem_hash: holds mapping from virtual address to virtual memory area
613 * descriptor (hl_vm_phys_pg_list or hl_userptr).
614 * @mmu_phys_hash: holds a mapping from physical address to pgt_info structure.
615 * @mmu_shadow_hash: holds a mapping from shadow address to pgt_info structure.
616 * @hpriv: pointer to the private (Kernel Driver) data of the process (fd).
617 * @hdev: pointer to the device structure.
618 * @refcount: reference counter for the context. Context is released only when
619 * this hits 0l. It is incremented on CS and CS_WAIT.
620 * @cs_pending: array of DMA fence objects representing pending CS.
621 * @host_va_range: holds available virtual addresses for host mappings.
622 * @dram_va_range: holds available virtual addresses for DRAM mappings.
623 * @mem_hash_lock: protects the mem_hash.
624 * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifing the
625 * MMU hash or walking the PGT requires talking this lock
626 * @debugfs_list: node in debugfs list of contexts.
627 * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed
628 * to user so user could inquire about CS. It is used as
629 * index to cs_pending array.
630 * @dram_default_hops: array that holds all hops addresses needed for default
631 * DRAM mapping.
632 * @cs_lock: spinlock to protect cs_sequence.
633 * @dram_phys_mem: amount of used physical DRAM memory by this context.
634 * @thread_ctx_switch_token: token to prevent multiple threads of the same
635 * context from running the context switch phase.
636 * Only a single thread should run it.
637 * @thread_ctx_switch_wait_token: token to prevent the threads that didn't run
638 * the context switch phase from moving to their
639 * execution phase before the context switch phase
640 * has finished.
641 * @asid: context's unique address space ID in the device's MMU.
642 * @handle: context's opaque handle for user
643 */
644 struct hl_ctx {
645 DECLARE_HASHTABLE(mem_hash, MEM_HASH_TABLE_BITS);
646 DECLARE_HASHTABLE(mmu_phys_hash, MMU_HASH_TABLE_BITS);
647 DECLARE_HASHTABLE(mmu_shadow_hash, MMU_HASH_TABLE_BITS);
648 struct hl_fpriv *hpriv;
649 struct hl_device *hdev;
650 struct kref refcount;
651 struct dma_fence *cs_pending[HL_MAX_PENDING_CS];
652 struct hl_va_range host_va_range;
653 struct hl_va_range dram_va_range;
654 struct mutex mem_hash_lock;
655 struct mutex mmu_lock;
656 struct list_head debugfs_list;
657 u64 cs_sequence;
658 u64 *dram_default_hops;
659 spinlock_t cs_lock;
660 atomic64_t dram_phys_mem;
661 atomic_t thread_ctx_switch_token;
662 u32 thread_ctx_switch_wait_token;
663 u32 asid;
664 u32 handle;
665 };
666
667 /**
668 * struct hl_ctx_mgr - for handling multiple contexts.
669 * @ctx_lock: protects ctx_handles.
670 * @ctx_handles: idr to hold all ctx handles.
671 */
672 struct hl_ctx_mgr {
673 struct mutex ctx_lock;
674 struct idr ctx_handles;
675 };
676
677
678
679 /*
680 * COMMAND SUBMISSIONS
681 */
682
683 /**
684 * struct hl_userptr - memory mapping chunk information
685 * @vm_type: type of the VM.
686 * @job_node: linked-list node for hanging the object on the Job's list.
687 * @vec: pointer to the frame vector.
688 * @sgt: pointer to the scatter-gather table that holds the pages.
689 * @dir: for DMA unmapping, the direction must be supplied, so save it.
690 * @debugfs_list: node in debugfs list of command submissions.
691 * @addr: user-space virtual pointer to the start of the memory area.
692 * @size: size of the memory area to pin & map.
693 * @dma_mapped: true if the SG was mapped to DMA addresses, false otherwise.
694 */
695 struct hl_userptr {
696 enum vm_type_t vm_type; /* must be first */
697 struct list_head job_node;
698 struct frame_vector *vec;
699 struct sg_table *sgt;
700 enum dma_data_direction dir;
701 struct list_head debugfs_list;
702 u64 addr;
703 u32 size;
704 u8 dma_mapped;
705 };
706
707 /**
708 * struct hl_cs - command submission.
709 * @jobs_in_queue_cnt: per each queue, maintain counter of submitted jobs.
710 * @ctx: the context this CS belongs to.
711 * @job_list: list of the CS's jobs in the various queues.
712 * @job_lock: spinlock for the CS's jobs list. Needed for free_job.
713 * @refcount: reference counter for usage of the CS.
714 * @fence: pointer to the fence object of this CS.
715 * @work_tdr: delayed work node for TDR.
716 * @mirror_node : node in device mirror list of command submissions.
717 * @debugfs_list: node in debugfs list of command submissions.
718 * @sequence: the sequence number of this CS.
719 * @submitted: true if CS was submitted to H/W.
720 * @completed: true if CS was completed by device.
721 * @timedout : true if CS was timedout.
722 * @tdr_active: true if TDR was activated for this CS (to prevent
723 * double TDR activation).
724 * @aborted: true if CS was aborted due to some device error.
725 */
726 struct hl_cs {
727 u8 jobs_in_queue_cnt[HL_MAX_QUEUES];
728 struct hl_ctx *ctx;
729 struct list_head job_list;
730 spinlock_t job_lock;
731 struct kref refcount;
732 struct dma_fence *fence;
733 struct delayed_work work_tdr;
734 struct list_head mirror_node;
735 struct list_head debugfs_list;
736 u64 sequence;
737 u8 submitted;
738 u8 completed;
739 u8 timedout;
740 u8 tdr_active;
741 u8 aborted;
742 };
743
744 /**
745 * struct hl_cs_job - command submission job.
746 * @cs_node: the node to hang on the CS jobs list.
747 * @cs: the CS this job belongs to.
748 * @user_cb: the CB we got from the user.
749 * @patched_cb: in case of patching, this is internal CB which is submitted on
750 * the queue instead of the CB we got from the IOCTL.
751 * @finish_work: workqueue object to run when job is completed.
752 * @userptr_list: linked-list of userptr mappings that belong to this job and
753 * wait for completion.
754 * @debugfs_list: node in debugfs list of command submission jobs.
755 * @id: the id of this job inside a CS.
756 * @hw_queue_id: the id of the H/W queue this job is submitted to.
757 * @user_cb_size: the actual size of the CB we got from the user.
758 * @job_cb_size: the actual size of the CB that we put on the queue.
759 * @ext_queue: whether the job is for external queue or internal queue.
760 */
761 struct hl_cs_job {
762 struct list_head cs_node;
763 struct hl_cs *cs;
764 struct hl_cb *user_cb;
765 struct hl_cb *patched_cb;
766 struct work_struct finish_work;
767 struct list_head userptr_list;
768 struct list_head debugfs_list;
769 u32 id;
770 u32 hw_queue_id;
771 u32 user_cb_size;
772 u32 job_cb_size;
773 u8 ext_queue;
774 };
775
776 /**
777 * struct hl_cs_parser - command submission paerser properties.
778 * @user_cb: the CB we got from the user.
779 * @patched_cb: in case of patching, this is internal CB which is submitted on
780 * the queue instead of the CB we got from the IOCTL.
781 * @job_userptr_list: linked-list of userptr mappings that belong to the related
782 * job and wait for completion.
783 * @cs_sequence: the sequence number of the related CS.
784 * @ctx_id: the ID of the context the related CS belongs to.
785 * @hw_queue_id: the id of the H/W queue this job is submitted to.
786 * @user_cb_size: the actual size of the CB we got from the user.
787 * @patched_cb_size: the size of the CB after parsing.
788 * @ext_queue: whether the job is for external queue or internal queue.
789 * @job_id: the id of the related job inside the related CS.
790 */
791 struct hl_cs_parser {
792 struct hl_cb *user_cb;
793 struct hl_cb *patched_cb;
794 struct list_head *job_userptr_list;
795 u64 cs_sequence;
796 u32 ctx_id;
797 u32 hw_queue_id;
798 u32 user_cb_size;
799 u32 patched_cb_size;
800 u8 ext_queue;
801 u8 job_id;
802 };
803
804
805 /*
806 * MEMORY STRUCTURE
807 */
808
809 /**
810 * struct hl_vm_hash_node - hash element from virtual address to virtual
811 * memory area descriptor (hl_vm_phys_pg_list or
812 * hl_userptr).
813 * @node: node to hang on the hash table in context object.
814 * @vaddr: key virtual address.
815 * @ptr: value pointer (hl_vm_phys_pg_list or hl_userptr).
816 */
817 struct hl_vm_hash_node {
818 struct hlist_node node;
819 u64 vaddr;
820 void *ptr;
821 };
822
823 /**
824 * struct hl_vm_phys_pg_pack - physical page pack.
825 * @vm_type: describes the type of the virtual area descriptor.
826 * @pages: the physical page array.
827 * @npages: num physical pages in the pack.
828 * @total_size: total size of all the pages in this list.
829 * @mapping_cnt: number of shared mappings.
830 * @asid: the context related to this list.
831 * @page_size: size of each page in the pack.
832 * @flags: HL_MEM_* flags related to this list.
833 * @handle: the provided handle related to this list.
834 * @offset: offset from the first page.
835 * @contiguous: is contiguous physical memory.
836 * @created_from_userptr: is product of host virtual address.
837 */
838 struct hl_vm_phys_pg_pack {
839 enum vm_type_t vm_type; /* must be first */
840 u64 *pages;
841 u64 npages;
842 u64 total_size;
843 atomic_t mapping_cnt;
844 u32 asid;
845 u32 page_size;
846 u32 flags;
847 u32 handle;
848 u32 offset;
849 u8 contiguous;
850 u8 created_from_userptr;
851 };
852
853 /**
854 * struct hl_vm_va_block - virtual range block information.
855 * @node: node to hang on the virtual range list in context object.
856 * @start: virtual range start address.
857 * @end: virtual range end address.
858 * @size: virtual range size.
859 */
860 struct hl_vm_va_block {
861 struct list_head node;
862 u64 start;
863 u64 end;
864 u64 size;
865 };
866
867 /**
868 * struct hl_vm - virtual memory manager for MMU.
869 * @dram_pg_pool: pool for DRAM physical pages of 2MB.
870 * @dram_pg_pool_refcount: reference counter for the pool usage.
871 * @idr_lock: protects the phys_pg_list_handles.
872 * @phys_pg_pack_handles: idr to hold all device allocations handles.
873 * @init_done: whether initialization was done. We need this because VM
874 * initialization might be skipped during device initialization.
875 */
876 struct hl_vm {
877 struct gen_pool *dram_pg_pool;
878 struct kref dram_pg_pool_refcount;
879 spinlock_t idr_lock;
880 struct idr phys_pg_pack_handles;
881 u8 init_done;
882 };
883
884
885 /*
886 * DEBUG, PROFILING STRUCTURE
887 */
888
889 /**
890 * struct hl_debug_params - Coresight debug parameters.
891 * @input: pointer to component specific input parameters.
892 * @output: pointer to component specific output parameters.
893 * @output_size: size of output buffer.
894 * @reg_idx: relevant register ID.
895 * @op: component operation to execute.
896 * @enable: true if to enable component debugging, false otherwise.
897 */
898 struct hl_debug_params {
899 void *input;
900 void *output;
901 u32 output_size;
902 u32 reg_idx;
903 u32 op;
904 bool enable;
905 };
906
907 /*
908 * FILE PRIVATE STRUCTURE
909 */
910
911 /**
912 * struct hl_fpriv - process information stored in FD private data.
913 * @hdev: habanalabs device structure.
914 * @filp: pointer to the given file structure.
915 * @taskpid: current process ID.
916 * @ctx: current executing context. TODO: remove for multiple ctx per process
917 * @ctx_mgr: context manager to handle multiple context for this FD.
918 * @cb_mgr: command buffer manager to handle multiple buffers for this FD.
919 * @debugfs_list: list of relevant ASIC debugfs.
920 * @dev_node: node in the device list of file private data
921 * @refcount: number of related contexts.
922 * @restore_phase_mutex: lock for context switch and restore phase.
923 * @is_control: true for control device, false otherwise
924 */
925 struct hl_fpriv {
926 struct hl_device *hdev;
927 struct file *filp;
928 struct pid *taskpid;
929 struct hl_ctx *ctx;
930 struct hl_ctx_mgr ctx_mgr;
931 struct hl_cb_mgr cb_mgr;
932 struct list_head debugfs_list;
933 struct list_head dev_node;
934 struct kref refcount;
935 struct mutex restore_phase_mutex;
936 u8 is_control;
937 };
938
939
940 /*
941 * DebugFS
942 */
943
944 /**
945 * struct hl_info_list - debugfs file ops.
946 * @name: file name.
947 * @show: function to output information.
948 * @write: function to write to the file.
949 */
950 struct hl_info_list {
951 const char *name;
952 int (*show)(struct seq_file *s, void *data);
953 ssize_t (*write)(struct file *file, const char __user *buf,
954 size_t count, loff_t *f_pos);
955 };
956
957 /**
958 * struct hl_debugfs_entry - debugfs dentry wrapper.
959 * @dent: base debugfs entry structure.
960 * @info_ent: dentry realted ops.
961 * @dev_entry: ASIC specific debugfs manager.
962 */
963 struct hl_debugfs_entry {
964 struct dentry *dent;
965 const struct hl_info_list *info_ent;
966 struct hl_dbg_device_entry *dev_entry;
967 };
968
969 /**
970 * struct hl_dbg_device_entry - ASIC specific debugfs manager.
971 * @root: root dentry.
972 * @hdev: habanalabs device structure.
973 * @entry_arr: array of available hl_debugfs_entry.
974 * @file_list: list of available debugfs files.
975 * @file_mutex: protects file_list.
976 * @cb_list: list of available CBs.
977 * @cb_spinlock: protects cb_list.
978 * @cs_list: list of available CSs.
979 * @cs_spinlock: protects cs_list.
980 * @cs_job_list: list of available CB jobs.
981 * @cs_job_spinlock: protects cs_job_list.
982 * @userptr_list: list of available userptrs (virtual memory chunk descriptor).
983 * @userptr_spinlock: protects userptr_list.
984 * @ctx_mem_hash_list: list of available contexts with MMU mappings.
985 * @ctx_mem_hash_spinlock: protects cb_list.
986 * @addr: next address to read/write from/to in read/write32.
987 * @mmu_addr: next virtual address to translate to physical address in mmu_show.
988 * @mmu_asid: ASID to use while translating in mmu_show.
989 * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read.
990 * @i2c_bus: generic u8 debugfs file for address value to use in i2c_data_read.
991 * @i2c_bus: generic u8 debugfs file for register value to use in i2c_data_read.
992 */
993 struct hl_dbg_device_entry {
994 struct dentry *root;
995 struct hl_device *hdev;
996 struct hl_debugfs_entry *entry_arr;
997 struct list_head file_list;
998 struct mutex file_mutex;
999 struct list_head cb_list;
1000 spinlock_t cb_spinlock;
1001 struct list_head cs_list;
1002 spinlock_t cs_spinlock;
1003 struct list_head cs_job_list;
1004 spinlock_t cs_job_spinlock;
1005 struct list_head userptr_list;
1006 spinlock_t userptr_spinlock;
1007 struct list_head ctx_mem_hash_list;
1008 spinlock_t ctx_mem_hash_spinlock;
1009 u64 addr;
1010 u64 mmu_addr;
1011 u32 mmu_asid;
1012 u8 i2c_bus;
1013 u8 i2c_addr;
1014 u8 i2c_reg;
1015 };
1016
1017
1018 /*
1019 * DEVICES
1020 */
1021
1022 /* Theoretical limit only. A single host can only contain up to 4 or 8 PCIe
1023 * x16 cards. In extreme cases, there are hosts that can accommodate 16 cards.
1024 */
1025 #define HL_MAX_MINORS 256
1026
1027 /*
1028 * Registers read & write functions.
1029 */
1030
1031 u32 hl_rreg(struct hl_device *hdev, u32 reg);
1032 void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
1033
1034 #define RREG32(reg) hdev->asic_funcs->rreg(hdev, (reg))
1035 #define WREG32(reg, v) hdev->asic_funcs->wreg(hdev, (reg), (v))
1036 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
1037 hdev->asic_funcs->rreg(hdev, (reg)))
1038
1039 #define WREG32_P(reg, val, mask) \
1040 do { \
1041 u32 tmp_ = RREG32(reg); \
1042 tmp_ &= (mask); \
1043 tmp_ |= ((val) & ~(mask)); \
1044 WREG32(reg, tmp_); \
1045 } while (0)
1046 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1047 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1048
1049 #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT
1050 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK
1051 #define WREG32_FIELD(reg, field, val) \
1052 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \
1053 (val) << REG_FIELD_SHIFT(reg, field))
1054
1055 /* Timeout should be longer when working with simulator but cap the
1056 * increased timeout to some maximum
1057 */
1058 #define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \
1059 ({ \
1060 ktime_t __timeout; \
1061 if (hdev->pdev) \
1062 __timeout = ktime_add_us(ktime_get(), timeout_us); \
1063 else \
1064 __timeout = ktime_add_us(ktime_get(),\
1065 min((u64)(timeout_us * 10), \
1066 (u64) HL_SIM_MAX_TIMEOUT_US)); \
1067 might_sleep_if(sleep_us); \
1068 for (;;) { \
1069 (val) = RREG32(addr); \
1070 if (cond) \
1071 break; \
1072 if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
1073 (val) = RREG32(addr); \
1074 break; \
1075 } \
1076 if (sleep_us) \
1077 usleep_range((sleep_us >> 2) + 1, sleep_us); \
1078 } \
1079 (cond) ? 0 : -ETIMEDOUT; \
1080 })
1081
1082 /*
1083 * address in this macro points always to a memory location in the
1084 * host's (server's) memory. That location is updated asynchronously
1085 * either by the direct access of the device or by another core.
1086 *
1087 * To work both in LE and BE architectures, we need to distinguish between the
1088 * two states (device or another core updates the memory location). Therefore,
1089 * if mem_written_by_device is true, the host memory being polled will be
1090 * updated directly by the device. If false, the host memory being polled will
1091 * be updated by host CPU. Required so host knows whether or not the memory
1092 * might need to be byte-swapped before returning value to caller.
1093 */
1094 #define hl_poll_timeout_memory(hdev, addr, val, cond, sleep_us, timeout_us, \
1095 mem_written_by_device) \
1096 ({ \
1097 ktime_t __timeout; \
1098 if (hdev->pdev) \
1099 __timeout = ktime_add_us(ktime_get(), timeout_us); \
1100 else \
1101 __timeout = ktime_add_us(ktime_get(),\
1102 min((u64)(timeout_us * 10), \
1103 (u64) HL_SIM_MAX_TIMEOUT_US)); \
1104 might_sleep_if(sleep_us); \
1105 for (;;) { \
1106 /* Verify we read updates done by other cores or by device */ \
1107 mb(); \
1108 (val) = *((u32 *) (uintptr_t) (addr)); \
1109 if (mem_written_by_device) \
1110 (val) = le32_to_cpu(*(__le32 *) &(val)); \
1111 if (cond) \
1112 break; \
1113 if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
1114 (val) = *((u32 *) (uintptr_t) (addr)); \
1115 if (mem_written_by_device) \
1116 (val) = le32_to_cpu(*(__le32 *) &(val)); \
1117 break; \
1118 } \
1119 if (sleep_us) \
1120 usleep_range((sleep_us >> 2) + 1, sleep_us); \
1121 } \
1122 (cond) ? 0 : -ETIMEDOUT; \
1123 })
1124
1125 #define hl_poll_timeout_device_memory(hdev, addr, val, cond, sleep_us, \
1126 timeout_us) \
1127 ({ \
1128 ktime_t __timeout; \
1129 if (hdev->pdev) \
1130 __timeout = ktime_add_us(ktime_get(), timeout_us); \
1131 else \
1132 __timeout = ktime_add_us(ktime_get(),\
1133 min((u64)(timeout_us * 10), \
1134 (u64) HL_SIM_MAX_TIMEOUT_US)); \
1135 might_sleep_if(sleep_us); \
1136 for (;;) { \
1137 (val) = readl(addr); \
1138 if (cond) \
1139 break; \
1140 if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
1141 (val) = readl(addr); \
1142 break; \
1143 } \
1144 if (sleep_us) \
1145 usleep_range((sleep_us >> 2) + 1, sleep_us); \
1146 } \
1147 (cond) ? 0 : -ETIMEDOUT; \
1148 })
1149
1150 struct hwmon_chip_info;
1151
1152 /**
1153 * struct hl_device_reset_work - reset workqueue task wrapper.
1154 * @reset_work: reset work to be done.
1155 * @hdev: habanalabs device structure.
1156 */
1157 struct hl_device_reset_work {
1158 struct work_struct reset_work;
1159 struct hl_device *hdev;
1160 };
1161
1162 /**
1163 * struct hl_device_idle_busy_ts - used for calculating device utilization rate.
1164 * @idle_to_busy_ts: timestamp where device changed from idle to busy.
1165 * @busy_to_idle_ts: timestamp where device changed from busy to idle.
1166 */
1167 struct hl_device_idle_busy_ts {
1168 ktime_t idle_to_busy_ts;
1169 ktime_t busy_to_idle_ts;
1170 };
1171
1172 /**
1173 * struct hl_device - habanalabs device structure.
1174 * @pdev: pointer to PCI device, can be NULL in case of simulator device.
1175 * @pcie_bar: array of available PCIe bars.
1176 * @rmmio: configuration area address on SRAM.
1177 * @cdev: related char device.
1178 * @cdev_ctrl: char device for control operations only (INFO IOCTL)
1179 * @dev: related kernel basic device structure.
1180 * @dev_ctrl: related kernel device structure for the control device
1181 * @work_freq: delayed work to lower device frequency if possible.
1182 * @work_heartbeat: delayed work for ArmCP is-alive check.
1183 * @asic_name: ASIC specific nmae.
1184 * @asic_type: ASIC specific type.
1185 * @completion_queue: array of hl_cq.
1186 * @cq_wq: work queue of completion queues for executing work in process context
1187 * @eq_wq: work queue of event queue for executing work in process context.
1188 * @kernel_ctx: Kernel driver context structure.
1189 * @kernel_queues: array of hl_hw_queue.
1190 * @hw_queues_mirror_list: CS mirror list for TDR.
1191 * @hw_queues_mirror_lock: protects hw_queues_mirror_list.
1192 * @kernel_cb_mgr: command buffer manager for creating/destroying/handling CGs.
1193 * @event_queue: event queue for IRQ from ArmCP.
1194 * @dma_pool: DMA pool for small allocations.
1195 * @cpu_accessible_dma_mem: Host <-> ArmCP shared memory CPU address.
1196 * @cpu_accessible_dma_address: Host <-> ArmCP shared memory DMA address.
1197 * @cpu_accessible_dma_pool: Host <-> ArmCP shared memory pool.
1198 * @asid_bitmap: holds used/available ASIDs.
1199 * @asid_mutex: protects asid_bitmap.
1200 * @send_cpu_message_lock: enforces only one message in Host <-> ArmCP queue.
1201 * @debug_lock: protects critical section of setting debug mode for device
1202 * @asic_prop: ASIC specific immutable properties.
1203 * @asic_funcs: ASIC specific functions.
1204 * @asic_specific: ASIC specific information to use only from ASIC files.
1205 * @mmu_pgt_pool: pool of available MMU hops.
1206 * @vm: virtual memory manager for MMU.
1207 * @mmu_cache_lock: protects MMU cache invalidation as it can serve one context.
1208 * @mmu_shadow_hop0: shadow mapping of the MMU hop 0 zone.
1209 * @hwmon_dev: H/W monitor device.
1210 * @pm_mng_profile: current power management profile.
1211 * @hl_chip_info: ASIC's sensors information.
1212 * @hl_debugfs: device's debugfs manager.
1213 * @cb_pool: list of preallocated CBs.
1214 * @cb_pool_lock: protects the CB pool.
1215 * @fpriv_list: list of file private data structures. Each structure is created
1216 * when a user opens the device
1217 * @fpriv_list_lock: protects the fpriv_list
1218 * @compute_ctx: current compute context executing.
1219 * @idle_busy_ts_arr: array to hold time stamps of transitions from idle to busy
1220 * and vice-versa
1221 * @dram_used_mem: current DRAM memory consumption.
1222 * @timeout_jiffies: device CS timeout value.
1223 * @max_power: the max power of the device, as configured by the sysadmin. This
1224 * value is saved so in case of hard-reset, the driver will restore
1225 * this value and update the F/W after the re-initialization
1226 * @in_reset: is device in reset flow.
1227 * @curr_pll_profile: current PLL profile.
1228 * @cs_active_cnt: number of active command submissions on this device (active
1229 * means already in H/W queues)
1230 * @major: habanalabs kernel driver major.
1231 * @high_pll: high PLL profile frequency.
1232 * @soft_reset_cnt: number of soft reset since the driver was loaded.
1233 * @hard_reset_cnt: number of hard reset since the driver was loaded.
1234 * @idle_busy_ts_idx: index of current entry in idle_busy_ts_arr
1235 * @id: device minor.
1236 * @id_control: minor of the control device
1237 * @disabled: is device disabled.
1238 * @late_init_done: is late init stage was done during initialization.
1239 * @hwmon_initialized: is H/W monitor sensors was initialized.
1240 * @hard_reset_pending: is there a hard reset work pending.
1241 * @heartbeat: is heartbeat sanity check towards ArmCP enabled.
1242 * @reset_on_lockup: true if a reset should be done in case of stuck CS, false
1243 * otherwise.
1244 * @dram_supports_virtual_memory: is MMU enabled towards DRAM.
1245 * @dram_default_page_mapping: is DRAM default page mapping enabled.
1246 * @init_done: is the initialization of the device done.
1247 * @mmu_enable: is MMU enabled.
1248 * @device_cpu_disabled: is the device CPU disabled (due to timeouts)
1249 * @dma_mask: the dma mask that was set for this device
1250 * @in_debug: is device under debug. This, together with fpriv_list, enforces
1251 * that only a single user is configuring the debug infrastructure.
1252 * @cdev_sysfs_created: were char devices and sysfs nodes created.
1253 */
1254 struct hl_device {
1255 struct pci_dev *pdev;
1256 void __iomem *pcie_bar[6];
1257 void __iomem *rmmio;
1258 struct cdev cdev;
1259 struct cdev cdev_ctrl;
1260 struct device *dev;
1261 struct device *dev_ctrl;
1262 struct delayed_work work_freq;
1263 struct delayed_work work_heartbeat;
1264 char asic_name[16];
1265 enum hl_asic_type asic_type;
1266 struct hl_cq *completion_queue;
1267 struct workqueue_struct *cq_wq;
1268 struct workqueue_struct *eq_wq;
1269 struct hl_ctx *kernel_ctx;
1270 struct hl_hw_queue *kernel_queues;
1271 struct list_head hw_queues_mirror_list;
1272 spinlock_t hw_queues_mirror_lock;
1273 struct hl_cb_mgr kernel_cb_mgr;
1274 struct hl_eq event_queue;
1275 struct dma_pool *dma_pool;
1276 void *cpu_accessible_dma_mem;
1277 dma_addr_t cpu_accessible_dma_address;
1278 struct gen_pool *cpu_accessible_dma_pool;
1279 unsigned long *asid_bitmap;
1280 struct mutex asid_mutex;
1281 struct mutex send_cpu_message_lock;
1282 struct mutex debug_lock;
1283 struct asic_fixed_properties asic_prop;
1284 const struct hl_asic_funcs *asic_funcs;
1285 void *asic_specific;
1286 struct gen_pool *mmu_pgt_pool;
1287 struct hl_vm vm;
1288 struct mutex mmu_cache_lock;
1289 void *mmu_shadow_hop0;
1290 struct device *hwmon_dev;
1291 enum hl_pm_mng_profile pm_mng_profile;
1292 struct hwmon_chip_info *hl_chip_info;
1293
1294 struct hl_dbg_device_entry hl_debugfs;
1295
1296 struct list_head cb_pool;
1297 spinlock_t cb_pool_lock;
1298
1299 struct list_head fpriv_list;
1300 struct mutex fpriv_list_lock;
1301
1302 struct hl_ctx *compute_ctx;
1303
1304 struct hl_device_idle_busy_ts *idle_busy_ts_arr;
1305
1306 atomic64_t dram_used_mem;
1307 u64 timeout_jiffies;
1308 u64 max_power;
1309 atomic_t in_reset;
1310 enum hl_pll_frequency curr_pll_profile;
1311 int cs_active_cnt;
1312 u32 major;
1313 u32 high_pll;
1314 u32 soft_reset_cnt;
1315 u32 hard_reset_cnt;
1316 u32 idle_busy_ts_idx;
1317 u16 id;
1318 u16 id_control;
1319 u8 disabled;
1320 u8 late_init_done;
1321 u8 hwmon_initialized;
1322 u8 hard_reset_pending;
1323 u8 heartbeat;
1324 u8 reset_on_lockup;
1325 u8 dram_supports_virtual_memory;
1326 u8 dram_default_page_mapping;
1327 u8 init_done;
1328 u8 device_cpu_disabled;
1329 u8 dma_mask;
1330 u8 in_debug;
1331 u8 cdev_sysfs_created;
1332
1333 /* Parameters for bring-up */
1334 u8 mmu_enable;
1335 u8 cpu_enable;
1336 u8 reset_pcilink;
1337 u8 cpu_queues_enable;
1338 u8 fw_loading;
1339 u8 pldm;
1340 };
1341
1342
1343 /*
1344 * IOCTLs
1345 */
1346
1347 /**
1348 * typedef hl_ioctl_t - typedef for ioctl function in the driver
1349 * @hpriv: pointer to the FD's private data, which contains state of
1350 * user process
1351 * @data: pointer to the input/output arguments structure of the IOCTL
1352 *
1353 * Return: 0 for success, negative value for error
1354 */
1355 typedef int hl_ioctl_t(struct hl_fpriv *hpriv, void *data);
1356
1357 /**
1358 * struct hl_ioctl_desc - describes an IOCTL entry of the driver.
1359 * @cmd: the IOCTL code as created by the kernel macros.
1360 * @func: pointer to the driver's function that should be called for this IOCTL.
1361 */
1362 struct hl_ioctl_desc {
1363 unsigned int cmd;
1364 hl_ioctl_t *func;
1365 };
1366
1367
1368 /*
1369 * Kernel module functions that can be accessed by entire module
1370 */
1371
1372 /**
1373 * hl_mem_area_inside_range() - Checks whether address+size are inside a range.
1374 * @address: The start address of the area we want to validate.
1375 * @size: The size in bytes of the area we want to validate.
1376 * @range_start_address: The start address of the valid range.
1377 * @range_end_address: The end address of the valid range.
1378 *
1379 * Return: true if the area is inside the valid range, false otherwise.
1380 */
1381 static inline bool hl_mem_area_inside_range(u64 address, u32 size,
1382 u64 range_start_address, u64 range_end_address)
1383 {
1384 u64 end_address = address + size;
1385
1386 if ((address >= range_start_address) &&
1387 (end_address <= range_end_address) &&
1388 (end_address > address))
1389 return true;
1390
1391 return false;
1392 }
1393
1394 /**
1395 * hl_mem_area_crosses_range() - Checks whether address+size crossing a range.
1396 * @address: The start address of the area we want to validate.
1397 * @size: The size in bytes of the area we want to validate.
1398 * @range_start_address: The start address of the valid range.
1399 * @range_end_address: The end address of the valid range.
1400 *
1401 * Return: true if the area overlaps part or all of the valid range,
1402 * false otherwise.
1403 */
1404 static inline bool hl_mem_area_crosses_range(u64 address, u32 size,
1405 u64 range_start_address, u64 range_end_address)
1406 {
1407 u64 end_address = address + size;
1408
1409 if ((address >= range_start_address) &&
1410 (address < range_end_address))
1411 return true;
1412
1413 if ((end_address >= range_start_address) &&
1414 (end_address < range_end_address))
1415 return true;
1416
1417 if ((address < range_start_address) &&
1418 (end_address >= range_end_address))
1419 return true;
1420
1421 return false;
1422 }
1423
1424 int hl_device_open(struct inode *inode, struct file *filp);
1425 int hl_device_open_ctrl(struct inode *inode, struct file *filp);
1426 bool hl_device_disabled_or_in_reset(struct hl_device *hdev);
1427 enum hl_device_status hl_device_status(struct hl_device *hdev);
1428 int hl_device_set_debug_mode(struct hl_device *hdev, bool enable);
1429 int create_hdev(struct hl_device **dev, struct pci_dev *pdev,
1430 enum hl_asic_type asic_type, int minor);
1431 void destroy_hdev(struct hl_device *hdev);
1432 int hl_hw_queues_create(struct hl_device *hdev);
1433 void hl_hw_queues_destroy(struct hl_device *hdev);
1434 int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id,
1435 u32 cb_size, u64 cb_ptr);
1436 int hl_hw_queue_schedule_cs(struct hl_cs *cs);
1437 u32 hl_hw_queue_add_ptr(u32 ptr, u16 val);
1438 void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id);
1439 void hl_int_hw_queue_update_ci(struct hl_cs *cs);
1440 void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset);
1441
1442 #define hl_queue_inc_ptr(p) hl_hw_queue_add_ptr(p, 1)
1443 #define hl_pi_2_offset(pi) ((pi) & (HL_QUEUE_LENGTH - 1))
1444
1445 int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id);
1446 void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q);
1447 int hl_eq_init(struct hl_device *hdev, struct hl_eq *q);
1448 void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q);
1449 void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q);
1450 void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q);
1451 irqreturn_t hl_irq_handler_cq(int irq, void *arg);
1452 irqreturn_t hl_irq_handler_eq(int irq, void *arg);
1453 u32 hl_cq_inc_ptr(u32 ptr);
1454
1455 int hl_asid_init(struct hl_device *hdev);
1456 void hl_asid_fini(struct hl_device *hdev);
1457 unsigned long hl_asid_alloc(struct hl_device *hdev);
1458 void hl_asid_free(struct hl_device *hdev, unsigned long asid);
1459
1460 int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv);
1461 void hl_ctx_free(struct hl_device *hdev, struct hl_ctx *ctx);
1462 int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx);
1463 void hl_ctx_do_release(struct kref *ref);
1464 void hl_ctx_get(struct hl_device *hdev, struct hl_ctx *ctx);
1465 int hl_ctx_put(struct hl_ctx *ctx);
1466 struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq);
1467 void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr);
1468 void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr);
1469
1470 int hl_device_init(struct hl_device *hdev, struct class *hclass);
1471 void hl_device_fini(struct hl_device *hdev);
1472 int hl_device_suspend(struct hl_device *hdev);
1473 int hl_device_resume(struct hl_device *hdev);
1474 int hl_device_reset(struct hl_device *hdev, bool hard_reset,
1475 bool from_hard_reset_thread);
1476 void hl_hpriv_get(struct hl_fpriv *hpriv);
1477 void hl_hpriv_put(struct hl_fpriv *hpriv);
1478 int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq);
1479 uint32_t hl_device_utilization(struct hl_device *hdev, uint32_t period_ms);
1480
1481 int hl_build_hwmon_channel_info(struct hl_device *hdev,
1482 struct armcp_sensor *sensors_arr);
1483
1484 int hl_sysfs_init(struct hl_device *hdev);
1485 void hl_sysfs_fini(struct hl_device *hdev);
1486
1487 int hl_hwmon_init(struct hl_device *hdev);
1488 void hl_hwmon_fini(struct hl_device *hdev);
1489
1490 int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, u32 cb_size,
1491 u64 *handle, int ctx_id);
1492 int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle);
1493 int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma);
1494 struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr,
1495 u32 handle);
1496 void hl_cb_put(struct hl_cb *cb);
1497 void hl_cb_mgr_init(struct hl_cb_mgr *mgr);
1498 void hl_cb_mgr_fini(struct hl_device *hdev, struct hl_cb_mgr *mgr);
1499 struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size);
1500 int hl_cb_pool_init(struct hl_device *hdev);
1501 int hl_cb_pool_fini(struct hl_device *hdev);
1502
1503 void hl_cs_rollback_all(struct hl_device *hdev);
1504 struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, bool ext_queue);
1505
1506 void goya_set_asic_funcs(struct hl_device *hdev);
1507
1508 int hl_vm_ctx_init(struct hl_ctx *ctx);
1509 void hl_vm_ctx_fini(struct hl_ctx *ctx);
1510
1511 int hl_vm_init(struct hl_device *hdev);
1512 void hl_vm_fini(struct hl_device *hdev);
1513
1514 int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size,
1515 struct hl_userptr *userptr);
1516 int hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr);
1517 void hl_userptr_delete_list(struct hl_device *hdev,
1518 struct list_head *userptr_list);
1519 bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, u32 size,
1520 struct list_head *userptr_list,
1521 struct hl_userptr **userptr);
1522
1523 int hl_mmu_init(struct hl_device *hdev);
1524 void hl_mmu_fini(struct hl_device *hdev);
1525 int hl_mmu_ctx_init(struct hl_ctx *ctx);
1526 void hl_mmu_ctx_fini(struct hl_ctx *ctx);
1527 int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size);
1528 int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size);
1529 void hl_mmu_swap_out(struct hl_ctx *ctx);
1530 void hl_mmu_swap_in(struct hl_ctx *ctx);
1531
1532 int hl_fw_push_fw_to_device(struct hl_device *hdev, const char *fw_name,
1533 void __iomem *dst);
1534 int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode);
1535 int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg,
1536 u16 len, u32 timeout, long *result);
1537 int hl_fw_test_cpu_queue(struct hl_device *hdev);
1538 void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
1539 dma_addr_t *dma_handle);
1540 void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
1541 void *vaddr);
1542 int hl_fw_send_heartbeat(struct hl_device *hdev);
1543 int hl_fw_armcp_info_get(struct hl_device *hdev);
1544 int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size);
1545
1546 int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
1547 bool is_wc[3]);
1548 int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data);
1549 int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar,
1550 u64 addr);
1551 int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address,
1552 u64 dram_base_address, u64 host_phys_base_address,
1553 u64 host_phys_size);
1554 int hl_pci_init(struct hl_device *hdev, u8 dma_mask);
1555 void hl_pci_fini(struct hl_device *hdev);
1556 int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask);
1557
1558 long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr);
1559 void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq);
1560 long hl_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
1561 long hl_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
1562 long hl_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
1563 long hl_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
1564 long hl_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
1565 void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
1566 long value);
1567 u64 hl_get_max_power(struct hl_device *hdev);
1568 void hl_set_max_power(struct hl_device *hdev, u64 value);
1569
1570 #ifdef CONFIG_DEBUG_FS
1571
1572 void hl_debugfs_init(void);
1573 void hl_debugfs_fini(void);
1574 void hl_debugfs_add_device(struct hl_device *hdev);
1575 void hl_debugfs_remove_device(struct hl_device *hdev);
1576 void hl_debugfs_add_file(struct hl_fpriv *hpriv);
1577 void hl_debugfs_remove_file(struct hl_fpriv *hpriv);
1578 void hl_debugfs_add_cb(struct hl_cb *cb);
1579 void hl_debugfs_remove_cb(struct hl_cb *cb);
1580 void hl_debugfs_add_cs(struct hl_cs *cs);
1581 void hl_debugfs_remove_cs(struct hl_cs *cs);
1582 void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job);
1583 void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job);
1584 void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr);
1585 void hl_debugfs_remove_userptr(struct hl_device *hdev,
1586 struct hl_userptr *userptr);
1587 void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
1588 void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
1589
1590 #else
1591
1592 static inline void __init hl_debugfs_init(void)
1593 {
1594 }
1595
1596 static inline void hl_debugfs_fini(void)
1597 {
1598 }
1599
1600 static inline void hl_debugfs_add_device(struct hl_device *hdev)
1601 {
1602 }
1603
1604 static inline void hl_debugfs_remove_device(struct hl_device *hdev)
1605 {
1606 }
1607
1608 static inline void hl_debugfs_add_file(struct hl_fpriv *hpriv)
1609 {
1610 }
1611
1612 static inline void hl_debugfs_remove_file(struct hl_fpriv *hpriv)
1613 {
1614 }
1615
1616 static inline void hl_debugfs_add_cb(struct hl_cb *cb)
1617 {
1618 }
1619
1620 static inline void hl_debugfs_remove_cb(struct hl_cb *cb)
1621 {
1622 }
1623
1624 static inline void hl_debugfs_add_cs(struct hl_cs *cs)
1625 {
1626 }
1627
1628 static inline void hl_debugfs_remove_cs(struct hl_cs *cs)
1629 {
1630 }
1631
1632 static inline void hl_debugfs_add_job(struct hl_device *hdev,
1633 struct hl_cs_job *job)
1634 {
1635 }
1636
1637 static inline void hl_debugfs_remove_job(struct hl_device *hdev,
1638 struct hl_cs_job *job)
1639 {
1640 }
1641
1642 static inline void hl_debugfs_add_userptr(struct hl_device *hdev,
1643 struct hl_userptr *userptr)
1644 {
1645 }
1646
1647 static inline void hl_debugfs_remove_userptr(struct hl_device *hdev,
1648 struct hl_userptr *userptr)
1649 {
1650 }
1651
1652 static inline void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev,
1653 struct hl_ctx *ctx)
1654 {
1655 }
1656
1657 static inline void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev,
1658 struct hl_ctx *ctx)
1659 {
1660 }
1661
1662 #endif
1663
1664 /* IOCTLs */
1665 long hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
1666 long hl_ioctl_control(struct file *filep, unsigned int cmd, unsigned long arg);
1667 int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data);
1668 int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data);
1669 int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data);
1670 int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data);
1671
1672 #endif /* HABANALABSP_H_ */