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13 #ifndef ASIC_REG_DMA_NRTR_REGS_H_
14 #define ASIC_REG_DMA_NRTR_REGS_H_
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21
22 #define mmDMA_NRTR_HBW_MAX_CRED 0x1C0100
23
24 #define mmDMA_NRTR_LBW_MAX_CRED 0x1C0120
25
26 #define mmDMA_NRTR_DBG_E_ARB 0x1C0300
27
28 #define mmDMA_NRTR_DBG_W_ARB 0x1C0304
29
30 #define mmDMA_NRTR_DBG_N_ARB 0x1C0308
31
32 #define mmDMA_NRTR_DBG_S_ARB 0x1C030C
33
34 #define mmDMA_NRTR_DBG_L_ARB 0x1C0310
35
36 #define mmDMA_NRTR_DBG_E_ARB_MAX 0x1C0320
37
38 #define mmDMA_NRTR_DBG_W_ARB_MAX 0x1C0324
39
40 #define mmDMA_NRTR_DBG_N_ARB_MAX 0x1C0328
41
42 #define mmDMA_NRTR_DBG_S_ARB_MAX 0x1C032C
43
44 #define mmDMA_NRTR_DBG_L_ARB_MAX 0x1C0330
45
46 #define mmDMA_NRTR_SPLIT_COEF_0 0x1C0400
47
48 #define mmDMA_NRTR_SPLIT_COEF_1 0x1C0404
49
50 #define mmDMA_NRTR_SPLIT_COEF_2 0x1C0408
51
52 #define mmDMA_NRTR_SPLIT_COEF_3 0x1C040C
53
54 #define mmDMA_NRTR_SPLIT_COEF_4 0x1C0410
55
56 #define mmDMA_NRTR_SPLIT_COEF_5 0x1C0414
57
58 #define mmDMA_NRTR_SPLIT_COEF_6 0x1C0418
59
60 #define mmDMA_NRTR_SPLIT_COEF_7 0x1C041C
61
62 #define mmDMA_NRTR_SPLIT_COEF_8 0x1C0420
63
64 #define mmDMA_NRTR_SPLIT_COEF_9 0x1C0424
65
66 #define mmDMA_NRTR_SPLIT_CFG 0x1C0440
67
68 #define mmDMA_NRTR_SPLIT_RD_SAT 0x1C0444
69
70 #define mmDMA_NRTR_SPLIT_RD_RST_TOKEN 0x1C0448
71
72 #define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0 0x1C044C
73
74 #define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1 0x1C0450
75
76 #define mmDMA_NRTR_SPLIT_WR_SAT 0x1C0454
77
78 #define mmDMA_NRTR_WPLIT_WR_TST_TOLEN 0x1C0458
79
80 #define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0 0x1C045C
81
82 #define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1 0x1C0460
83
84 #define mmDMA_NRTR_HBW_RANGE_HIT 0x1C0470
85
86 #define mmDMA_NRTR_HBW_RANGE_MASK_L_0 0x1C0480
87
88 #define mmDMA_NRTR_HBW_RANGE_MASK_L_1 0x1C0484
89
90 #define mmDMA_NRTR_HBW_RANGE_MASK_L_2 0x1C0488
91
92 #define mmDMA_NRTR_HBW_RANGE_MASK_L_3 0x1C048C
93
94 #define mmDMA_NRTR_HBW_RANGE_MASK_L_4 0x1C0490
95
96 #define mmDMA_NRTR_HBW_RANGE_MASK_L_5 0x1C0494
97
98 #define mmDMA_NRTR_HBW_RANGE_MASK_L_6 0x1C0498
99
100 #define mmDMA_NRTR_HBW_RANGE_MASK_L_7 0x1C049C
101
102 #define mmDMA_NRTR_HBW_RANGE_MASK_H_0 0x1C04A0
103
104 #define mmDMA_NRTR_HBW_RANGE_MASK_H_1 0x1C04A4
105
106 #define mmDMA_NRTR_HBW_RANGE_MASK_H_2 0x1C04A8
107
108 #define mmDMA_NRTR_HBW_RANGE_MASK_H_3 0x1C04AC
109
110 #define mmDMA_NRTR_HBW_RANGE_MASK_H_4 0x1C04B0
111
112 #define mmDMA_NRTR_HBW_RANGE_MASK_H_5 0x1C04B4
113
114 #define mmDMA_NRTR_HBW_RANGE_MASK_H_6 0x1C04B8
115
116 #define mmDMA_NRTR_HBW_RANGE_MASK_H_7 0x1C04BC
117
118 #define mmDMA_NRTR_HBW_RANGE_BASE_L_0 0x1C04C0
119
120 #define mmDMA_NRTR_HBW_RANGE_BASE_L_1 0x1C04C4
121
122 #define mmDMA_NRTR_HBW_RANGE_BASE_L_2 0x1C04C8
123
124 #define mmDMA_NRTR_HBW_RANGE_BASE_L_3 0x1C04CC
125
126 #define mmDMA_NRTR_HBW_RANGE_BASE_L_4 0x1C04D0
127
128 #define mmDMA_NRTR_HBW_RANGE_BASE_L_5 0x1C04D4
129
130 #define mmDMA_NRTR_HBW_RANGE_BASE_L_6 0x1C04D8
131
132 #define mmDMA_NRTR_HBW_RANGE_BASE_L_7 0x1C04DC
133
134 #define mmDMA_NRTR_HBW_RANGE_BASE_H_0 0x1C04E0
135
136 #define mmDMA_NRTR_HBW_RANGE_BASE_H_1 0x1C04E4
137
138 #define mmDMA_NRTR_HBW_RANGE_BASE_H_2 0x1C04E8
139
140 #define mmDMA_NRTR_HBW_RANGE_BASE_H_3 0x1C04EC
141
142 #define mmDMA_NRTR_HBW_RANGE_BASE_H_4 0x1C04F0
143
144 #define mmDMA_NRTR_HBW_RANGE_BASE_H_5 0x1C04F4
145
146 #define mmDMA_NRTR_HBW_RANGE_BASE_H_6 0x1C04F8
147
148 #define mmDMA_NRTR_HBW_RANGE_BASE_H_7 0x1C04FC
149
150 #define mmDMA_NRTR_LBW_RANGE_HIT 0x1C0500
151
152 #define mmDMA_NRTR_LBW_RANGE_MASK_0 0x1C0510
153
154 #define mmDMA_NRTR_LBW_RANGE_MASK_1 0x1C0514
155
156 #define mmDMA_NRTR_LBW_RANGE_MASK_2 0x1C0518
157
158 #define mmDMA_NRTR_LBW_RANGE_MASK_3 0x1C051C
159
160 #define mmDMA_NRTR_LBW_RANGE_MASK_4 0x1C0520
161
162 #define mmDMA_NRTR_LBW_RANGE_MASK_5 0x1C0524
163
164 #define mmDMA_NRTR_LBW_RANGE_MASK_6 0x1C0528
165
166 #define mmDMA_NRTR_LBW_RANGE_MASK_7 0x1C052C
167
168 #define mmDMA_NRTR_LBW_RANGE_MASK_8 0x1C0530
169
170 #define mmDMA_NRTR_LBW_RANGE_MASK_9 0x1C0534
171
172 #define mmDMA_NRTR_LBW_RANGE_MASK_10 0x1C0538
173
174 #define mmDMA_NRTR_LBW_RANGE_MASK_11 0x1C053C
175
176 #define mmDMA_NRTR_LBW_RANGE_MASK_12 0x1C0540
177
178 #define mmDMA_NRTR_LBW_RANGE_MASK_13 0x1C0544
179
180 #define mmDMA_NRTR_LBW_RANGE_MASK_14 0x1C0548
181
182 #define mmDMA_NRTR_LBW_RANGE_MASK_15 0x1C054C
183
184 #define mmDMA_NRTR_LBW_RANGE_BASE_0 0x1C0550
185
186 #define mmDMA_NRTR_LBW_RANGE_BASE_1 0x1C0554
187
188 #define mmDMA_NRTR_LBW_RANGE_BASE_2 0x1C0558
189
190 #define mmDMA_NRTR_LBW_RANGE_BASE_3 0x1C055C
191
192 #define mmDMA_NRTR_LBW_RANGE_BASE_4 0x1C0560
193
194 #define mmDMA_NRTR_LBW_RANGE_BASE_5 0x1C0564
195
196 #define mmDMA_NRTR_LBW_RANGE_BASE_6 0x1C0568
197
198 #define mmDMA_NRTR_LBW_RANGE_BASE_7 0x1C056C
199
200 #define mmDMA_NRTR_LBW_RANGE_BASE_8 0x1C0570
201
202 #define mmDMA_NRTR_LBW_RANGE_BASE_9 0x1C0574
203
204 #define mmDMA_NRTR_LBW_RANGE_BASE_10 0x1C0578
205
206 #define mmDMA_NRTR_LBW_RANGE_BASE_11 0x1C057C
207
208 #define mmDMA_NRTR_LBW_RANGE_BASE_12 0x1C0580
209
210 #define mmDMA_NRTR_LBW_RANGE_BASE_13 0x1C0584
211
212 #define mmDMA_NRTR_LBW_RANGE_BASE_14 0x1C0588
213
214 #define mmDMA_NRTR_LBW_RANGE_BASE_15 0x1C058C
215
216 #define mmDMA_NRTR_RGLTR 0x1C0590
217
218 #define mmDMA_NRTR_RGLTR_WR_RESULT 0x1C0594
219
220 #define mmDMA_NRTR_RGLTR_RD_RESULT 0x1C0598
221
222 #define mmDMA_NRTR_SCRAMB_EN 0x1C0600
223
224 #define mmDMA_NRTR_NON_LIN_SCRAMB 0x1C0604
225
226 #endif