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13 #ifndef ASIC_REG_MMU_REGS_H_
14 #define ASIC_REG_MMU_REGS_H_
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22 #define mmMMU_INPUT_FIFO_THRESHOLD 0x480000
23
24 #define mmMMU_MMU_ENABLE 0x48000C
25
26 #define mmMMU_FORCE_ORDERING 0x480010
27
28 #define mmMMU_FEATURE_ENABLE 0x480014
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30 #define mmMMU_VA_ORDERING_MASK_31_7 0x480018
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32 #define mmMMU_VA_ORDERING_MASK_49_32 0x48001C
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34 #define mmMMU_LOG2_DDR_SIZE 0x480020
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36 #define mmMMU_SCRAMBLER 0x480024
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38 #define mmMMU_MEM_INIT_BUSY 0x480028
39
40 #define mmMMU_SPI_MASK 0x48002C
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42 #define mmMMU_SPI_CAUSE 0x480030
43
44 #define mmMMU_PAGE_ERROR_CAPTURE 0x480034
45
46 #define mmMMU_PAGE_ERROR_CAPTURE_VA 0x480038
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48 #define mmMMU_ACCESS_ERROR_CAPTURE 0x48003C
49
50 #define mmMMU_ACCESS_ERROR_CAPTURE_VA 0x480040
51
52 #endif