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13 #ifndef ASIC_REG_TPC0_QM_REGS_H_
14 #define ASIC_REG_TPC0_QM_REGS_H_
15
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20
21
22 #define mmTPC0_QM_GLBL_CFG0 0xE08000
23
24 #define mmTPC0_QM_GLBL_CFG1 0xE08004
25
26 #define mmTPC0_QM_GLBL_PROT 0xE08008
27
28 #define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C
29
30 #define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08010
31
32 #define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08014
33
34 #define mmTPC0_QM_GLBL_ERR_WDATA 0xE08018
35
36 #define mmTPC0_QM_GLBL_SECURE_PROPS 0xE0801C
37
38 #define mmTPC0_QM_GLBL_NON_SECURE_PROPS 0xE08020
39
40 #define mmTPC0_QM_GLBL_STS0 0xE08024
41
42 #define mmTPC0_QM_GLBL_STS1 0xE08028
43
44 #define mmTPC0_QM_PQ_BASE_LO 0xE08060
45
46 #define mmTPC0_QM_PQ_BASE_HI 0xE08064
47
48 #define mmTPC0_QM_PQ_SIZE 0xE08068
49
50 #define mmTPC0_QM_PQ_PI 0xE0806C
51
52 #define mmTPC0_QM_PQ_CI 0xE08070
53
54 #define mmTPC0_QM_PQ_CFG0 0xE08074
55
56 #define mmTPC0_QM_PQ_CFG1 0xE08078
57
58 #define mmTPC0_QM_PQ_ARUSER 0xE0807C
59
60 #define mmTPC0_QM_PQ_PUSH0 0xE08080
61
62 #define mmTPC0_QM_PQ_PUSH1 0xE08084
63
64 #define mmTPC0_QM_PQ_PUSH2 0xE08088
65
66 #define mmTPC0_QM_PQ_PUSH3 0xE0808C
67
68 #define mmTPC0_QM_PQ_STS0 0xE08090
69
70 #define mmTPC0_QM_PQ_STS1 0xE08094
71
72 #define mmTPC0_QM_PQ_RD_RATE_LIM_EN 0xE080A0
73
74 #define mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE080A4
75
76 #define mmTPC0_QM_PQ_RD_RATE_LIM_SAT 0xE080A8
77
78 #define mmTPC0_QM_PQ_RD_RATE_LIM_TOUT 0xE080AC
79
80 #define mmTPC0_QM_CQ_CFG0 0xE080B0
81
82 #define mmTPC0_QM_CQ_CFG1 0xE080B4
83
84 #define mmTPC0_QM_CQ_ARUSER 0xE080B8
85
86 #define mmTPC0_QM_CQ_PTR_LO 0xE080C0
87
88 #define mmTPC0_QM_CQ_PTR_HI 0xE080C4
89
90 #define mmTPC0_QM_CQ_TSIZE 0xE080C8
91
92 #define mmTPC0_QM_CQ_CTL 0xE080CC
93
94 #define mmTPC0_QM_CQ_PTR_LO_STS 0xE080D4
95
96 #define mmTPC0_QM_CQ_PTR_HI_STS 0xE080D8
97
98 #define mmTPC0_QM_CQ_TSIZE_STS 0xE080DC
99
100 #define mmTPC0_QM_CQ_CTL_STS 0xE080E0
101
102 #define mmTPC0_QM_CQ_STS0 0xE080E4
103
104 #define mmTPC0_QM_CQ_STS1 0xE080E8
105
106 #define mmTPC0_QM_CQ_RD_RATE_LIM_EN 0xE080F0
107
108 #define mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE080F4
109
110 #define mmTPC0_QM_CQ_RD_RATE_LIM_SAT 0xE080F8
111
112 #define mmTPC0_QM_CQ_RD_RATE_LIM_TOUT 0xE080FC
113
114 #define mmTPC0_QM_CQ_IFIFO_CNT 0xE08108
115
116 #define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO 0xE08120
117
118 #define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI 0xE08124
119
120 #define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO 0xE08128
121
122 #define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI 0xE0812C
123
124 #define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO 0xE08130
125
126 #define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI 0xE08134
127
128 #define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO 0xE08138
129
130 #define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI 0xE0813C
131
132 #define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET 0xE08140
133
134 #define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE08144
135
136 #define mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE08148
137
138 #define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE0814C
139
140 #define mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE08150
141
142 #define mmTPC0_QM_CP_LDMA_COMMIT_OFFSET 0xE08154
143
144 #define mmTPC0_QM_CP_FENCE0_RDATA 0xE08158
145
146 #define mmTPC0_QM_CP_FENCE1_RDATA 0xE0815C
147
148 #define mmTPC0_QM_CP_FENCE2_RDATA 0xE08160
149
150 #define mmTPC0_QM_CP_FENCE3_RDATA 0xE08164
151
152 #define mmTPC0_QM_CP_FENCE0_CNT 0xE08168
153
154 #define mmTPC0_QM_CP_FENCE1_CNT 0xE0816C
155
156 #define mmTPC0_QM_CP_FENCE2_CNT 0xE08170
157
158 #define mmTPC0_QM_CP_FENCE3_CNT 0xE08174
159
160 #define mmTPC0_QM_CP_STS 0xE08178
161
162 #define mmTPC0_QM_CP_CURRENT_INST_LO 0xE0817C
163
164 #define mmTPC0_QM_CP_CURRENT_INST_HI 0xE08180
165
166 #define mmTPC0_QM_CP_BARRIER_CFG 0xE08184
167
168 #define mmTPC0_QM_CP_DBG_0 0xE08188
169
170 #define mmTPC0_QM_PQ_BUF_ADDR 0xE08300
171
172 #define mmTPC0_QM_PQ_BUF_RDATA 0xE08304
173
174 #define mmTPC0_QM_CQ_BUF_ADDR 0xE08308
175
176 #define mmTPC0_QM_CQ_BUF_RDATA 0xE0830C
177
178 #endif