root/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_MMU_MASKS_H_
  14 #define ASIC_REG_MMU_MASKS_H_
  15 
  16 /*
  17  *****************************************
  18  *   MMU (Prototype: MMU)
  19  *****************************************
  20  */
  21 
  22 /* MMU_INPUT_FIFO_THRESHOLD */
  23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT                           0
  24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK                            0x7
  25 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT                          4
  26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK                           0x70
  27 #define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT                           8
  28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK                            0x700
  29 #define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT                           12
  30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK                            0x7000
  31 #define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT                           16
  32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK                            0x70000
  33 #define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT                           20
  34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK                            0x700000
  35 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT                         24
  36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK                          0x7000000
  37 
  38 /* MMU_MMU_ENABLE */
  39 #define MMU_MMU_ENABLE_R_SHIFT                                       0
  40 #define MMU_MMU_ENABLE_R_MASK                                        0x1
  41 
  42 /* MMU_FORCE_ORDERING */
  43 #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT                   0
  44 #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK                    0x1
  45 #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT                  1
  46 #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK                   0x2
  47 #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT                   2
  48 #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK                    0x4
  49 #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT                   3
  50 #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK                    0x8
  51 #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT                   4
  52 #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK                    0x10
  53 #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT                   5
  54 #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK                    0x20
  55 #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT               6
  56 #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK                0x40
  57 #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT                 8
  58 #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK                  0x100
  59 #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT                9
  60 #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK                 0x200
  61 #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT                 10
  62 #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK                  0x400
  63 #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT                 11
  64 #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK                  0x800
  65 #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT                 12
  66 #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK                  0x1000
  67 #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT                 13
  68 #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK                  0x2000
  69 #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT             14
  70 #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK              0x4000
  71 
  72 /* MMU_FEATURE_ENABLE */
  73 #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT                      0
  74 #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK                       0x1
  75 #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT                     1
  76 #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK                      0x2
  77 #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT                       2
  78 #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK                        0x4
  79 #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT                     3
  80 #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK                      0x8
  81 #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT             4
  82 #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK              0x10
  83 #define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT                        5
  84 #define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK                         0x20
  85 
  86 /* MMU_VA_ORDERING_MASK_31_7 */
  87 #define MMU_VA_ORDERING_MASK_31_7_R_SHIFT                            0
  88 #define MMU_VA_ORDERING_MASK_31_7_R_MASK                             0x1FFFFFF
  89 
  90 /* MMU_VA_ORDERING_MASK_49_32 */
  91 #define MMU_VA_ORDERING_MASK_49_32_R_SHIFT                           0
  92 #define MMU_VA_ORDERING_MASK_49_32_R_MASK                            0x3FFFF
  93 
  94 /* MMU_LOG2_DDR_SIZE */
  95 #define MMU_LOG2_DDR_SIZE_R_SHIFT                                    0
  96 #define MMU_LOG2_DDR_SIZE_R_MASK                                     0xFF
  97 
  98 /* MMU_SCRAMBLER */
  99 #define MMU_SCRAMBLER_ADDR_BIT_SHIFT                                 0
 100 #define MMU_SCRAMBLER_ADDR_BIT_MASK                                  0x3F
 101 #define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT                            6
 102 #define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK                             0x40
 103 #define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT                            7
 104 #define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK                             0x80
 105 
 106 /* MMU_MEM_INIT_BUSY */
 107 #define MMU_MEM_INIT_BUSY_DATA_SHIFT                                 0
 108 #define MMU_MEM_INIT_BUSY_DATA_MASK                                  0x3
 109 #define MMU_MEM_INIT_BUSY_OBI0_SHIFT                                 2
 110 #define MMU_MEM_INIT_BUSY_OBI0_MASK                                  0x4
 111 #define MMU_MEM_INIT_BUSY_OBI1_SHIFT                                 3
 112 #define MMU_MEM_INIT_BUSY_OBI1_MASK                                  0x8
 113 
 114 /* MMU_SPI_MASK */
 115 #define MMU_SPI_MASK_R_SHIFT                                         0
 116 #define MMU_SPI_MASK_R_MASK                                          0xFF
 117 
 118 /* MMU_SPI_CAUSE */
 119 #define MMU_SPI_CAUSE_R_SHIFT                                        0
 120 #define MMU_SPI_CAUSE_R_MASK                                         0xFF
 121 
 122 /* MMU_PAGE_ERROR_CAPTURE */
 123 #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT                        0
 124 #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK                         0x3FFFF
 125 #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT                     18
 126 #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK                      0x40000
 127 
 128 /* MMU_PAGE_ERROR_CAPTURE_VA */
 129 #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT                      0
 130 #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK                       0xFFFFFFFF
 131 
 132 /* MMU_ACCESS_ERROR_CAPTURE */
 133 #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT                      0
 134 #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK                       0x3FFFF
 135 #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT                   18
 136 #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK                    0x40000
 137 
 138 /* MMU_ACCESS_ERROR_CAPTURE_VA */
 139 #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT                    0
 140 #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK                     0xFFFFFFFF
 141 
 142 #endif /* ASIC_REG_MMU_MASKS_H_ */