root/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_MME_CMDQ_REGS_H_
  14 #define ASIC_REG_MME_CMDQ_REGS_H_
  15 
  16 /*
  17  *****************************************
  18  *   MME_CMDQ (Prototype: CMDQ)
  19  *****************************************
  20  */
  21 
  22 #define mmMME_CMDQ_GLBL_CFG0                                         0xD9000
  23 
  24 #define mmMME_CMDQ_GLBL_CFG1                                         0xD9004
  25 
  26 #define mmMME_CMDQ_GLBL_PROT                                         0xD9008
  27 
  28 #define mmMME_CMDQ_GLBL_ERR_CFG                                      0xD900C
  29 
  30 #define mmMME_CMDQ_GLBL_ERR_ADDR_LO                                  0xD9010
  31 
  32 #define mmMME_CMDQ_GLBL_ERR_ADDR_HI                                  0xD9014
  33 
  34 #define mmMME_CMDQ_GLBL_ERR_WDATA                                    0xD9018
  35 
  36 #define mmMME_CMDQ_GLBL_SECURE_PROPS                                 0xD901C
  37 
  38 #define mmMME_CMDQ_GLBL_NON_SECURE_PROPS                             0xD9020
  39 
  40 #define mmMME_CMDQ_GLBL_STS0                                         0xD9024
  41 
  42 #define mmMME_CMDQ_GLBL_STS1                                         0xD9028
  43 
  44 #define mmMME_CMDQ_CQ_CFG0                                           0xD90B0
  45 
  46 #define mmMME_CMDQ_CQ_CFG1                                           0xD90B4
  47 
  48 #define mmMME_CMDQ_CQ_ARUSER                                         0xD90B8
  49 
  50 #define mmMME_CMDQ_CQ_PTR_LO                                         0xD90C0
  51 
  52 #define mmMME_CMDQ_CQ_PTR_HI                                         0xD90C4
  53 
  54 #define mmMME_CMDQ_CQ_TSIZE                                          0xD90C8
  55 
  56 #define mmMME_CMDQ_CQ_CTL                                            0xD90CC
  57 
  58 #define mmMME_CMDQ_CQ_PTR_LO_STS                                     0xD90D4
  59 
  60 #define mmMME_CMDQ_CQ_PTR_HI_STS                                     0xD90D8
  61 
  62 #define mmMME_CMDQ_CQ_TSIZE_STS                                      0xD90DC
  63 
  64 #define mmMME_CMDQ_CQ_CTL_STS                                        0xD90E0
  65 
  66 #define mmMME_CMDQ_CQ_STS0                                           0xD90E4
  67 
  68 #define mmMME_CMDQ_CQ_STS1                                           0xD90E8
  69 
  70 #define mmMME_CMDQ_CQ_RD_RATE_LIM_EN                                 0xD90F0
  71 
  72 #define mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                          0xD90F4
  73 
  74 #define mmMME_CMDQ_CQ_RD_RATE_LIM_SAT                                0xD90F8
  75 
  76 #define mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT                               0xD90FC
  77 
  78 #define mmMME_CMDQ_CQ_IFIFO_CNT                                      0xD9108
  79 
  80 #define mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO                              0xD9120
  81 
  82 #define mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI                              0xD9124
  83 
  84 #define mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO                              0xD9128
  85 
  86 #define mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI                              0xD912C
  87 
  88 #define mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO                              0xD9130
  89 
  90 #define mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI                              0xD9134
  91 
  92 #define mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO                              0xD9138
  93 
  94 #define mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI                              0xD913C
  95 
  96 #define mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET                              0xD9140
  97 
  98 #define mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                        0xD9144
  99 
 100 #define mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                        0xD9148
 101 
 102 #define mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                        0xD914C
 103 
 104 #define mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                        0xD9150
 105 
 106 #define mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET                             0xD9154
 107 
 108 #define mmMME_CMDQ_CP_FENCE0_RDATA                                   0xD9158
 109 
 110 #define mmMME_CMDQ_CP_FENCE1_RDATA                                   0xD915C
 111 
 112 #define mmMME_CMDQ_CP_FENCE2_RDATA                                   0xD9160
 113 
 114 #define mmMME_CMDQ_CP_FENCE3_RDATA                                   0xD9164
 115 
 116 #define mmMME_CMDQ_CP_FENCE0_CNT                                     0xD9168
 117 
 118 #define mmMME_CMDQ_CP_FENCE1_CNT                                     0xD916C
 119 
 120 #define mmMME_CMDQ_CP_FENCE2_CNT                                     0xD9170
 121 
 122 #define mmMME_CMDQ_CP_FENCE3_CNT                                     0xD9174
 123 
 124 #define mmMME_CMDQ_CP_STS                                            0xD9178
 125 
 126 #define mmMME_CMDQ_CP_CURRENT_INST_LO                                0xD917C
 127 
 128 #define mmMME_CMDQ_CP_CURRENT_INST_HI                                0xD9180
 129 
 130 #define mmMME_CMDQ_CP_BARRIER_CFG                                    0xD9184
 131 
 132 #define mmMME_CMDQ_CP_DBG_0                                          0xD9188
 133 
 134 #define mmMME_CMDQ_CQ_BUF_ADDR                                       0xD9308
 135 
 136 #define mmMME_CMDQ_CQ_BUF_RDATA                                      0xD930C
 137 
 138 #endif /* ASIC_REG_MME_CMDQ_REGS_H_ */