root/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_MME1_RTR_MASKS_H_
  14 #define ASIC_REG_MME1_RTR_MASKS_H_
  15 
  16 /*
  17  *****************************************
  18  *   MME1_RTR (Prototype: MME_RTR)
  19  *****************************************
  20  */
  21 
  22 /* MME1_RTR_HBW_RD_RQ_E_ARB */
  23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT                             0
  24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK                              0x7
  25 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_SHIFT                             8
  26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK                              0x700
  27 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_SHIFT                             16
  28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK                              0x70000
  29 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_SHIFT                             24
  30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK                              0x7000000
  31 
  32 /* MME1_RTR_HBW_RD_RQ_W_ARB */
  33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT                             0
  34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK                              0x7
  35 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_SHIFT                             8
  36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK                              0x700
  37 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_SHIFT                             16
  38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK                              0x70000
  39 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_SHIFT                             24
  40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK                              0x7000000
  41 
  42 /* MME1_RTR_HBW_RD_RQ_N_ARB */
  43 #define MME1_RTR_HBW_RD_RQ_N_ARB_W_SHIFT                             0
  44 #define MME1_RTR_HBW_RD_RQ_N_ARB_W_MASK                              0x7
  45 #define MME1_RTR_HBW_RD_RQ_N_ARB_E_SHIFT                             8
  46 #define MME1_RTR_HBW_RD_RQ_N_ARB_E_MASK                              0x700
  47 #define MME1_RTR_HBW_RD_RQ_N_ARB_S_SHIFT                             16
  48 #define MME1_RTR_HBW_RD_RQ_N_ARB_S_MASK                              0x70000
  49 #define MME1_RTR_HBW_RD_RQ_N_ARB_L_SHIFT                             24
  50 #define MME1_RTR_HBW_RD_RQ_N_ARB_L_MASK                              0x7000000
  51 
  52 /* MME1_RTR_HBW_RD_RQ_S_ARB */
  53 #define MME1_RTR_HBW_RD_RQ_S_ARB_W_SHIFT                             0
  54 #define MME1_RTR_HBW_RD_RQ_S_ARB_W_MASK                              0x7
  55 #define MME1_RTR_HBW_RD_RQ_S_ARB_E_SHIFT                             8
  56 #define MME1_RTR_HBW_RD_RQ_S_ARB_E_MASK                              0x700
  57 #define MME1_RTR_HBW_RD_RQ_S_ARB_N_SHIFT                             16
  58 #define MME1_RTR_HBW_RD_RQ_S_ARB_N_MASK                              0x70000
  59 #define MME1_RTR_HBW_RD_RQ_S_ARB_L_SHIFT                             24
  60 #define MME1_RTR_HBW_RD_RQ_S_ARB_L_MASK                              0x7000000
  61 
  62 /* MME1_RTR_HBW_RD_RQ_L_ARB */
  63 #define MME1_RTR_HBW_RD_RQ_L_ARB_W_SHIFT                             0
  64 #define MME1_RTR_HBW_RD_RQ_L_ARB_W_MASK                              0x7
  65 #define MME1_RTR_HBW_RD_RQ_L_ARB_E_SHIFT                             8
  66 #define MME1_RTR_HBW_RD_RQ_L_ARB_E_MASK                              0x700
  67 #define MME1_RTR_HBW_RD_RQ_L_ARB_S_SHIFT                             16
  68 #define MME1_RTR_HBW_RD_RQ_L_ARB_S_MASK                              0x70000
  69 #define MME1_RTR_HBW_RD_RQ_L_ARB_N_SHIFT                             24
  70 #define MME1_RTR_HBW_RD_RQ_L_ARB_N_MASK                              0x7000000
  71 
  72 /* MME1_RTR_HBW_E_ARB_MAX */
  73 #define MME1_RTR_HBW_E_ARB_MAX_CREDIT_SHIFT                          0
  74 #define MME1_RTR_HBW_E_ARB_MAX_CREDIT_MASK                           0x3F
  75 
  76 /* MME1_RTR_HBW_W_ARB_MAX */
  77 #define MME1_RTR_HBW_W_ARB_MAX_CREDIT_SHIFT                          0
  78 #define MME1_RTR_HBW_W_ARB_MAX_CREDIT_MASK                           0x3F
  79 
  80 /* MME1_RTR_HBW_N_ARB_MAX */
  81 #define MME1_RTR_HBW_N_ARB_MAX_CREDIT_SHIFT                          0
  82 #define MME1_RTR_HBW_N_ARB_MAX_CREDIT_MASK                           0x3F
  83 
  84 /* MME1_RTR_HBW_S_ARB_MAX */
  85 #define MME1_RTR_HBW_S_ARB_MAX_CREDIT_SHIFT                          0
  86 #define MME1_RTR_HBW_S_ARB_MAX_CREDIT_MASK                           0x3F
  87 
  88 /* MME1_RTR_HBW_L_ARB_MAX */
  89 #define MME1_RTR_HBW_L_ARB_MAX_CREDIT_SHIFT                          0
  90 #define MME1_RTR_HBW_L_ARB_MAX_CREDIT_MASK                           0x3F
  91 
  92 /* MME1_RTR_HBW_RD_RS_MAX_CREDIT */
  93 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_SHIFT                        0
  94 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_MASK                         0x3F
  95 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_SHIFT                        8
  96 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_MASK                         0x3F00
  97 
  98 /* MME1_RTR_HBW_WR_RQ_MAX_CREDIT */
  99 #define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_SHIFT                      0
 100 #define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_MASK                       0x3F
 101 
 102 /* MME1_RTR_HBW_RD_RQ_MAX_CREDIT */
 103 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_SHIFT                        0
 104 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_MASK                         0x3F
 105 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_SHIFT                        8
 106 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_MASK                         0x3F00
 107 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_SHIFT                       16
 108 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_MASK                        0x3F0000
 109 
 110 /* MME1_RTR_HBW_RD_RS_E_ARB */
 111 #define MME1_RTR_HBW_RD_RS_E_ARB_W_SHIFT                             0
 112 #define MME1_RTR_HBW_RD_RS_E_ARB_W_MASK                              0x7
 113 #define MME1_RTR_HBW_RD_RS_E_ARB_S_SHIFT                             8
 114 #define MME1_RTR_HBW_RD_RS_E_ARB_S_MASK                              0x700
 115 #define MME1_RTR_HBW_RD_RS_E_ARB_N_SHIFT                             16
 116 #define MME1_RTR_HBW_RD_RS_E_ARB_N_MASK                              0x70000
 117 #define MME1_RTR_HBW_RD_RS_E_ARB_L_SHIFT                             24
 118 #define MME1_RTR_HBW_RD_RS_E_ARB_L_MASK                              0x7000000
 119 
 120 /* MME1_RTR_HBW_RD_RS_W_ARB */
 121 #define MME1_RTR_HBW_RD_RS_W_ARB_E_SHIFT                             0
 122 #define MME1_RTR_HBW_RD_RS_W_ARB_E_MASK                              0x7
 123 #define MME1_RTR_HBW_RD_RS_W_ARB_S_SHIFT                             8
 124 #define MME1_RTR_HBW_RD_RS_W_ARB_S_MASK                              0x700
 125 #define MME1_RTR_HBW_RD_RS_W_ARB_N_SHIFT                             16
 126 #define MME1_RTR_HBW_RD_RS_W_ARB_N_MASK                              0x70000
 127 #define MME1_RTR_HBW_RD_RS_W_ARB_L_SHIFT                             24
 128 #define MME1_RTR_HBW_RD_RS_W_ARB_L_MASK                              0x7000000
 129 
 130 /* MME1_RTR_HBW_RD_RS_N_ARB */
 131 #define MME1_RTR_HBW_RD_RS_N_ARB_W_SHIFT                             0
 132 #define MME1_RTR_HBW_RD_RS_N_ARB_W_MASK                              0x7
 133 #define MME1_RTR_HBW_RD_RS_N_ARB_E_SHIFT                             8
 134 #define MME1_RTR_HBW_RD_RS_N_ARB_E_MASK                              0x700
 135 #define MME1_RTR_HBW_RD_RS_N_ARB_S_SHIFT                             16
 136 #define MME1_RTR_HBW_RD_RS_N_ARB_S_MASK                              0x70000
 137 #define MME1_RTR_HBW_RD_RS_N_ARB_L_SHIFT                             24
 138 #define MME1_RTR_HBW_RD_RS_N_ARB_L_MASK                              0x7000000
 139 
 140 /* MME1_RTR_HBW_RD_RS_S_ARB */
 141 #define MME1_RTR_HBW_RD_RS_S_ARB_W_SHIFT                             0
 142 #define MME1_RTR_HBW_RD_RS_S_ARB_W_MASK                              0x7
 143 #define MME1_RTR_HBW_RD_RS_S_ARB_E_SHIFT                             8
 144 #define MME1_RTR_HBW_RD_RS_S_ARB_E_MASK                              0x700
 145 #define MME1_RTR_HBW_RD_RS_S_ARB_N_SHIFT                             16
 146 #define MME1_RTR_HBW_RD_RS_S_ARB_N_MASK                              0x70000
 147 #define MME1_RTR_HBW_RD_RS_S_ARB_L_SHIFT                             24
 148 #define MME1_RTR_HBW_RD_RS_S_ARB_L_MASK                              0x7000000
 149 
 150 /* MME1_RTR_HBW_RD_RS_L_ARB */
 151 #define MME1_RTR_HBW_RD_RS_L_ARB_W_SHIFT                             0
 152 #define MME1_RTR_HBW_RD_RS_L_ARB_W_MASK                              0x7
 153 #define MME1_RTR_HBW_RD_RS_L_ARB_E_SHIFT                             8
 154 #define MME1_RTR_HBW_RD_RS_L_ARB_E_MASK                              0x700
 155 #define MME1_RTR_HBW_RD_RS_L_ARB_S_SHIFT                             16
 156 #define MME1_RTR_HBW_RD_RS_L_ARB_S_MASK                              0x70000
 157 #define MME1_RTR_HBW_RD_RS_L_ARB_N_SHIFT                             24
 158 #define MME1_RTR_HBW_RD_RS_L_ARB_N_MASK                              0x7000000
 159 
 160 /* MME1_RTR_HBW_WR_RQ_E_ARB */
 161 #define MME1_RTR_HBW_WR_RQ_E_ARB_W_SHIFT                             0
 162 #define MME1_RTR_HBW_WR_RQ_E_ARB_W_MASK                              0x7
 163 #define MME1_RTR_HBW_WR_RQ_E_ARB_S_SHIFT                             8
 164 #define MME1_RTR_HBW_WR_RQ_E_ARB_S_MASK                              0x700
 165 #define MME1_RTR_HBW_WR_RQ_E_ARB_N_SHIFT                             16
 166 #define MME1_RTR_HBW_WR_RQ_E_ARB_N_MASK                              0x70000
 167 #define MME1_RTR_HBW_WR_RQ_E_ARB_L_SHIFT                             24
 168 #define MME1_RTR_HBW_WR_RQ_E_ARB_L_MASK                              0x7000000
 169 
 170 /* MME1_RTR_HBW_WR_RQ_W_ARB */
 171 #define MME1_RTR_HBW_WR_RQ_W_ARB_E_SHIFT                             0
 172 #define MME1_RTR_HBW_WR_RQ_W_ARB_E_MASK                              0x7
 173 #define MME1_RTR_HBW_WR_RQ_W_ARB_S_SHIFT                             8
 174 #define MME1_RTR_HBW_WR_RQ_W_ARB_S_MASK                              0x700
 175 #define MME1_RTR_HBW_WR_RQ_W_ARB_N_SHIFT                             16
 176 #define MME1_RTR_HBW_WR_RQ_W_ARB_N_MASK                              0x70000
 177 #define MME1_RTR_HBW_WR_RQ_W_ARB_L_SHIFT                             24
 178 #define MME1_RTR_HBW_WR_RQ_W_ARB_L_MASK                              0x7000000
 179 
 180 /* MME1_RTR_HBW_WR_RQ_N_ARB */
 181 #define MME1_RTR_HBW_WR_RQ_N_ARB_W_SHIFT                             0
 182 #define MME1_RTR_HBW_WR_RQ_N_ARB_W_MASK                              0x7
 183 #define MME1_RTR_HBW_WR_RQ_N_ARB_E_SHIFT                             8
 184 #define MME1_RTR_HBW_WR_RQ_N_ARB_E_MASK                              0x700
 185 #define MME1_RTR_HBW_WR_RQ_N_ARB_S_SHIFT                             16
 186 #define MME1_RTR_HBW_WR_RQ_N_ARB_S_MASK                              0x70000
 187 #define MME1_RTR_HBW_WR_RQ_N_ARB_L_SHIFT                             24
 188 #define MME1_RTR_HBW_WR_RQ_N_ARB_L_MASK                              0x7000000
 189 
 190 /* MME1_RTR_HBW_WR_RQ_S_ARB */
 191 #define MME1_RTR_HBW_WR_RQ_S_ARB_W_SHIFT                             0
 192 #define MME1_RTR_HBW_WR_RQ_S_ARB_W_MASK                              0x7
 193 #define MME1_RTR_HBW_WR_RQ_S_ARB_E_SHIFT                             8
 194 #define MME1_RTR_HBW_WR_RQ_S_ARB_E_MASK                              0x700
 195 #define MME1_RTR_HBW_WR_RQ_S_ARB_N_SHIFT                             16
 196 #define MME1_RTR_HBW_WR_RQ_S_ARB_N_MASK                              0x70000
 197 #define MME1_RTR_HBW_WR_RQ_S_ARB_L_SHIFT                             24
 198 #define MME1_RTR_HBW_WR_RQ_S_ARB_L_MASK                              0x7000000
 199 
 200 /* MME1_RTR_HBW_WR_RQ_L_ARB */
 201 #define MME1_RTR_HBW_WR_RQ_L_ARB_W_SHIFT                             0
 202 #define MME1_RTR_HBW_WR_RQ_L_ARB_W_MASK                              0x7
 203 #define MME1_RTR_HBW_WR_RQ_L_ARB_E_SHIFT                             8
 204 #define MME1_RTR_HBW_WR_RQ_L_ARB_E_MASK                              0x700
 205 #define MME1_RTR_HBW_WR_RQ_L_ARB_S_SHIFT                             16
 206 #define MME1_RTR_HBW_WR_RQ_L_ARB_S_MASK                              0x70000
 207 #define MME1_RTR_HBW_WR_RQ_L_ARB_N_SHIFT                             24
 208 #define MME1_RTR_HBW_WR_RQ_L_ARB_N_MASK                              0x7000000
 209 
 210 /* MME1_RTR_HBW_WR_RS_E_ARB */
 211 #define MME1_RTR_HBW_WR_RS_E_ARB_W_SHIFT                             0
 212 #define MME1_RTR_HBW_WR_RS_E_ARB_W_MASK                              0x7
 213 #define MME1_RTR_HBW_WR_RS_E_ARB_S_SHIFT                             8
 214 #define MME1_RTR_HBW_WR_RS_E_ARB_S_MASK                              0x700
 215 #define MME1_RTR_HBW_WR_RS_E_ARB_N_SHIFT                             16
 216 #define MME1_RTR_HBW_WR_RS_E_ARB_N_MASK                              0x70000
 217 #define MME1_RTR_HBW_WR_RS_E_ARB_L_SHIFT                             24
 218 #define MME1_RTR_HBW_WR_RS_E_ARB_L_MASK                              0x7000000
 219 
 220 /* MME1_RTR_HBW_WR_RS_W_ARB */
 221 #define MME1_RTR_HBW_WR_RS_W_ARB_E_SHIFT                             0
 222 #define MME1_RTR_HBW_WR_RS_W_ARB_E_MASK                              0x7
 223 #define MME1_RTR_HBW_WR_RS_W_ARB_S_SHIFT                             8
 224 #define MME1_RTR_HBW_WR_RS_W_ARB_S_MASK                              0x700
 225 #define MME1_RTR_HBW_WR_RS_W_ARB_N_SHIFT                             16
 226 #define MME1_RTR_HBW_WR_RS_W_ARB_N_MASK                              0x70000
 227 #define MME1_RTR_HBW_WR_RS_W_ARB_L_SHIFT                             24
 228 #define MME1_RTR_HBW_WR_RS_W_ARB_L_MASK                              0x7000000
 229 
 230 /* MME1_RTR_HBW_WR_RS_N_ARB */
 231 #define MME1_RTR_HBW_WR_RS_N_ARB_W_SHIFT                             0
 232 #define MME1_RTR_HBW_WR_RS_N_ARB_W_MASK                              0x7
 233 #define MME1_RTR_HBW_WR_RS_N_ARB_E_SHIFT                             8
 234 #define MME1_RTR_HBW_WR_RS_N_ARB_E_MASK                              0x700
 235 #define MME1_RTR_HBW_WR_RS_N_ARB_S_SHIFT                             16
 236 #define MME1_RTR_HBW_WR_RS_N_ARB_S_MASK                              0x70000
 237 #define MME1_RTR_HBW_WR_RS_N_ARB_L_SHIFT                             24
 238 #define MME1_RTR_HBW_WR_RS_N_ARB_L_MASK                              0x7000000
 239 
 240 /* MME1_RTR_HBW_WR_RS_S_ARB */
 241 #define MME1_RTR_HBW_WR_RS_S_ARB_W_SHIFT                             0
 242 #define MME1_RTR_HBW_WR_RS_S_ARB_W_MASK                              0x7
 243 #define MME1_RTR_HBW_WR_RS_S_ARB_E_SHIFT                             8
 244 #define MME1_RTR_HBW_WR_RS_S_ARB_E_MASK                              0x700
 245 #define MME1_RTR_HBW_WR_RS_S_ARB_N_SHIFT                             16
 246 #define MME1_RTR_HBW_WR_RS_S_ARB_N_MASK                              0x70000
 247 #define MME1_RTR_HBW_WR_RS_S_ARB_L_SHIFT                             24
 248 #define MME1_RTR_HBW_WR_RS_S_ARB_L_MASK                              0x7000000
 249 
 250 /* MME1_RTR_HBW_WR_RS_L_ARB */
 251 #define MME1_RTR_HBW_WR_RS_L_ARB_W_SHIFT                             0
 252 #define MME1_RTR_HBW_WR_RS_L_ARB_W_MASK                              0x7
 253 #define MME1_RTR_HBW_WR_RS_L_ARB_E_SHIFT                             8
 254 #define MME1_RTR_HBW_WR_RS_L_ARB_E_MASK                              0x700
 255 #define MME1_RTR_HBW_WR_RS_L_ARB_S_SHIFT                             16
 256 #define MME1_RTR_HBW_WR_RS_L_ARB_S_MASK                              0x70000
 257 #define MME1_RTR_HBW_WR_RS_L_ARB_N_SHIFT                             24
 258 #define MME1_RTR_HBW_WR_RS_L_ARB_N_MASK                              0x7000000
 259 
 260 /* MME1_RTR_LBW_RD_RQ_E_ARB */
 261 #define MME1_RTR_LBW_RD_RQ_E_ARB_W_SHIFT                             0
 262 #define MME1_RTR_LBW_RD_RQ_E_ARB_W_MASK                              0x7
 263 #define MME1_RTR_LBW_RD_RQ_E_ARB_S_SHIFT                             8
 264 #define MME1_RTR_LBW_RD_RQ_E_ARB_S_MASK                              0x700
 265 #define MME1_RTR_LBW_RD_RQ_E_ARB_N_SHIFT                             16
 266 #define MME1_RTR_LBW_RD_RQ_E_ARB_N_MASK                              0x70000
 267 #define MME1_RTR_LBW_RD_RQ_E_ARB_L_SHIFT                             24
 268 #define MME1_RTR_LBW_RD_RQ_E_ARB_L_MASK                              0x7000000
 269 
 270 /* MME1_RTR_LBW_RD_RQ_W_ARB */
 271 #define MME1_RTR_LBW_RD_RQ_W_ARB_E_SHIFT                             0
 272 #define MME1_RTR_LBW_RD_RQ_W_ARB_E_MASK                              0x7
 273 #define MME1_RTR_LBW_RD_RQ_W_ARB_S_SHIFT                             8
 274 #define MME1_RTR_LBW_RD_RQ_W_ARB_S_MASK                              0x700
 275 #define MME1_RTR_LBW_RD_RQ_W_ARB_N_SHIFT                             16
 276 #define MME1_RTR_LBW_RD_RQ_W_ARB_N_MASK                              0x70000
 277 #define MME1_RTR_LBW_RD_RQ_W_ARB_L_SHIFT                             24
 278 #define MME1_RTR_LBW_RD_RQ_W_ARB_L_MASK                              0x7000000
 279 
 280 /* MME1_RTR_LBW_RD_RQ_N_ARB */
 281 #define MME1_RTR_LBW_RD_RQ_N_ARB_W_SHIFT                             0
 282 #define MME1_RTR_LBW_RD_RQ_N_ARB_W_MASK                              0x7
 283 #define MME1_RTR_LBW_RD_RQ_N_ARB_E_SHIFT                             8
 284 #define MME1_RTR_LBW_RD_RQ_N_ARB_E_MASK                              0x700
 285 #define MME1_RTR_LBW_RD_RQ_N_ARB_S_SHIFT                             16
 286 #define MME1_RTR_LBW_RD_RQ_N_ARB_S_MASK                              0x70000
 287 #define MME1_RTR_LBW_RD_RQ_N_ARB_L_SHIFT                             24
 288 #define MME1_RTR_LBW_RD_RQ_N_ARB_L_MASK                              0x7000000
 289 
 290 /* MME1_RTR_LBW_RD_RQ_S_ARB */
 291 #define MME1_RTR_LBW_RD_RQ_S_ARB_W_SHIFT                             0
 292 #define MME1_RTR_LBW_RD_RQ_S_ARB_W_MASK                              0x7
 293 #define MME1_RTR_LBW_RD_RQ_S_ARB_E_SHIFT                             8
 294 #define MME1_RTR_LBW_RD_RQ_S_ARB_E_MASK                              0x700
 295 #define MME1_RTR_LBW_RD_RQ_S_ARB_N_SHIFT                             16
 296 #define MME1_RTR_LBW_RD_RQ_S_ARB_N_MASK                              0x70000
 297 #define MME1_RTR_LBW_RD_RQ_S_ARB_L_SHIFT                             24
 298 #define MME1_RTR_LBW_RD_RQ_S_ARB_L_MASK                              0x7000000
 299 
 300 /* MME1_RTR_LBW_RD_RQ_L_ARB */
 301 #define MME1_RTR_LBW_RD_RQ_L_ARB_W_SHIFT                             0
 302 #define MME1_RTR_LBW_RD_RQ_L_ARB_W_MASK                              0x7
 303 #define MME1_RTR_LBW_RD_RQ_L_ARB_E_SHIFT                             8
 304 #define MME1_RTR_LBW_RD_RQ_L_ARB_E_MASK                              0x700
 305 #define MME1_RTR_LBW_RD_RQ_L_ARB_S_SHIFT                             16
 306 #define MME1_RTR_LBW_RD_RQ_L_ARB_S_MASK                              0x70000
 307 #define MME1_RTR_LBW_RD_RQ_L_ARB_N_SHIFT                             24
 308 #define MME1_RTR_LBW_RD_RQ_L_ARB_N_MASK                              0x7000000
 309 
 310 /* MME1_RTR_LBW_E_ARB_MAX */
 311 #define MME1_RTR_LBW_E_ARB_MAX_CREDIT_SHIFT                          0
 312 #define MME1_RTR_LBW_E_ARB_MAX_CREDIT_MASK                           0x3F
 313 
 314 /* MME1_RTR_LBW_W_ARB_MAX */
 315 #define MME1_RTR_LBW_W_ARB_MAX_CREDIT_SHIFT                          0
 316 #define MME1_RTR_LBW_W_ARB_MAX_CREDIT_MASK                           0x3F
 317 
 318 /* MME1_RTR_LBW_N_ARB_MAX */
 319 #define MME1_RTR_LBW_N_ARB_MAX_CREDIT_SHIFT                          0
 320 #define MME1_RTR_LBW_N_ARB_MAX_CREDIT_MASK                           0x3F
 321 
 322 /* MME1_RTR_LBW_S_ARB_MAX */
 323 #define MME1_RTR_LBW_S_ARB_MAX_CREDIT_SHIFT                          0
 324 #define MME1_RTR_LBW_S_ARB_MAX_CREDIT_MASK                           0x3F
 325 
 326 /* MME1_RTR_LBW_L_ARB_MAX */
 327 #define MME1_RTR_LBW_L_ARB_MAX_CREDIT_SHIFT                          0
 328 #define MME1_RTR_LBW_L_ARB_MAX_CREDIT_MASK                           0x3F
 329 
 330 /* MME1_RTR_LBW_SRAM_MAX_CREDIT */
 331 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_SHIFT                      0
 332 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_MASK                       0x3F
 333 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_SHIFT                       8
 334 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_MASK                        0x3F00
 335 
 336 /* MME1_RTR_LBW_RD_RS_E_ARB */
 337 #define MME1_RTR_LBW_RD_RS_E_ARB_W_SHIFT                             0
 338 #define MME1_RTR_LBW_RD_RS_E_ARB_W_MASK                              0x7
 339 #define MME1_RTR_LBW_RD_RS_E_ARB_S_SHIFT                             8
 340 #define MME1_RTR_LBW_RD_RS_E_ARB_S_MASK                              0x700
 341 #define MME1_RTR_LBW_RD_RS_E_ARB_N_SHIFT                             16
 342 #define MME1_RTR_LBW_RD_RS_E_ARB_N_MASK                              0x70000
 343 #define MME1_RTR_LBW_RD_RS_E_ARB_L_SHIFT                             24
 344 #define MME1_RTR_LBW_RD_RS_E_ARB_L_MASK                              0x7000000
 345 
 346 /* MME1_RTR_LBW_RD_RS_W_ARB */
 347 #define MME1_RTR_LBW_RD_RS_W_ARB_E_SHIFT                             0
 348 #define MME1_RTR_LBW_RD_RS_W_ARB_E_MASK                              0x7
 349 #define MME1_RTR_LBW_RD_RS_W_ARB_S_SHIFT                             8
 350 #define MME1_RTR_LBW_RD_RS_W_ARB_S_MASK                              0x700
 351 #define MME1_RTR_LBW_RD_RS_W_ARB_N_SHIFT                             16
 352 #define MME1_RTR_LBW_RD_RS_W_ARB_N_MASK                              0x70000
 353 #define MME1_RTR_LBW_RD_RS_W_ARB_L_SHIFT                             24
 354 #define MME1_RTR_LBW_RD_RS_W_ARB_L_MASK                              0x7000000
 355 
 356 /* MME1_RTR_LBW_RD_RS_N_ARB */
 357 #define MME1_RTR_LBW_RD_RS_N_ARB_W_SHIFT                             0
 358 #define MME1_RTR_LBW_RD_RS_N_ARB_W_MASK                              0x7
 359 #define MME1_RTR_LBW_RD_RS_N_ARB_E_SHIFT                             8
 360 #define MME1_RTR_LBW_RD_RS_N_ARB_E_MASK                              0x700
 361 #define MME1_RTR_LBW_RD_RS_N_ARB_S_SHIFT                             16
 362 #define MME1_RTR_LBW_RD_RS_N_ARB_S_MASK                              0x70000
 363 #define MME1_RTR_LBW_RD_RS_N_ARB_L_SHIFT                             24
 364 #define MME1_RTR_LBW_RD_RS_N_ARB_L_MASK                              0x7000000
 365 
 366 /* MME1_RTR_LBW_RD_RS_S_ARB */
 367 #define MME1_RTR_LBW_RD_RS_S_ARB_W_SHIFT                             0
 368 #define MME1_RTR_LBW_RD_RS_S_ARB_W_MASK                              0x7
 369 #define MME1_RTR_LBW_RD_RS_S_ARB_E_SHIFT                             8
 370 #define MME1_RTR_LBW_RD_RS_S_ARB_E_MASK                              0x700
 371 #define MME1_RTR_LBW_RD_RS_S_ARB_N_SHIFT                             16
 372 #define MME1_RTR_LBW_RD_RS_S_ARB_N_MASK                              0x70000
 373 #define MME1_RTR_LBW_RD_RS_S_ARB_L_SHIFT                             24
 374 #define MME1_RTR_LBW_RD_RS_S_ARB_L_MASK                              0x7000000
 375 
 376 /* MME1_RTR_LBW_RD_RS_L_ARB */
 377 #define MME1_RTR_LBW_RD_RS_L_ARB_W_SHIFT                             0
 378 #define MME1_RTR_LBW_RD_RS_L_ARB_W_MASK                              0x7
 379 #define MME1_RTR_LBW_RD_RS_L_ARB_E_SHIFT                             8
 380 #define MME1_RTR_LBW_RD_RS_L_ARB_E_MASK                              0x700
 381 #define MME1_RTR_LBW_RD_RS_L_ARB_S_SHIFT                             16
 382 #define MME1_RTR_LBW_RD_RS_L_ARB_S_MASK                              0x70000
 383 #define MME1_RTR_LBW_RD_RS_L_ARB_N_SHIFT                             24
 384 #define MME1_RTR_LBW_RD_RS_L_ARB_N_MASK                              0x7000000
 385 
 386 /* MME1_RTR_LBW_WR_RQ_E_ARB */
 387 #define MME1_RTR_LBW_WR_RQ_E_ARB_W_SHIFT                             0
 388 #define MME1_RTR_LBW_WR_RQ_E_ARB_W_MASK                              0x7
 389 #define MME1_RTR_LBW_WR_RQ_E_ARB_S_SHIFT                             8
 390 #define MME1_RTR_LBW_WR_RQ_E_ARB_S_MASK                              0x700
 391 #define MME1_RTR_LBW_WR_RQ_E_ARB_N_SHIFT                             16
 392 #define MME1_RTR_LBW_WR_RQ_E_ARB_N_MASK                              0x70000
 393 #define MME1_RTR_LBW_WR_RQ_E_ARB_L_SHIFT                             24
 394 #define MME1_RTR_LBW_WR_RQ_E_ARB_L_MASK                              0x7000000
 395 
 396 /* MME1_RTR_LBW_WR_RQ_W_ARB */
 397 #define MME1_RTR_LBW_WR_RQ_W_ARB_E_SHIFT                             0
 398 #define MME1_RTR_LBW_WR_RQ_W_ARB_E_MASK                              0x7
 399 #define MME1_RTR_LBW_WR_RQ_W_ARB_S_SHIFT                             8
 400 #define MME1_RTR_LBW_WR_RQ_W_ARB_S_MASK                              0x700
 401 #define MME1_RTR_LBW_WR_RQ_W_ARB_N_SHIFT                             16
 402 #define MME1_RTR_LBW_WR_RQ_W_ARB_N_MASK                              0x70000
 403 #define MME1_RTR_LBW_WR_RQ_W_ARB_L_SHIFT                             24
 404 #define MME1_RTR_LBW_WR_RQ_W_ARB_L_MASK                              0x7000000
 405 
 406 /* MME1_RTR_LBW_WR_RQ_N_ARB */
 407 #define MME1_RTR_LBW_WR_RQ_N_ARB_W_SHIFT                             0
 408 #define MME1_RTR_LBW_WR_RQ_N_ARB_W_MASK                              0x7
 409 #define MME1_RTR_LBW_WR_RQ_N_ARB_E_SHIFT                             8
 410 #define MME1_RTR_LBW_WR_RQ_N_ARB_E_MASK                              0x700
 411 #define MME1_RTR_LBW_WR_RQ_N_ARB_S_SHIFT                             16
 412 #define MME1_RTR_LBW_WR_RQ_N_ARB_S_MASK                              0x70000
 413 #define MME1_RTR_LBW_WR_RQ_N_ARB_L_SHIFT                             24
 414 #define MME1_RTR_LBW_WR_RQ_N_ARB_L_MASK                              0x7000000
 415 
 416 /* MME1_RTR_LBW_WR_RQ_S_ARB */
 417 #define MME1_RTR_LBW_WR_RQ_S_ARB_W_SHIFT                             0
 418 #define MME1_RTR_LBW_WR_RQ_S_ARB_W_MASK                              0x7
 419 #define MME1_RTR_LBW_WR_RQ_S_ARB_E_SHIFT                             8
 420 #define MME1_RTR_LBW_WR_RQ_S_ARB_E_MASK                              0x700
 421 #define MME1_RTR_LBW_WR_RQ_S_ARB_N_SHIFT                             16
 422 #define MME1_RTR_LBW_WR_RQ_S_ARB_N_MASK                              0x70000
 423 #define MME1_RTR_LBW_WR_RQ_S_ARB_L_SHIFT                             24
 424 #define MME1_RTR_LBW_WR_RQ_S_ARB_L_MASK                              0x7000000
 425 
 426 /* MME1_RTR_LBW_WR_RQ_L_ARB */
 427 #define MME1_RTR_LBW_WR_RQ_L_ARB_W_SHIFT                             0
 428 #define MME1_RTR_LBW_WR_RQ_L_ARB_W_MASK                              0x7
 429 #define MME1_RTR_LBW_WR_RQ_L_ARB_E_SHIFT                             8
 430 #define MME1_RTR_LBW_WR_RQ_L_ARB_E_MASK                              0x700
 431 #define MME1_RTR_LBW_WR_RQ_L_ARB_S_SHIFT                             16
 432 #define MME1_RTR_LBW_WR_RQ_L_ARB_S_MASK                              0x70000
 433 #define MME1_RTR_LBW_WR_RQ_L_ARB_N_SHIFT                             24
 434 #define MME1_RTR_LBW_WR_RQ_L_ARB_N_MASK                              0x7000000
 435 
 436 /* MME1_RTR_LBW_WR_RS_E_ARB */
 437 #define MME1_RTR_LBW_WR_RS_E_ARB_W_SHIFT                             0
 438 #define MME1_RTR_LBW_WR_RS_E_ARB_W_MASK                              0x7
 439 #define MME1_RTR_LBW_WR_RS_E_ARB_S_SHIFT                             8
 440 #define MME1_RTR_LBW_WR_RS_E_ARB_S_MASK                              0x700
 441 #define MME1_RTR_LBW_WR_RS_E_ARB_N_SHIFT                             16
 442 #define MME1_RTR_LBW_WR_RS_E_ARB_N_MASK                              0x70000
 443 #define MME1_RTR_LBW_WR_RS_E_ARB_L_SHIFT                             24
 444 #define MME1_RTR_LBW_WR_RS_E_ARB_L_MASK                              0x7000000
 445 
 446 /* MME1_RTR_LBW_WR_RS_W_ARB */
 447 #define MME1_RTR_LBW_WR_RS_W_ARB_E_SHIFT                             0
 448 #define MME1_RTR_LBW_WR_RS_W_ARB_E_MASK                              0x7
 449 #define MME1_RTR_LBW_WR_RS_W_ARB_S_SHIFT                             8
 450 #define MME1_RTR_LBW_WR_RS_W_ARB_S_MASK                              0x700
 451 #define MME1_RTR_LBW_WR_RS_W_ARB_N_SHIFT                             16
 452 #define MME1_RTR_LBW_WR_RS_W_ARB_N_MASK                              0x70000
 453 #define MME1_RTR_LBW_WR_RS_W_ARB_L_SHIFT                             24
 454 #define MME1_RTR_LBW_WR_RS_W_ARB_L_MASK                              0x7000000
 455 
 456 /* MME1_RTR_LBW_WR_RS_N_ARB */
 457 #define MME1_RTR_LBW_WR_RS_N_ARB_W_SHIFT                             0
 458 #define MME1_RTR_LBW_WR_RS_N_ARB_W_MASK                              0x7
 459 #define MME1_RTR_LBW_WR_RS_N_ARB_E_SHIFT                             8
 460 #define MME1_RTR_LBW_WR_RS_N_ARB_E_MASK                              0x700
 461 #define MME1_RTR_LBW_WR_RS_N_ARB_S_SHIFT                             16
 462 #define MME1_RTR_LBW_WR_RS_N_ARB_S_MASK                              0x70000
 463 #define MME1_RTR_LBW_WR_RS_N_ARB_L_SHIFT                             24
 464 #define MME1_RTR_LBW_WR_RS_N_ARB_L_MASK                              0x7000000
 465 
 466 /* MME1_RTR_LBW_WR_RS_S_ARB */
 467 #define MME1_RTR_LBW_WR_RS_S_ARB_W_SHIFT                             0
 468 #define MME1_RTR_LBW_WR_RS_S_ARB_W_MASK                              0x7
 469 #define MME1_RTR_LBW_WR_RS_S_ARB_E_SHIFT                             8
 470 #define MME1_RTR_LBW_WR_RS_S_ARB_E_MASK                              0x700
 471 #define MME1_RTR_LBW_WR_RS_S_ARB_N_SHIFT                             16
 472 #define MME1_RTR_LBW_WR_RS_S_ARB_N_MASK                              0x70000
 473 #define MME1_RTR_LBW_WR_RS_S_ARB_L_SHIFT                             24
 474 #define MME1_RTR_LBW_WR_RS_S_ARB_L_MASK                              0x7000000
 475 
 476 /* MME1_RTR_LBW_WR_RS_L_ARB */
 477 #define MME1_RTR_LBW_WR_RS_L_ARB_W_SHIFT                             0
 478 #define MME1_RTR_LBW_WR_RS_L_ARB_W_MASK                              0x7
 479 #define MME1_RTR_LBW_WR_RS_L_ARB_E_SHIFT                             8
 480 #define MME1_RTR_LBW_WR_RS_L_ARB_E_MASK                              0x700
 481 #define MME1_RTR_LBW_WR_RS_L_ARB_S_SHIFT                             16
 482 #define MME1_RTR_LBW_WR_RS_L_ARB_S_MASK                              0x70000
 483 #define MME1_RTR_LBW_WR_RS_L_ARB_N_SHIFT                             24
 484 #define MME1_RTR_LBW_WR_RS_L_ARB_N_MASK                              0x7000000
 485 
 486 /* MME1_RTR_DBG_E_ARB */
 487 #define MME1_RTR_DBG_E_ARB_W_SHIFT                                   0
 488 #define MME1_RTR_DBG_E_ARB_W_MASK                                    0x7
 489 #define MME1_RTR_DBG_E_ARB_S_SHIFT                                   8
 490 #define MME1_RTR_DBG_E_ARB_S_MASK                                    0x700
 491 #define MME1_RTR_DBG_E_ARB_N_SHIFT                                   16
 492 #define MME1_RTR_DBG_E_ARB_N_MASK                                    0x70000
 493 #define MME1_RTR_DBG_E_ARB_L_SHIFT                                   24
 494 #define MME1_RTR_DBG_E_ARB_L_MASK                                    0x7000000
 495 
 496 /* MME1_RTR_DBG_W_ARB */
 497 #define MME1_RTR_DBG_W_ARB_E_SHIFT                                   0
 498 #define MME1_RTR_DBG_W_ARB_E_MASK                                    0x7
 499 #define MME1_RTR_DBG_W_ARB_S_SHIFT                                   8
 500 #define MME1_RTR_DBG_W_ARB_S_MASK                                    0x700
 501 #define MME1_RTR_DBG_W_ARB_N_SHIFT                                   16
 502 #define MME1_RTR_DBG_W_ARB_N_MASK                                    0x70000
 503 #define MME1_RTR_DBG_W_ARB_L_SHIFT                                   24
 504 #define MME1_RTR_DBG_W_ARB_L_MASK                                    0x7000000
 505 
 506 /* MME1_RTR_DBG_N_ARB */
 507 #define MME1_RTR_DBG_N_ARB_W_SHIFT                                   0
 508 #define MME1_RTR_DBG_N_ARB_W_MASK                                    0x7
 509 #define MME1_RTR_DBG_N_ARB_E_SHIFT                                   8
 510 #define MME1_RTR_DBG_N_ARB_E_MASK                                    0x700
 511 #define MME1_RTR_DBG_N_ARB_S_SHIFT                                   16
 512 #define MME1_RTR_DBG_N_ARB_S_MASK                                    0x70000
 513 #define MME1_RTR_DBG_N_ARB_L_SHIFT                                   24
 514 #define MME1_RTR_DBG_N_ARB_L_MASK                                    0x7000000
 515 
 516 /* MME1_RTR_DBG_S_ARB */
 517 #define MME1_RTR_DBG_S_ARB_W_SHIFT                                   0
 518 #define MME1_RTR_DBG_S_ARB_W_MASK                                    0x7
 519 #define MME1_RTR_DBG_S_ARB_E_SHIFT                                   8
 520 #define MME1_RTR_DBG_S_ARB_E_MASK                                    0x700
 521 #define MME1_RTR_DBG_S_ARB_N_SHIFT                                   16
 522 #define MME1_RTR_DBG_S_ARB_N_MASK                                    0x70000
 523 #define MME1_RTR_DBG_S_ARB_L_SHIFT                                   24
 524 #define MME1_RTR_DBG_S_ARB_L_MASK                                    0x7000000
 525 
 526 /* MME1_RTR_DBG_L_ARB */
 527 #define MME1_RTR_DBG_L_ARB_W_SHIFT                                   0
 528 #define MME1_RTR_DBG_L_ARB_W_MASK                                    0x7
 529 #define MME1_RTR_DBG_L_ARB_E_SHIFT                                   8
 530 #define MME1_RTR_DBG_L_ARB_E_MASK                                    0x700
 531 #define MME1_RTR_DBG_L_ARB_S_SHIFT                                   16
 532 #define MME1_RTR_DBG_L_ARB_S_MASK                                    0x70000
 533 #define MME1_RTR_DBG_L_ARB_N_SHIFT                                   24
 534 #define MME1_RTR_DBG_L_ARB_N_MASK                                    0x7000000
 535 
 536 /* MME1_RTR_DBG_E_ARB_MAX */
 537 #define MME1_RTR_DBG_E_ARB_MAX_CREDIT_SHIFT                          0
 538 #define MME1_RTR_DBG_E_ARB_MAX_CREDIT_MASK                           0x3F
 539 
 540 /* MME1_RTR_DBG_W_ARB_MAX */
 541 #define MME1_RTR_DBG_W_ARB_MAX_CREDIT_SHIFT                          0
 542 #define MME1_RTR_DBG_W_ARB_MAX_CREDIT_MASK                           0x3F
 543 
 544 /* MME1_RTR_DBG_N_ARB_MAX */
 545 #define MME1_RTR_DBG_N_ARB_MAX_CREDIT_SHIFT                          0
 546 #define MME1_RTR_DBG_N_ARB_MAX_CREDIT_MASK                           0x3F
 547 
 548 /* MME1_RTR_DBG_S_ARB_MAX */
 549 #define MME1_RTR_DBG_S_ARB_MAX_CREDIT_SHIFT                          0
 550 #define MME1_RTR_DBG_S_ARB_MAX_CREDIT_MASK                           0x3F
 551 
 552 /* MME1_RTR_DBG_L_ARB_MAX */
 553 #define MME1_RTR_DBG_L_ARB_MAX_CREDIT_SHIFT                          0
 554 #define MME1_RTR_DBG_L_ARB_MAX_CREDIT_MASK                           0x3F
 555 
 556 /* MME1_RTR_SPLIT_COEF */
 557 #define MME1_RTR_SPLIT_COEF_VAL_SHIFT                                0
 558 #define MME1_RTR_SPLIT_COEF_VAL_MASK                                 0xFFFF
 559 
 560 /* MME1_RTR_SPLIT_CFG */
 561 #define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT                     0
 562 #define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK                      0x1
 563 #define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT                  1
 564 #define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK                   0x2
 565 #define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_SHIFT                        2
 566 #define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_MASK                         0xC
 567 #define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT                      4
 568 #define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK                       0x10
 569 #define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT                      5
 570 #define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK                       0x20
 571 #define MME1_RTR_SPLIT_CFG_B2B_OPT_SHIFT                             6
 572 #define MME1_RTR_SPLIT_CFG_B2B_OPT_MASK                              0x1C0
 573 
 574 /* MME1_RTR_SPLIT_RD_SAT */
 575 #define MME1_RTR_SPLIT_RD_SAT_VAL_SHIFT                              0
 576 #define MME1_RTR_SPLIT_RD_SAT_VAL_MASK                               0xFFFF
 577 
 578 /* MME1_RTR_SPLIT_RD_RST_TOKEN */
 579 #define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT                        0
 580 #define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_MASK                         0xFFFF
 581 
 582 /* MME1_RTR_SPLIT_RD_TIMEOUT */
 583 #define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_SHIFT                          0
 584 #define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_MASK                           0xFFFFFFFF
 585 
 586 /* MME1_RTR_SPLIT_WR_SAT */
 587 #define MME1_RTR_SPLIT_WR_SAT_VAL_SHIFT                              0
 588 #define MME1_RTR_SPLIT_WR_SAT_VAL_MASK                               0xFFFF
 589 
 590 /* MME1_RTR_WPLIT_WR_TST_TOLEN */
 591 #define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT                        0
 592 #define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_MASK                         0xFFFF
 593 
 594 /* MME1_RTR_SPLIT_WR_TIMEOUT */
 595 #define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_SHIFT                          0
 596 #define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_MASK                           0xFFFFFFFF
 597 
 598 /* MME1_RTR_HBW_RANGE_HIT */
 599 #define MME1_RTR_HBW_RANGE_HIT_IND_SHIFT                             0
 600 #define MME1_RTR_HBW_RANGE_HIT_IND_MASK                              0xFF
 601 
 602 /* MME1_RTR_HBW_RANGE_MASK_L */
 603 #define MME1_RTR_HBW_RANGE_MASK_L_VAL_SHIFT                          0
 604 #define MME1_RTR_HBW_RANGE_MASK_L_VAL_MASK                           0xFFFFFFFF
 605 
 606 /* MME1_RTR_HBW_RANGE_MASK_H */
 607 #define MME1_RTR_HBW_RANGE_MASK_H_VAL_SHIFT                          0
 608 #define MME1_RTR_HBW_RANGE_MASK_H_VAL_MASK                           0x3FFFF
 609 
 610 /* MME1_RTR_HBW_RANGE_BASE_L */
 611 #define MME1_RTR_HBW_RANGE_BASE_L_VAL_SHIFT                          0
 612 #define MME1_RTR_HBW_RANGE_BASE_L_VAL_MASK                           0xFFFFFFFF
 613 
 614 /* MME1_RTR_HBW_RANGE_BASE_H */
 615 #define MME1_RTR_HBW_RANGE_BASE_H_VAL_SHIFT                          0
 616 #define MME1_RTR_HBW_RANGE_BASE_H_VAL_MASK                           0x3FFFF
 617 
 618 /* MME1_RTR_LBW_RANGE_HIT */
 619 #define MME1_RTR_LBW_RANGE_HIT_IND_SHIFT                             0
 620 #define MME1_RTR_LBW_RANGE_HIT_IND_MASK                              0xFFFF
 621 
 622 /* MME1_RTR_LBW_RANGE_MASK */
 623 #define MME1_RTR_LBW_RANGE_MASK_VAL_SHIFT                            0
 624 #define MME1_RTR_LBW_RANGE_MASK_VAL_MASK                             0x3FFFFFF
 625 
 626 /* MME1_RTR_LBW_RANGE_BASE */
 627 #define MME1_RTR_LBW_RANGE_BASE_VAL_SHIFT                            0
 628 #define MME1_RTR_LBW_RANGE_BASE_VAL_MASK                             0x3FFFFFF
 629 
 630 /* MME1_RTR_RGLTR */
 631 #define MME1_RTR_RGLTR_WR_EN_SHIFT                                   0
 632 #define MME1_RTR_RGLTR_WR_EN_MASK                                    0x1
 633 #define MME1_RTR_RGLTR_RD_EN_SHIFT                                   4
 634 #define MME1_RTR_RGLTR_RD_EN_MASK                                    0x10
 635 
 636 /* MME1_RTR_RGLTR_WR_RESULT */
 637 #define MME1_RTR_RGLTR_WR_RESULT_VAL_SHIFT                           0
 638 #define MME1_RTR_RGLTR_WR_RESULT_VAL_MASK                            0xFF
 639 
 640 /* MME1_RTR_RGLTR_RD_RESULT */
 641 #define MME1_RTR_RGLTR_RD_RESULT_VAL_SHIFT                           0
 642 #define MME1_RTR_RGLTR_RD_RESULT_VAL_MASK                            0xFF
 643 
 644 /* MME1_RTR_SCRAMB_EN */
 645 #define MME1_RTR_SCRAMB_EN_VAL_SHIFT                                 0
 646 #define MME1_RTR_SCRAMB_EN_VAL_MASK                                  0x1
 647 
 648 /* MME1_RTR_NON_LIN_SCRAMB */
 649 #define MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT                             0
 650 #define MME1_RTR_NON_LIN_SCRAMB_EN_MASK                              0x1
 651 
 652 #endif /* ASIC_REG_MME1_RTR_MASKS_H_ */