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13 #ifndef ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_
14 #define ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_
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22 #define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_E_ARB 0x211100
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24 #define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_W_ARB 0x211104
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26 #define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB 0x211110
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28 #define mmSRAM_Y0_X4_RTR_HBW_E_ARB_MAX 0x211120
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30 #define mmSRAM_Y0_X4_RTR_HBW_W_ARB_MAX 0x211124
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32 #define mmSRAM_Y0_X4_RTR_HBW_L_ARB_MAX 0x211130
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34 #define mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB 0x211140
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36 #define mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB 0x211144
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38 #define mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB 0x211148
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40 #define mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB 0x211160
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42 #define mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB 0x211164
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44 #define mmSRAM_Y0_X4_RTR_HBW_WR_RS_L_ARB 0x211168
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46 #define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_E_ARB 0x211200
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48 #define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_W_ARB 0x211204
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50 #define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_L_ARB 0x211210
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52 #define mmSRAM_Y0_X4_RTR_LBW_E_ARB_MAX 0x211220
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54 #define mmSRAM_Y0_X4_RTR_LBW_W_ARB_MAX 0x211224
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56 #define mmSRAM_Y0_X4_RTR_LBW_L_ARB_MAX 0x211230
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58 #define mmSRAM_Y0_X4_RTR_LBW_DATA_E_ARB 0x211240
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60 #define mmSRAM_Y0_X4_RTR_LBW_DATA_W_ARB 0x211244
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62 #define mmSRAM_Y0_X4_RTR_LBW_DATA_L_ARB 0x211248
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64 #define mmSRAM_Y0_X4_RTR_LBW_WR_RS_E_ARB 0x211260
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66 #define mmSRAM_Y0_X4_RTR_LBW_WR_RS_W_ARB 0x211264
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68 #define mmSRAM_Y0_X4_RTR_LBW_WR_RS_L_ARB 0x211268
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70 #define mmSRAM_Y0_X4_RTR_DBG_E_ARB 0x211300
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72 #define mmSRAM_Y0_X4_RTR_DBG_W_ARB 0x211304
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74 #define mmSRAM_Y0_X4_RTR_DBG_L_ARB 0x211310
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76 #define mmSRAM_Y0_X4_RTR_DBG_E_ARB_MAX 0x211320
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78 #define mmSRAM_Y0_X4_RTR_DBG_W_ARB_MAX 0x211324
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80 #define mmSRAM_Y0_X4_RTR_DBG_L_ARB_MAX 0x211330
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82 #endif