drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg

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   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_TPC0_CFG_MASKS_H_
  14 #define ASIC_REG_TPC0_CFG_MASKS_H_
  15 
  16 /*
  17  *****************************************
  18  *   TPC0_CFG (Prototype: TPC)
  19  *****************************************
  20  */
  21 
  22 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */
  23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT               0
  24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
  25 
  26 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */
  27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT              0
  28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
  29 
  30 /* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */
  31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT               0
  32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK                0xFFFFFFFF
  33 
  34 /* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */
  35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
  36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
  37 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
  38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
  39 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT        16
  40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
  41 
  42 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */
  43 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT                  0
  44 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
  45 
  46 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */
  47 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT                0
  48 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
  49 
  50 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET */
  51 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT           0
  52 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
  53 
  54 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */
  55 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT                  0
  56 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
  57 
  58 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */
  59 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT                0
  60 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
  61 
  62 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET */
  63 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT           0
  64 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
  65 
  66 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */
  67 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT                  0
  68 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
  69 
  70 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */
  71 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT                0
  72 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
  73 
  74 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET */
  75 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT           0
  76 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
  77 
  78 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */
  79 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT                  0
  80 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
  81 
  82 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */
  83 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT                0
  84 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
  85 
  86 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET */
  87 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT           0
  88 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
  89 
  90 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */
  91 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT                  0
  92 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
  93 
  94 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */
  95 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT                0
  96 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
  97 
  98 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET */
  99 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT           0
 100 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 101 
 102 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */
 103 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT               0
 104 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 105 
 106 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */
 107 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT              0
 108 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 109 
 110 /* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */
 111 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT               0
 112 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK                0xFFFFFFFF
 113 
 114 /* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */
 115 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 116 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 117 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 118 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 119 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 120 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 121 
 122 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */
 123 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT                  0
 124 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 125 
 126 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */
 127 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT                0
 128 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 129 
 130 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET */
 131 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT           0
 132 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 133 
 134 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */
 135 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT                  0
 136 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 137 
 138 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */
 139 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT                0
 140 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 141 
 142 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET */
 143 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT           0
 144 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 145 
 146 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */
 147 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT                  0
 148 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 149 
 150 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */
 151 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT                0
 152 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 153 
 154 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET */
 155 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT           0
 156 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 157 
 158 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */
 159 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT                  0
 160 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 161 
 162 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */
 163 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT                0
 164 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 165 
 166 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET */
 167 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT           0
 168 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 169 
 170 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */
 171 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT                  0
 172 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 173 
 174 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */
 175 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT                0
 176 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 177 
 178 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET */
 179 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT           0
 180 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 181 
 182 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */
 183 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT               0
 184 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 185 
 186 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */
 187 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT              0
 188 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 189 
 190 /* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */
 191 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT               0
 192 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK                0xFFFFFFFF
 193 
 194 /* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */
 195 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 196 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 197 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 198 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 199 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 200 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 201 
 202 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */
 203 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT                  0
 204 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 205 
 206 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */
 207 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT                0
 208 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 209 
 210 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET */
 211 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT           0
 212 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 213 
 214 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */
 215 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT                  0
 216 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 217 
 218 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */
 219 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT                0
 220 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 221 
 222 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET */
 223 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT           0
 224 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 225 
 226 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */
 227 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT                  0
 228 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 229 
 230 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */
 231 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT                0
 232 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 233 
 234 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET */
 235 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT           0
 236 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 237 
 238 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */
 239 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT                  0
 240 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 241 
 242 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */
 243 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT                0
 244 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 245 
 246 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET */
 247 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT           0
 248 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 249 
 250 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */
 251 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT                  0
 252 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 253 
 254 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */
 255 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT                0
 256 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 257 
 258 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET */
 259 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT           0
 260 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 261 
 262 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */
 263 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT               0
 264 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 265 
 266 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */
 267 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT              0
 268 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 269 
 270 /* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */
 271 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT               0
 272 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK                0xFFFFFFFF
 273 
 274 /* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */
 275 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 276 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 277 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 278 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 279 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 280 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 281 
 282 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */
 283 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT                  0
 284 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 285 
 286 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */
 287 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT                0
 288 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 289 
 290 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET */
 291 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT           0
 292 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 293 
 294 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */
 295 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT                  0
 296 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 297 
 298 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */
 299 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT                0
 300 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 301 
 302 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET */
 303 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT           0
 304 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 305 
 306 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */
 307 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT                  0
 308 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 309 
 310 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */
 311 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT                0
 312 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 313 
 314 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET */
 315 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT           0
 316 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 317 
 318 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */
 319 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT                  0
 320 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 321 
 322 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */
 323 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT                0
 324 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 325 
 326 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET */
 327 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT           0
 328 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 329 
 330 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */
 331 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT                  0
 332 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 333 
 334 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */
 335 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT                0
 336 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 337 
 338 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET */
 339 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT           0
 340 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 341 
 342 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */
 343 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT               0
 344 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 345 
 346 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */
 347 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT              0
 348 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 349 
 350 /* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */
 351 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT               0
 352 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK                0xFFFFFFFF
 353 
 354 /* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */
 355 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 356 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 357 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 358 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 359 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 360 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 361 
 362 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */
 363 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT                  0
 364 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 365 
 366 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */
 367 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT                0
 368 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 369 
 370 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET */
 371 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT           0
 372 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 373 
 374 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */
 375 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT                  0
 376 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 377 
 378 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */
 379 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT                0
 380 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 381 
 382 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET */
 383 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT           0
 384 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 385 
 386 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */
 387 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT                  0
 388 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 389 
 390 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */
 391 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT                0
 392 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 393 
 394 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET */
 395 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT           0
 396 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 397 
 398 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */
 399 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT                  0
 400 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 401 
 402 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */
 403 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT                0
 404 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 405 
 406 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET */
 407 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT           0
 408 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 409 
 410 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */
 411 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT                  0
 412 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 413 
 414 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */
 415 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT                0
 416 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 417 
 418 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET */
 419 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT           0
 420 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 421 
 422 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */
 423 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT               0
 424 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 425 
 426 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */
 427 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT              0
 428 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 429 
 430 /* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */
 431 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT               0
 432 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK                0xFFFFFFFF
 433 
 434 /* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */
 435 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 436 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 437 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 438 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 439 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 440 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 441 
 442 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */
 443 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT                  0
 444 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 445 
 446 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */
 447 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT                0
 448 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 449 
 450 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET */
 451 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT           0
 452 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 453 
 454 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */
 455 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT                  0
 456 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 457 
 458 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */
 459 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT                0
 460 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 461 
 462 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET */
 463 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT           0
 464 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 465 
 466 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */
 467 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT                  0
 468 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 469 
 470 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */
 471 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT                0
 472 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 473 
 474 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET */
 475 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT           0
 476 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 477 
 478 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */
 479 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT                  0
 480 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 481 
 482 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */
 483 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT                0
 484 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 485 
 486 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET */
 487 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT           0
 488 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 489 
 490 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */
 491 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT                  0
 492 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 493 
 494 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */
 495 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT                0
 496 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 497 
 498 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET */
 499 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT           0
 500 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 501 
 502 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */
 503 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT               0
 504 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 505 
 506 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */
 507 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT              0
 508 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 509 
 510 /* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */
 511 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT               0
 512 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK                0xFFFFFFFF
 513 
 514 /* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */
 515 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 516 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 517 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 518 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 519 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 520 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 521 
 522 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */
 523 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT                  0
 524 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 525 
 526 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */
 527 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT                0
 528 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 529 
 530 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET */
 531 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT           0
 532 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 533 
 534 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */
 535 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT                  0
 536 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 537 
 538 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */
 539 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT                0
 540 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 541 
 542 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET */
 543 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT           0
 544 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 545 
 546 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */
 547 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT                  0
 548 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 549 
 550 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */
 551 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT                0
 552 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 553 
 554 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET */
 555 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT           0
 556 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 557 
 558 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */
 559 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT                  0
 560 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 561 
 562 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */
 563 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT                0
 564 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 565 
 566 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET */
 567 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT           0
 568 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 569 
 570 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */
 571 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT                  0
 572 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 573 
 574 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */
 575 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT                0
 576 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 577 
 578 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET */
 579 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT           0
 580 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 581 
 582 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */
 583 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT               0
 584 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 585 
 586 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */
 587 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT              0
 588 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 589 
 590 /* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */
 591 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT               0
 592 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK                0xFFFFFFFF
 593 
 594 /* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */
 595 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 596 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 597 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 598 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 599 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 600 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 601 
 602 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */
 603 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT                  0
 604 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 605 
 606 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */
 607 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT                0
 608 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 609 
 610 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET */
 611 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT           0
 612 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 613 
 614 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */
 615 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT                  0
 616 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 617 
 618 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */
 619 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT                0
 620 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 621 
 622 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET */
 623 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT           0
 624 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 625 
 626 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */
 627 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT                  0
 628 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 629 
 630 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */
 631 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT                0
 632 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 633 
 634 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET */
 635 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT           0
 636 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 637 
 638 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */
 639 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT                  0
 640 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 641 
 642 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */
 643 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT                0
 644 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 645 
 646 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET */
 647 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT           0
 648 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 649 
 650 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */
 651 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT                  0
 652 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 653 
 654 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */
 655 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT                0
 656 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 657 
 658 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET */
 659 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT           0
 660 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 661 
 662 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */
 663 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT              0
 664 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK               0xFFFFFFFF
 665 
 666 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */
 667 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT             0
 668 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK              0xFFFFFFFF
 669 
 670 /* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */
 671 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT                       0
 672 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK                        0xFFFFFFFF
 673 
 674 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */
 675 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT                       0
 676 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK                        0xFFFFFFFF
 677 
 678 /* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */
 679 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT                       0
 680 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK                        0xFFFFFFFF
 681 
 682 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */
 683 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT                       0
 684 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK                        0xFFFFFFFF
 685 
 686 /* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */
 687 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT                       0
 688 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK                        0xFFFFFFFF
 689 
 690 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */
 691 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT                       0
 692 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK                        0xFFFFFFFF
 693 
 694 /* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */
 695 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT                       0
 696 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK                        0xFFFFFFFF
 697 
 698 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */
 699 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT                       0
 700 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK                        0xFFFFFFFF
 701 
 702 /* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */
 703 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT                       0
 704 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK                        0xFFFFFFFF
 705 
 706 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */
 707 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT                       0
 708 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK                        0xFFFFFFFF
 709 
 710 /* TPC0_CFG_KERNEL_SRF */
 711 #define TPC0_CFG_KERNEL_SRF_V_SHIFT                                  0
 712 #define TPC0_CFG_KERNEL_SRF_V_MASK                                   0xFFFFFFFF
 713 
 714 /* TPC0_CFG_KERNEL_KERNEL_CONFIG */
 715 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT                0
 716 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK                 0x1
 717 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT             1
 718 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK              0x2
 719 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT           8
 720 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK            0x3F00
 721 
 722 /* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */
 723 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT     0
 724 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK      0xFFFF
 725 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT  16
 726 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK   0x7FFF0000
 727 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT       31
 728 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK        0x80000000
 729 
 730 /* TPC0_CFG_RESERVED_DESC_END */
 731 #define TPC0_CFG_RESERVED_DESC_END_V_SHIFT                           0
 732 #define TPC0_CFG_RESERVED_DESC_END_V_MASK                            0xFFFFFFFF
 733 
 734 /* TPC0_CFG_ROUND_CSR */
 735 #define TPC0_CFG_ROUND_CSR_MODE_SHIFT                                0
 736 #define TPC0_CFG_ROUND_CSR_MODE_MASK                                 0x7
 737 
 738 /* TPC0_CFG_TBUF_BASE_ADDR_LOW */
 739 #define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_SHIFT                          0
 740 #define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_MASK                           0xFFFFFFFF
 741 
 742 /* TPC0_CFG_TBUF_BASE_ADDR_HIGH */
 743 #define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_SHIFT                         0
 744 #define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_MASK                          0xFFFFFFFF
 745 
 746 /* TPC0_CFG_SEMAPHORE */
 747 #define TPC0_CFG_SEMAPHORE_V_SHIFT                                   0
 748 #define TPC0_CFG_SEMAPHORE_V_MASK                                    0xFFFFFFFF
 749 
 750 /* TPC0_CFG_VFLAGS */
 751 #define TPC0_CFG_VFLAGS_V_SHIFT                                      0
 752 #define TPC0_CFG_VFLAGS_V_MASK                                       0xF
 753 
 754 /* TPC0_CFG_SFLAGS */
 755 #define TPC0_CFG_SFLAGS_V_SHIFT                                      0
 756 #define TPC0_CFG_SFLAGS_V_MASK                                       0xF
 757 
 758 /* TPC0_CFG_LFSR_POLYNOM */
 759 #define TPC0_CFG_LFSR_POLYNOM_V_SHIFT                                0
 760 #define TPC0_CFG_LFSR_POLYNOM_V_MASK                                 0xFFFFFFFF
 761 
 762 /* TPC0_CFG_STATUS */
 763 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT                      1
 764 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK                       0x2
 765 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT                      2
 766 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK                       0x4
 767 #define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT                               3
 768 #define TPC0_CFG_STATUS_IQ_EMPTY_MASK                                0x8
 769 #define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_SHIFT                4
 770 #define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK                 0x10
 771 
 772 /* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
 773 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT                       0
 774 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK                        0xFFFFFFFF
 775 
 776 /* TPC0_CFG_CFG_SUBTRACT_VALUE */
 777 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT                          0
 778 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK                           0xFFFFFFFF
 779 
 780 /* TPC0_CFG_SM_BASE_ADDRESS_LOW */
 781 #define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_SHIFT                         0
 782 #define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_MASK                          0xFFFFFFFF
 783 
 784 /* TPC0_CFG_SM_BASE_ADDRESS_HIGH */
 785 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT                        0
 786 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK                         0xFFFFFFFF
 787 
 788 /* TPC0_CFG_TPC_CMD */
 789 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT                     0
 790 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK                      0x1
 791 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT                     1
 792 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK                      0x2
 793 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT                     2
 794 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK                      0x4
 795 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT                     3
 796 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK                      0x8
 797 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT                  4
 798 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK                   0x10
 799 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT                  5
 800 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK                   0x20
 801 #define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT                             6
 802 #define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK                              0x40
 803 
 804 /* TPC0_CFG_TPC_EXECUTE */
 805 #define TPC0_CFG_TPC_EXECUTE_V_SHIFT                                 0
 806 #define TPC0_CFG_TPC_EXECUTE_V_MASK                                  0x1
 807 
 808 /* TPC0_CFG_TPC_STALL */
 809 #define TPC0_CFG_TPC_STALL_V_SHIFT                                   0
 810 #define TPC0_CFG_TPC_STALL_V_MASK                                    0x1
 811 
 812 /* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
 813 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT                    0
 814 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK                     0xFFFFFFFF
 815 
 816 /* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
 817 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT                   0
 818 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK                    0xFFFFFFFF
 819 
 820 /* TPC0_CFG_MSS_CONFIG */
 821 #define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT                            0
 822 #define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK                             0xF
 823 #define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT                            4
 824 #define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK                             0xF0
 825 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT              8
 826 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK               0x300
 827 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT                   10
 828 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK                    0x400
 829 
 830 /* TPC0_CFG_TPC_INTR_CAUSE */
 831 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT                          0
 832 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK                           0xFFFFFFFF
 833 
 834 /* TPC0_CFG_TPC_INTR_MASK */
 835 #define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT                            0
 836 #define TPC0_CFG_TPC_INTR_MASK_MASK_MASK                             0xFFFFFFFF
 837 
 838 /* TPC0_CFG_TSB_CONFIG */
 839 #define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_SHIFT                 0
 840 #define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_MASK                  0x1F
 841 #define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_SHIFT                  5
 842 #define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_MASK                   0x3E0
 843 #define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_SHIFT                    10
 844 #define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_MASK                     0xFFC00
 845 #define TPC0_CFG_TSB_CONFIG_MAX_SIZE_SHIFT                           20
 846 #define TPC0_CFG_TSB_CONFIG_MAX_SIZE_MASK                            0x3FF00000
 847 
 848 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */
 849 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT                   0
 850 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 851 
 852 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */
 853 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT                  0
 854 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 855 
 856 /* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */
 857 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT                   0
 858 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 859 
 860 /* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */
 861 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 862 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 863 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 864 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 865 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 866 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 867 
 868 /* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */
 869 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT                      0
 870 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 871 
 872 /* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */
 873 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT                    0
 874 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 875 
 876 /* TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET */
 877 #define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT               0
 878 #define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 879 
 880 /* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */
 881 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT                      0
 882 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 883 
 884 /* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */
 885 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT                    0
 886 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 887 
 888 /* TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET */
 889 #define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT               0
 890 #define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 891 
 892 /* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */
 893 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT                      0
 894 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 895 
 896 /* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */
 897 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT                    0
 898 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 899 
 900 /* TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET */
 901 #define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT               0
 902 #define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 903 
 904 /* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */
 905 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT                      0
 906 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 907 
 908 /* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */
 909 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT                    0
 910 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 911 
 912 /* TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET */
 913 #define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT               0
 914 #define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 915 
 916 /* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */
 917 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT                      0
 918 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 919 
 920 /* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */
 921 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT                    0
 922 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 923 
 924 /* TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET */
 925 #define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT               0
 926 #define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 927 
 928 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */
 929 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT                   0
 930 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 931 
 932 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */
 933 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT                  0
 934 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 935 
 936 /* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */
 937 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT                   0
 938 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 939 
 940 /* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */
 941 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 942 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 943 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 944 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 945 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 946 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 947 
 948 /* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */
 949 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT                      0
 950 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 951 
 952 /* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */
 953 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT                    0
 954 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 955 
 956 /* TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET */
 957 #define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT               0
 958 #define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 959 
 960 /* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */
 961 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT                      0
 962 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 963 
 964 /* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */
 965 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT                    0
 966 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 967 
 968 /* TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET */
 969 #define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT               0
 970 #define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 971 
 972 /* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */
 973 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT                      0
 974 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 975 
 976 /* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */
 977 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT                    0
 978 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 979 
 980 /* TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET */
 981 #define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT               0
 982 #define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 983 
 984 /* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */
 985 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT                      0
 986 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 987 
 988 /* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */
 989 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT                    0
 990 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 991 
 992 /* TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET */
 993 #define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT               0
 994 #define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 995 
 996 /* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */
 997 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT                      0
 998 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 999 
1000 /* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */
1001 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT                    0
1002 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1003 
1004 /* TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET */
1005 #define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT               0
1006 #define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1007 
1008 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */
1009 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT                   0
1010 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1011 
1012 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */
1013 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT                  0
1014 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1015 
1016 /* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */
1017 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT                   0
1018 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1019 
1020 /* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */
1021 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1022 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
1023 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1024 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1025 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1026 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1027 
1028 /* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */
1029 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT                      0
1030 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1031 
1032 /* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */
1033 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT                    0
1034 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1035 
1036 /* TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET */
1037 #define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT               0
1038 #define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
1039 
1040 /* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */
1041 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT                      0
1042 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1043 
1044 /* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */
1045 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT                    0
1046 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1047 
1048 /* TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET */
1049 #define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT               0
1050 #define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
1051 
1052 /* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */
1053 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT                      0
1054 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1055 
1056 /* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */
1057 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT                    0
1058 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1059 
1060 /* TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET */
1061 #define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT               0
1062 #define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
1063 
1064 /* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */
1065 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT                      0
1066 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1067 
1068 /* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */
1069 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT                    0
1070 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1071 
1072 /* TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET */
1073 #define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT               0
1074 #define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
1075 
1076 /* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */
1077 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT                      0
1078 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1079 
1080 /* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */
1081 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT                    0
1082 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1083 
1084 /* TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET */
1085 #define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT               0
1086 #define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1087 
1088 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */
1089 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT                   0
1090 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1091 
1092 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */
1093 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT                  0
1094 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1095 
1096 /* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */
1097 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT                   0
1098 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1099 
1100 /* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */
1101 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1102 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
1103 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1104 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1105 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1106 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1107 
1108 /* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */
1109 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT                      0
1110 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1111 
1112 /* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */
1113 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT                    0
1114 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1115 
1116 /* TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET */
1117 #define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT               0
1118 #define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
1119 
1120 /* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */
1121 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT                      0
1122 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1123 
1124 /* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */
1125 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT                    0
1126 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1127 
1128 /* TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET */
1129 #define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT               0
1130 #define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
1131 
1132 /* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */
1133 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT                      0
1134 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1135 
1136 /* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */
1137 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT                    0
1138 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1139 
1140 /* TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET */
1141 #define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT               0
1142 #define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
1143 
1144 /* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */
1145 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT                      0
1146 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1147 
1148 /* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */
1149 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT                    0
1150 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1151 
1152 /* TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET */
1153 #define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT               0
1154 #define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
1155 
1156 /* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */
1157 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT                      0
1158 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1159 
1160 /* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */
1161 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT                    0
1162 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1163 
1164 /* TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET */
1165 #define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT               0
1166 #define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1167 
1168 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */
1169 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT                   0
1170 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1171 
1172 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */
1173 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT                  0
1174 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1175 
1176 /* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */
1177 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT                   0
1178 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1179 
1180 /* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */
1181 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1182 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
1183 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1184 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1185 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1186 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1187 
1188 /* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */
1189 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT                      0
1190 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1191 
1192 /* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */
1193 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT                    0
1194 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1195 
1196 /* TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET */
1197 #define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT               0
1198 #define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
1199 
1200 /* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */
1201 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT                      0
1202 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1203 
1204 /* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */
1205 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT                    0
1206 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1207 
1208 /* TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET */
1209 #define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT               0
1210 #define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
1211 
1212 /* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */
1213 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT                      0
1214 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1215 
1216 /* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */
1217 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT                    0
1218 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1219 
1220 /* TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET */
1221 #define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT               0
1222 #define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
1223 
1224 /* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */
1225 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT                      0
1226 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1227 
1228 /* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */
1229 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT                    0
1230 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1231 
1232 /* TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET */
1233 #define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT               0
1234 #define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
1235 
1236 /* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */
1237 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT                      0
1238 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1239 
1240 /* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */
1241 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT                    0
1242 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1243 
1244 /* TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET */
1245 #define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT               0
1246 #define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1247 
1248 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */
1249 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT                   0
1250 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1251 
1252 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */
1253 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT                  0
1254 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1255 
1256 /* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */
1257 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT                   0
1258 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1259 
1260 /* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */
1261 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1262 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
1263 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1264 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1265 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1266 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1267 
1268 /* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */
1269 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT                      0
1270 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1271 
1272 /* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */
1273 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT                    0
1274 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1275 
1276 /* TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET */
1277 #define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT               0
1278 #define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
1279 
1280 /* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */
1281 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT                      0
1282 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1283 
1284 /* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */
1285 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT                    0
1286 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1287 
1288 /* TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET */
1289 #define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT               0
1290 #define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
1291 
1292 /* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */
1293 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT                      0
1294 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1295 
1296 /* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */
1297 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT                    0
1298 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1299 
1300 /* TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET */
1301 #define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT               0
1302 #define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
1303 
1304 /* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */
1305 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT                      0
1306 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1307 
1308 /* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */
1309 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT                    0
1310 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1311 
1312 /* TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET */
1313 #define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT               0
1314 #define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
1315 
1316 /* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */
1317 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT                      0
1318 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1319 
1320 /* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */
1321 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT                    0
1322 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1323 
1324 /* TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET */
1325 #define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT               0
1326 #define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1327 
1328 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */
1329 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT                   0
1330 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1331 
1332 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */
1333 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT                  0
1334 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1335 
1336 /* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */
1337 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT                   0
1338 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1339 
1340 /* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */
1341 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1342 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
1343 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1344 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1345 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1346 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1347 
1348 /* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */
1349 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT                      0
1350 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1351 
1352 /* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */
1353 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT                    0
1354 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1355 
1356 /* TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET */
1357 #define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT               0
1358 #define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
1359 
1360 /* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */
1361 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT                      0
1362 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1363 
1364 /* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */
1365 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT                    0
1366 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1367 
1368 /* TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET */
1369 #define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT               0
1370 #define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
1371 
1372 /* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */
1373 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT                      0
1374 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1375 
1376 /* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */
1377 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT                    0
1378 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1379 
1380 /* TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET */
1381 #define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT               0
1382 #define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
1383 
1384 /* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */
1385 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT                      0
1386 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1387 
1388 /* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */
1389 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT                    0
1390 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1391 
1392 /* TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET */
1393 #define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT               0
1394 #define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
1395 
1396 /* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */
1397 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT                      0
1398 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1399 
1400 /* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */
1401 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT                    0
1402 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1403 
1404 /* TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET */
1405 #define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT               0
1406 #define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1407 
1408 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */
1409 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT                   0
1410 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1411 
1412 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */
1413 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT                  0
1414 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1415 
1416 /* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */
1417 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT                   0
1418 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1419 
1420 /* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */
1421 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1422 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
1423 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1424 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1425 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1426 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1427 
1428 /* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */
1429 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT                      0
1430 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1431 
1432 /* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */
1433 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT                    0
1434 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1435 
1436 /* TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET */
1437 #define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT               0
1438 #define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
1439 
1440 /* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */
1441 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT                      0
1442 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1443 
1444 /* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */
1445 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT                    0
1446 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1447 
1448 /* TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET */
1449 #define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT               0
1450 #define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
1451 
1452 /* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */
1453 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT                      0
1454 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1455 
1456 /* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */
1457 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT                    0
1458 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1459 
1460 /* TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET */
1461 #define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT               0
1462 #define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
1463 
1464 /* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */
1465 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT                      0
1466 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1467 
1468 /* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */
1469 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT                    0
1470 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1471 
1472 /* TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET */
1473 #define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT               0
1474 #define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
1475 
1476 /* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */
1477 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT                      0
1478 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1479 
1480 /* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */
1481 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT                    0
1482 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1483 
1484 /* TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET */
1485 #define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT               0
1486 #define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
1487 
1488 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */
1489 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT                  0
1490 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK                   0xFFFFFFFF
1491 
1492 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */
1493 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT                 0
1494 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK                  0xFFFFFFFF
1495 
1496 /* TPC0_CFG_QM_TID_BASE_DIM_0 */
1497 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT                           0
1498 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK                            0xFFFFFFFF
1499 
1500 /* TPC0_CFG_QM_TID_SIZE_DIM_0 */
1501 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT                           0
1502 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK                            0xFFFFFFFF
1503 
1504 /* TPC0_CFG_QM_TID_BASE_DIM_1 */
1505 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT                           0
1506 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK                            0xFFFFFFFF
1507 
1508 /* TPC0_CFG_QM_TID_SIZE_DIM_1 */
1509 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT                           0
1510 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK                            0xFFFFFFFF
1511 
1512 /* TPC0_CFG_QM_TID_BASE_DIM_2 */
1513 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT                           0
1514 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK                            0xFFFFFFFF
1515 
1516 /* TPC0_CFG_QM_TID_SIZE_DIM_2 */
1517 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT                           0
1518 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK                            0xFFFFFFFF
1519 
1520 /* TPC0_CFG_QM_TID_BASE_DIM_3 */
1521 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT                           0
1522 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK                            0xFFFFFFFF
1523 
1524 /* TPC0_CFG_QM_TID_SIZE_DIM_3 */
1525 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT                           0
1526 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK                            0xFFFFFFFF
1527 
1528 /* TPC0_CFG_QM_TID_BASE_DIM_4 */
1529 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT                           0
1530 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK                            0xFFFFFFFF
1531 
1532 /* TPC0_CFG_QM_TID_SIZE_DIM_4 */
1533 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT                           0
1534 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK                            0xFFFFFFFF
1535 
1536 /* TPC0_CFG_QM_SRF */
1537 #define TPC0_CFG_QM_SRF_V_SHIFT                                      0
1538 #define TPC0_CFG_QM_SRF_V_MASK                                       0xFFFFFFFF
1539 
1540 /* TPC0_CFG_QM_KERNEL_CONFIG */
1541 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT                    0
1542 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK                     0x1
1543 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT                 1
1544 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK                  0x2
1545 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT               8
1546 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK                0x3F00
1547 
1548 /* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */
1549 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT         0
1550 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK          0xFFFF
1551 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT      16
1552 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK       0x7FFF0000
1553 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT           31
1554 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK            0x80000000
1555 
1556 /* TPC0_CFG_ARUSER */
1557 #define TPC0_CFG_ARUSER_ASID_SHIFT                                   0
1558 #define TPC0_CFG_ARUSER_ASID_MASK                                    0x3FF
1559 #define TPC0_CFG_ARUSER_MMBP_SHIFT                                   10
1560 #define TPC0_CFG_ARUSER_MMBP_MASK                                    0x400
1561 #define TPC0_CFG_ARUSER_V_SHIFT                                      11
1562 #define TPC0_CFG_ARUSER_V_MASK                                       0xFFFFF800
1563 
1564 /* TPC0_CFG_AWUSER */
1565 #define TPC0_CFG_AWUSER_ASID_SHIFT                                   0
1566 #define TPC0_CFG_AWUSER_ASID_MASK                                    0x3FF
1567 #define TPC0_CFG_AWUSER_MMBP_SHIFT                                   10
1568 #define TPC0_CFG_AWUSER_MMBP_MASK                                    0x400
1569 #define TPC0_CFG_AWUSER_V_SHIFT                                      11
1570 #define TPC0_CFG_AWUSER_V_MASK                                       0xFFFFF800
1571 
1572 /* TPC0_CFG_FUNC_MBIST_CNTRL */
1573 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT                  0
1574 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK                   0x1
1575 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT                   1
1576 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK                    0x2
1577 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT                 2
1578 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK                  0x4
1579 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT                 16
1580 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK                  0x3FF0000
1581 
1582 /* TPC0_CFG_FUNC_MBIST_PAT */
1583 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT            0
1584 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK             0x3
1585 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT             2
1586 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK              0xC
1587 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT            4
1588 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK             0x30
1589 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT             6
1590 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK              0xC0
1591 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT            8
1592 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK             0x300
1593 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT             10
1594 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK              0xC00
1595 
1596 /* TPC0_CFG_FUNC_MBIST_MEM */
1597 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT                       0
1598 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK                        0x7FF
1599 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT                     12
1600 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK                      0x7000
1601 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT               16
1602 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK                0x7FF0000
1603 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT            28
1604 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK             0x70000000
1605 
1606 #endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */
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root/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h

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