root/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h

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   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_TPC0_CMDQ_MASKS_H_
  14 #define ASIC_REG_TPC0_CMDQ_MASKS_H_
  15 
  16 /*
  17  *****************************************
  18  *   TPC0_CMDQ (Prototype: CMDQ)
  19  *****************************************
  20  */
  21 
  22 /* TPC0_CMDQ_GLBL_CFG0 */
  23 #define TPC0_CMDQ_GLBL_CFG0_PQF_EN_SHIFT                             0
  24 #define TPC0_CMDQ_GLBL_CFG0_PQF_EN_MASK                              0x1
  25 #define TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT                             1
  26 #define TPC0_CMDQ_GLBL_CFG0_CQF_EN_MASK                              0x2
  27 #define TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT                              2
  28 #define TPC0_CMDQ_GLBL_CFG0_CP_EN_MASK                               0x4
  29 #define TPC0_CMDQ_GLBL_CFG0_DMA_EN_SHIFT                             3
  30 #define TPC0_CMDQ_GLBL_CFG0_DMA_EN_MASK                              0x8
  31 
  32 /* TPC0_CMDQ_GLBL_CFG1 */
  33 #define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT                           0
  34 #define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_MASK                            0x1
  35 #define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT                           1
  36 #define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_MASK                            0x2
  37 #define TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT                            2
  38 #define TPC0_CMDQ_GLBL_CFG1_CP_STOP_MASK                             0x4
  39 #define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT                           3
  40 #define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_MASK                            0x8
  41 #define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT                          8
  42 #define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK                           0x100
  43 #define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT                          9
  44 #define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK                           0x200
  45 #define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT                           10
  46 #define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_MASK                            0x400
  47 #define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT                          11
  48 #define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK                           0x800
  49 
  50 /* TPC0_CMDQ_GLBL_PROT */
  51 #define TPC0_CMDQ_GLBL_PROT_PQF_PROT_SHIFT                           0
  52 #define TPC0_CMDQ_GLBL_PROT_PQF_PROT_MASK                            0x1
  53 #define TPC0_CMDQ_GLBL_PROT_CQF_PROT_SHIFT                           1
  54 #define TPC0_CMDQ_GLBL_PROT_CQF_PROT_MASK                            0x2
  55 #define TPC0_CMDQ_GLBL_PROT_CP_PROT_SHIFT                            2
  56 #define TPC0_CMDQ_GLBL_PROT_CP_PROT_MASK                             0x4
  57 #define TPC0_CMDQ_GLBL_PROT_DMA_PROT_SHIFT                           3
  58 #define TPC0_CMDQ_GLBL_PROT_DMA_PROT_MASK                            0x8
  59 #define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT                       4
  60 #define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK                        0x10
  61 #define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT                       5
  62 #define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK                        0x20
  63 #define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT                        6
  64 #define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK                         0x40
  65 #define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT                       7
  66 #define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK                        0x80
  67 
  68 /* TPC0_CMDQ_GLBL_ERR_CFG */
  69 #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT                  0
  70 #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK                   0x1
  71 #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT                  1
  72 #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK                   0x2
  73 #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT                 2
  74 #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK                  0x4
  75 #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT                  3
  76 #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK                   0x8
  77 #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT                  4
  78 #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK                   0x10
  79 #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT                 5
  80 #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK                  0x20
  81 #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT                   6
  82 #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK                    0x40
  83 #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT                   7
  84 #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK                    0x80
  85 #define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT                  8
  86 #define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK                   0x100
  87 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT                  9
  88 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK                   0x200
  89 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT                  10
  90 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK                   0x400
  91 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT                 11
  92 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK                  0x800
  93 
  94 /* TPC0_CMDQ_GLBL_ERR_ADDR_LO */
  95 #define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT                         0
  96 #define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK                          0xFFFFFFFF
  97 
  98 /* TPC0_CMDQ_GLBL_ERR_ADDR_HI */
  99 #define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT                         0
 100 #define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK                          0xFFFFFFFF
 101 
 102 /* TPC0_CMDQ_GLBL_ERR_WDATA */
 103 #define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT                           0
 104 #define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_MASK                            0xFFFFFFFF
 105 
 106 /* TPC0_CMDQ_GLBL_SECURE_PROPS */
 107 #define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT                       0
 108 #define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_MASK                        0x3FF
 109 #define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT                       10
 110 #define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK                        0x400
 111 
 112 /* TPC0_CMDQ_GLBL_NON_SECURE_PROPS */
 113 #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT                   0
 114 #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK                    0x3FF
 115 #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT                   10
 116 #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK                    0x400
 117 
 118 /* TPC0_CMDQ_GLBL_STS0 */
 119 #define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT                           0
 120 #define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_MASK                            0x1
 121 #define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT                           1
 122 #define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK                            0x2
 123 #define TPC0_CMDQ_GLBL_STS0_CP_IDLE_SHIFT                            2
 124 #define TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK                             0x4
 125 #define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT                           3
 126 #define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_MASK                            0x8
 127 #define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT                        4
 128 #define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK                         0x10
 129 #define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT                        5
 130 #define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK                         0x20
 131 #define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT                         6
 132 #define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_MASK                          0x40
 133 #define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT                        7
 134 #define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK                         0x80
 135 
 136 /* TPC0_CMDQ_GLBL_STS1 */
 137 #define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT                         0
 138 #define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK                          0x1
 139 #define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT                         1
 140 #define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK                          0x2
 141 #define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT                          2
 142 #define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_MASK                           0x4
 143 #define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT                   3
 144 #define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK                    0x8
 145 #define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT                         4
 146 #define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_MASK                          0x10
 147 #define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT                      5
 148 #define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK                       0x20
 149 #define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT                         8
 150 #define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK                          0x100
 151 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT                         9
 152 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK                          0x200
 153 #define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT                     10
 154 #define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK                      0x400
 155 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT                     11
 156 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK                      0x800
 157 
 158 /* TPC0_CMDQ_CQ_CFG0 */
 159 #define TPC0_CMDQ_CQ_CFG0_RESERVED_SHIFT                             0
 160 #define TPC0_CMDQ_CQ_CFG0_RESERVED_MASK                              0x1
 161 
 162 /* TPC0_CMDQ_CQ_CFG1 */
 163 #define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT                           0
 164 #define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_MASK                            0xFFFF
 165 #define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT                         16
 166 #define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK                          0xFFFF0000
 167 
 168 /* TPC0_CMDQ_CQ_ARUSER */
 169 #define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT                            0
 170 #define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_MASK                             0x1
 171 #define TPC0_CMDQ_CQ_ARUSER_WORD_SHIFT                               1
 172 #define TPC0_CMDQ_CQ_ARUSER_WORD_MASK                                0x2
 173 
 174 /* TPC0_CMDQ_CQ_PTR_LO */
 175 #define TPC0_CMDQ_CQ_PTR_LO_VAL_SHIFT                                0
 176 #define TPC0_CMDQ_CQ_PTR_LO_VAL_MASK                                 0xFFFFFFFF
 177 
 178 /* TPC0_CMDQ_CQ_PTR_HI */
 179 #define TPC0_CMDQ_CQ_PTR_HI_VAL_SHIFT                                0
 180 #define TPC0_CMDQ_CQ_PTR_HI_VAL_MASK                                 0xFFFFFFFF
 181 
 182 /* TPC0_CMDQ_CQ_TSIZE */
 183 #define TPC0_CMDQ_CQ_TSIZE_VAL_SHIFT                                 0
 184 #define TPC0_CMDQ_CQ_TSIZE_VAL_MASK                                  0xFFFFFFFF
 185 
 186 /* TPC0_CMDQ_CQ_CTL */
 187 #define TPC0_CMDQ_CQ_CTL_RPT_SHIFT                                   0
 188 #define TPC0_CMDQ_CQ_CTL_RPT_MASK                                    0xFFFF
 189 #define TPC0_CMDQ_CQ_CTL_CTL_SHIFT                                   16
 190 #define TPC0_CMDQ_CQ_CTL_CTL_MASK                                    0xFFFF0000
 191 
 192 /* TPC0_CMDQ_CQ_PTR_LO_STS */
 193 #define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT                            0
 194 #define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_MASK                             0xFFFFFFFF
 195 
 196 /* TPC0_CMDQ_CQ_PTR_HI_STS */
 197 #define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT                            0
 198 #define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_MASK                             0xFFFFFFFF
 199 
 200 /* TPC0_CMDQ_CQ_TSIZE_STS */
 201 #define TPC0_CMDQ_CQ_TSIZE_STS_VAL_SHIFT                             0
 202 #define TPC0_CMDQ_CQ_TSIZE_STS_VAL_MASK                              0xFFFFFFFF
 203 
 204 /* TPC0_CMDQ_CQ_CTL_STS */
 205 #define TPC0_CMDQ_CQ_CTL_STS_RPT_SHIFT                               0
 206 #define TPC0_CMDQ_CQ_CTL_STS_RPT_MASK                                0xFFFF
 207 #define TPC0_CMDQ_CQ_CTL_STS_CTL_SHIFT                               16
 208 #define TPC0_CMDQ_CQ_CTL_STS_CTL_MASK                                0xFFFF0000
 209 
 210 /* TPC0_CMDQ_CQ_STS0 */
 211 #define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT                        0
 212 #define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK                         0xFFFF
 213 #define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT                          16
 214 #define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK                           0xFFFF0000
 215 
 216 /* TPC0_CMDQ_CQ_STS1 */
 217 #define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT                      0
 218 #define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK                       0xFFFF
 219 #define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT                         30
 220 #define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK                          0x40000000
 221 #define TPC0_CMDQ_CQ_STS1_CQ_BUSY_SHIFT                              31
 222 #define TPC0_CMDQ_CQ_STS1_CQ_BUSY_MASK                               0x80000000
 223 
 224 /* TPC0_CMDQ_CQ_RD_RATE_LIM_EN */
 225 #define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT                        0
 226 #define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK                         0x1
 227 
 228 /* TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */
 229 #define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT                 0
 230 #define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK                  0xFFFF
 231 
 232 /* TPC0_CMDQ_CQ_RD_RATE_LIM_SAT */
 233 #define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT                       0
 234 #define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK                        0xFFFF
 235 
 236 /* TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT */
 237 #define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT                      0
 238 #define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK                       0x7FFFFFFF
 239 
 240 /* TPC0_CMDQ_CQ_IFIFO_CNT */
 241 #define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT                             0
 242 #define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_MASK                              0x3
 243 
 244 /* TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO */
 245 #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT                     0
 246 #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK                      0xFFFFFFFF
 247 
 248 /* TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI */
 249 #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT                     0
 250 #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK                      0xFFFFFFFF
 251 
 252 /* TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO */
 253 #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT                     0
 254 #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK                      0xFFFFFFFF
 255 
 256 /* TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI */
 257 #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT                     0
 258 #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK                      0xFFFFFFFF
 259 
 260 /* TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO */
 261 #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT                     0
 262 #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK                      0xFFFFFFFF
 263 
 264 /* TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI */
 265 #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT                     0
 266 #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK                      0xFFFFFFFF
 267 
 268 /* TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO */
 269 #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT                     0
 270 #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK                      0xFFFFFFFF
 271 
 272 /* TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI */
 273 #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT                     0
 274 #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK                      0xFFFFFFFF
 275 
 276 /* TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET */
 277 #define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT                     0
 278 #define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK                      0xFFFFFFFF
 279 
 280 /* TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */
 281 #define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT               0
 282 #define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK                0xFFFFFFFF
 283 
 284 /* TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */
 285 #define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT               0
 286 #define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK                0xFFFFFFFF
 287 
 288 /* TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */
 289 #define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT               0
 290 #define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK                0xFFFFFFFF
 291 
 292 /* TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */
 293 #define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT               0
 294 #define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK                0xFFFFFFFF
 295 
 296 /* TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET */
 297 #define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT                    0
 298 #define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK                     0xFFFFFFFF
 299 
 300 /* TPC0_CMDQ_CP_FENCE0_RDATA */
 301 #define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT                      0
 302 #define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK                       0xF
 303 
 304 /* TPC0_CMDQ_CP_FENCE1_RDATA */
 305 #define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT                      0
 306 #define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK                       0xF
 307 
 308 /* TPC0_CMDQ_CP_FENCE2_RDATA */
 309 #define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT                      0
 310 #define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK                       0xF
 311 
 312 /* TPC0_CMDQ_CP_FENCE3_RDATA */
 313 #define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT                      0
 314 #define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK                       0xF
 315 
 316 /* TPC0_CMDQ_CP_FENCE0_CNT */
 317 #define TPC0_CMDQ_CP_FENCE0_CNT_VAL_SHIFT                            0
 318 #define TPC0_CMDQ_CP_FENCE0_CNT_VAL_MASK                             0xFF
 319 
 320 /* TPC0_CMDQ_CP_FENCE1_CNT */
 321 #define TPC0_CMDQ_CP_FENCE1_CNT_VAL_SHIFT                            0
 322 #define TPC0_CMDQ_CP_FENCE1_CNT_VAL_MASK                             0xFF
 323 
 324 /* TPC0_CMDQ_CP_FENCE2_CNT */
 325 #define TPC0_CMDQ_CP_FENCE2_CNT_VAL_SHIFT                            0
 326 #define TPC0_CMDQ_CP_FENCE2_CNT_VAL_MASK                             0xFF
 327 
 328 /* TPC0_CMDQ_CP_FENCE3_CNT */
 329 #define TPC0_CMDQ_CP_FENCE3_CNT_VAL_SHIFT                            0
 330 #define TPC0_CMDQ_CP_FENCE3_CNT_VAL_MASK                             0xFF
 331 
 332 /* TPC0_CMDQ_CP_STS */
 333 #define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT                      0
 334 #define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK                       0xFFFF
 335 #define TPC0_CMDQ_CP_STS_ERDY_SHIFT                                  16
 336 #define TPC0_CMDQ_CP_STS_ERDY_MASK                                   0x10000
 337 #define TPC0_CMDQ_CP_STS_RRDY_SHIFT                                  17
 338 #define TPC0_CMDQ_CP_STS_RRDY_MASK                                   0x20000
 339 #define TPC0_CMDQ_CP_STS_MRDY_SHIFT                                  18
 340 #define TPC0_CMDQ_CP_STS_MRDY_MASK                                   0x40000
 341 #define TPC0_CMDQ_CP_STS_SW_STOP_SHIFT                               19
 342 #define TPC0_CMDQ_CP_STS_SW_STOP_MASK                                0x80000
 343 #define TPC0_CMDQ_CP_STS_FENCE_ID_SHIFT                              20
 344 #define TPC0_CMDQ_CP_STS_FENCE_ID_MASK                               0x300000
 345 #define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT                     22
 346 #define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK                      0x400000
 347 
 348 /* TPC0_CMDQ_CP_CURRENT_INST_LO */
 349 #define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT                       0
 350 #define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_MASK                        0xFFFFFFFF
 351 
 352 /* TPC0_CMDQ_CP_CURRENT_INST_HI */
 353 #define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT                       0
 354 #define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_MASK                        0xFFFFFFFF
 355 
 356 /* TPC0_CMDQ_CP_BARRIER_CFG */
 357 #define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT                       0
 358 #define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK                        0xFFF
 359 
 360 /* TPC0_CMDQ_CP_DBG_0 */
 361 #define TPC0_CMDQ_CP_DBG_0_VAL_SHIFT                                 0
 362 #define TPC0_CMDQ_CP_DBG_0_VAL_MASK                                  0xFF
 363 
 364 /* TPC0_CMDQ_CQ_BUF_ADDR */
 365 #define TPC0_CMDQ_CQ_BUF_ADDR_VAL_SHIFT                              0
 366 #define TPC0_CMDQ_CQ_BUF_ADDR_VAL_MASK                               0xFFFFFFFF
 367 
 368 /* TPC0_CMDQ_CQ_BUF_RDATA */
 369 #define TPC0_CMDQ_CQ_BUF_RDATA_VAL_SHIFT                             0
 370 #define TPC0_CMDQ_CQ_BUF_RDATA_VAL_MASK                              0xFFFFFFFF
 371 
 372 #endif /* ASIC_REG_TPC0_CMDQ_MASKS_H_ */
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