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13 #ifndef ASIC_REG_DMA_QM_1_REGS_H_
14 #define ASIC_REG_DMA_QM_1_REGS_H_
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20
21
22 #define mmDMA_QM_1_GLBL_CFG0 0x408000
23
24 #define mmDMA_QM_1_GLBL_CFG1 0x408004
25
26 #define mmDMA_QM_1_GLBL_PROT 0x408008
27
28 #define mmDMA_QM_1_GLBL_ERR_CFG 0x40800C
29
30 #define mmDMA_QM_1_GLBL_ERR_ADDR_LO 0x408010
31
32 #define mmDMA_QM_1_GLBL_ERR_ADDR_HI 0x408014
33
34 #define mmDMA_QM_1_GLBL_ERR_WDATA 0x408018
35
36 #define mmDMA_QM_1_GLBL_SECURE_PROPS 0x40801C
37
38 #define mmDMA_QM_1_GLBL_NON_SECURE_PROPS 0x408020
39
40 #define mmDMA_QM_1_GLBL_STS0 0x408024
41
42 #define mmDMA_QM_1_GLBL_STS1 0x408028
43
44 #define mmDMA_QM_1_PQ_BASE_LO 0x408060
45
46 #define mmDMA_QM_1_PQ_BASE_HI 0x408064
47
48 #define mmDMA_QM_1_PQ_SIZE 0x408068
49
50 #define mmDMA_QM_1_PQ_PI 0x40806C
51
52 #define mmDMA_QM_1_PQ_CI 0x408070
53
54 #define mmDMA_QM_1_PQ_CFG0 0x408074
55
56 #define mmDMA_QM_1_PQ_CFG1 0x408078
57
58 #define mmDMA_QM_1_PQ_ARUSER 0x40807C
59
60 #define mmDMA_QM_1_PQ_PUSH0 0x408080
61
62 #define mmDMA_QM_1_PQ_PUSH1 0x408084
63
64 #define mmDMA_QM_1_PQ_PUSH2 0x408088
65
66 #define mmDMA_QM_1_PQ_PUSH3 0x40808C
67
68 #define mmDMA_QM_1_PQ_STS0 0x408090
69
70 #define mmDMA_QM_1_PQ_STS1 0x408094
71
72 #define mmDMA_QM_1_PQ_RD_RATE_LIM_EN 0x4080A0
73
74 #define mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN 0x4080A4
75
76 #define mmDMA_QM_1_PQ_RD_RATE_LIM_SAT 0x4080A8
77
78 #define mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT 0x4080AC
79
80 #define mmDMA_QM_1_CQ_CFG0 0x4080B0
81
82 #define mmDMA_QM_1_CQ_CFG1 0x4080B4
83
84 #define mmDMA_QM_1_CQ_ARUSER 0x4080B8
85
86 #define mmDMA_QM_1_CQ_PTR_LO 0x4080C0
87
88 #define mmDMA_QM_1_CQ_PTR_HI 0x4080C4
89
90 #define mmDMA_QM_1_CQ_TSIZE 0x4080C8
91
92 #define mmDMA_QM_1_CQ_CTL 0x4080CC
93
94 #define mmDMA_QM_1_CQ_PTR_LO_STS 0x4080D4
95
96 #define mmDMA_QM_1_CQ_PTR_HI_STS 0x4080D8
97
98 #define mmDMA_QM_1_CQ_TSIZE_STS 0x4080DC
99
100 #define mmDMA_QM_1_CQ_CTL_STS 0x4080E0
101
102 #define mmDMA_QM_1_CQ_STS0 0x4080E4
103
104 #define mmDMA_QM_1_CQ_STS1 0x4080E8
105
106 #define mmDMA_QM_1_CQ_RD_RATE_LIM_EN 0x4080F0
107
108 #define mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN 0x4080F4
109
110 #define mmDMA_QM_1_CQ_RD_RATE_LIM_SAT 0x4080F8
111
112 #define mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT 0x4080FC
113
114 #define mmDMA_QM_1_CQ_IFIFO_CNT 0x408108
115
116 #define mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO 0x408120
117
118 #define mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI 0x408124
119
120 #define mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO 0x408128
121
122 #define mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI 0x40812C
123
124 #define mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO 0x408130
125
126 #define mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI 0x408134
127
128 #define mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO 0x408138
129
130 #define mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI 0x40813C
131
132 #define mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET 0x408140
133
134 #define mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET 0x408144
135
136 #define mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET 0x408148
137
138 #define mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET 0x40814C
139
140 #define mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET 0x408150
141
142 #define mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET 0x408154
143
144 #define mmDMA_QM_1_CP_FENCE0_RDATA 0x408158
145
146 #define mmDMA_QM_1_CP_FENCE1_RDATA 0x40815C
147
148 #define mmDMA_QM_1_CP_FENCE2_RDATA 0x408160
149
150 #define mmDMA_QM_1_CP_FENCE3_RDATA 0x408164
151
152 #define mmDMA_QM_1_CP_FENCE0_CNT 0x408168
153
154 #define mmDMA_QM_1_CP_FENCE1_CNT 0x40816C
155
156 #define mmDMA_QM_1_CP_FENCE2_CNT 0x408170
157
158 #define mmDMA_QM_1_CP_FENCE3_CNT 0x408174
159
160 #define mmDMA_QM_1_CP_STS 0x408178
161
162 #define mmDMA_QM_1_CP_CURRENT_INST_LO 0x40817C
163
164 #define mmDMA_QM_1_CP_CURRENT_INST_HI 0x408180
165
166 #define mmDMA_QM_1_CP_BARRIER_CFG 0x408184
167
168 #define mmDMA_QM_1_CP_DBG_0 0x408188
169
170 #define mmDMA_QM_1_PQ_BUF_ADDR 0x408300
171
172 #define mmDMA_QM_1_PQ_BUF_RDATA 0x408304
173
174 #define mmDMA_QM_1_CQ_BUF_ADDR 0x408308
175
176 #define mmDMA_QM_1_CQ_BUF_RDATA 0x40830C
177
178 #endif