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13 #ifndef ASIC_REG_DMA_QM_4_REGS_H_
14 #define ASIC_REG_DMA_QM_4_REGS_H_
15
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20
21
22 #define mmDMA_QM_4_GLBL_CFG0 0x420000
23
24 #define mmDMA_QM_4_GLBL_CFG1 0x420004
25
26 #define mmDMA_QM_4_GLBL_PROT 0x420008
27
28 #define mmDMA_QM_4_GLBL_ERR_CFG 0x42000C
29
30 #define mmDMA_QM_4_GLBL_ERR_ADDR_LO 0x420010
31
32 #define mmDMA_QM_4_GLBL_ERR_ADDR_HI 0x420014
33
34 #define mmDMA_QM_4_GLBL_ERR_WDATA 0x420018
35
36 #define mmDMA_QM_4_GLBL_SECURE_PROPS 0x42001C
37
38 #define mmDMA_QM_4_GLBL_NON_SECURE_PROPS 0x420020
39
40 #define mmDMA_QM_4_GLBL_STS0 0x420024
41
42 #define mmDMA_QM_4_GLBL_STS1 0x420028
43
44 #define mmDMA_QM_4_PQ_BASE_LO 0x420060
45
46 #define mmDMA_QM_4_PQ_BASE_HI 0x420064
47
48 #define mmDMA_QM_4_PQ_SIZE 0x420068
49
50 #define mmDMA_QM_4_PQ_PI 0x42006C
51
52 #define mmDMA_QM_4_PQ_CI 0x420070
53
54 #define mmDMA_QM_4_PQ_CFG0 0x420074
55
56 #define mmDMA_QM_4_PQ_CFG1 0x420078
57
58 #define mmDMA_QM_4_PQ_ARUSER 0x42007C
59
60 #define mmDMA_QM_4_PQ_PUSH0 0x420080
61
62 #define mmDMA_QM_4_PQ_PUSH1 0x420084
63
64 #define mmDMA_QM_4_PQ_PUSH2 0x420088
65
66 #define mmDMA_QM_4_PQ_PUSH3 0x42008C
67
68 #define mmDMA_QM_4_PQ_STS0 0x420090
69
70 #define mmDMA_QM_4_PQ_STS1 0x420094
71
72 #define mmDMA_QM_4_PQ_RD_RATE_LIM_EN 0x4200A0
73
74 #define mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN 0x4200A4
75
76 #define mmDMA_QM_4_PQ_RD_RATE_LIM_SAT 0x4200A8
77
78 #define mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT 0x4200AC
79
80 #define mmDMA_QM_4_CQ_CFG0 0x4200B0
81
82 #define mmDMA_QM_4_CQ_CFG1 0x4200B4
83
84 #define mmDMA_QM_4_CQ_ARUSER 0x4200B8
85
86 #define mmDMA_QM_4_CQ_PTR_LO 0x4200C0
87
88 #define mmDMA_QM_4_CQ_PTR_HI 0x4200C4
89
90 #define mmDMA_QM_4_CQ_TSIZE 0x4200C8
91
92 #define mmDMA_QM_4_CQ_CTL 0x4200CC
93
94 #define mmDMA_QM_4_CQ_PTR_LO_STS 0x4200D4
95
96 #define mmDMA_QM_4_CQ_PTR_HI_STS 0x4200D8
97
98 #define mmDMA_QM_4_CQ_TSIZE_STS 0x4200DC
99
100 #define mmDMA_QM_4_CQ_CTL_STS 0x4200E0
101
102 #define mmDMA_QM_4_CQ_STS0 0x4200E4
103
104 #define mmDMA_QM_4_CQ_STS1 0x4200E8
105
106 #define mmDMA_QM_4_CQ_RD_RATE_LIM_EN 0x4200F0
107
108 #define mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN 0x4200F4
109
110 #define mmDMA_QM_4_CQ_RD_RATE_LIM_SAT 0x4200F8
111
112 #define mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT 0x4200FC
113
114 #define mmDMA_QM_4_CQ_IFIFO_CNT 0x420108
115
116 #define mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO 0x420120
117
118 #define mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI 0x420124
119
120 #define mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO 0x420128
121
122 #define mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI 0x42012C
123
124 #define mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO 0x420130
125
126 #define mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI 0x420134
127
128 #define mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO 0x420138
129
130 #define mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI 0x42013C
131
132 #define mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET 0x420140
133
134 #define mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET 0x420144
135
136 #define mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET 0x420148
137
138 #define mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET 0x42014C
139
140 #define mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET 0x420150
141
142 #define mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET 0x420154
143
144 #define mmDMA_QM_4_CP_FENCE0_RDATA 0x420158
145
146 #define mmDMA_QM_4_CP_FENCE1_RDATA 0x42015C
147
148 #define mmDMA_QM_4_CP_FENCE2_RDATA 0x420160
149
150 #define mmDMA_QM_4_CP_FENCE3_RDATA 0x420164
151
152 #define mmDMA_QM_4_CP_FENCE0_CNT 0x420168
153
154 #define mmDMA_QM_4_CP_FENCE1_CNT 0x42016C
155
156 #define mmDMA_QM_4_CP_FENCE2_CNT 0x420170
157
158 #define mmDMA_QM_4_CP_FENCE3_CNT 0x420174
159
160 #define mmDMA_QM_4_CP_STS 0x420178
161
162 #define mmDMA_QM_4_CP_CURRENT_INST_LO 0x42017C
163
164 #define mmDMA_QM_4_CP_CURRENT_INST_HI 0x420180
165
166 #define mmDMA_QM_4_CP_BARRIER_CFG 0x420184
167
168 #define mmDMA_QM_4_CP_DBG_0 0x420188
169
170 #define mmDMA_QM_4_PQ_BUF_ADDR 0x420300
171
172 #define mmDMA_QM_4_PQ_BUF_RDATA 0x420304
173
174 #define mmDMA_QM_4_CQ_BUF_ADDR 0x420308
175
176 #define mmDMA_QM_4_CQ_BUF_RDATA 0x42030C
177
178 #endif