root/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_DMA_CH_4_REGS_H_
  14 #define ASIC_REG_DMA_CH_4_REGS_H_
  15 
  16 /*
  17  *****************************************
  18  *   DMA_CH_4 (Prototype: DMA_CH)
  19  *****************************************
  20  */
  21 
  22 #define mmDMA_CH_4_CFG0                                              0x421000
  23 
  24 #define mmDMA_CH_4_CFG1                                              0x421004
  25 
  26 #define mmDMA_CH_4_ERRMSG_ADDR_LO                                    0x421008
  27 
  28 #define mmDMA_CH_4_ERRMSG_ADDR_HI                                    0x42100C
  29 
  30 #define mmDMA_CH_4_ERRMSG_WDATA                                      0x421010
  31 
  32 #define mmDMA_CH_4_RD_COMP_ADDR_LO                                   0x421014
  33 
  34 #define mmDMA_CH_4_RD_COMP_ADDR_HI                                   0x421018
  35 
  36 #define mmDMA_CH_4_RD_COMP_WDATA                                     0x42101C
  37 
  38 #define mmDMA_CH_4_WR_COMP_ADDR_LO                                   0x421020
  39 
  40 #define mmDMA_CH_4_WR_COMP_ADDR_HI                                   0x421024
  41 
  42 #define mmDMA_CH_4_WR_COMP_WDATA                                     0x421028
  43 
  44 #define mmDMA_CH_4_LDMA_SRC_ADDR_LO                                  0x42102C
  45 
  46 #define mmDMA_CH_4_LDMA_SRC_ADDR_HI                                  0x421030
  47 
  48 #define mmDMA_CH_4_LDMA_DST_ADDR_LO                                  0x421034
  49 
  50 #define mmDMA_CH_4_LDMA_DST_ADDR_HI                                  0x421038
  51 
  52 #define mmDMA_CH_4_LDMA_TSIZE                                        0x42103C
  53 
  54 #define mmDMA_CH_4_COMIT_TRANSFER                                    0x421040
  55 
  56 #define mmDMA_CH_4_STS0                                              0x421044
  57 
  58 #define mmDMA_CH_4_STS1                                              0x421048
  59 
  60 #define mmDMA_CH_4_STS2                                              0x42104C
  61 
  62 #define mmDMA_CH_4_STS3                                              0x421050
  63 
  64 #define mmDMA_CH_4_STS4                                              0x421054
  65 
  66 #define mmDMA_CH_4_SRC_ADDR_LO_STS                                   0x421058
  67 
  68 #define mmDMA_CH_4_SRC_ADDR_HI_STS                                   0x42105C
  69 
  70 #define mmDMA_CH_4_SRC_TSIZE_STS                                     0x421060
  71 
  72 #define mmDMA_CH_4_DST_ADDR_LO_STS                                   0x421064
  73 
  74 #define mmDMA_CH_4_DST_ADDR_HI_STS                                   0x421068
  75 
  76 #define mmDMA_CH_4_DST_TSIZE_STS                                     0x42106C
  77 
  78 #define mmDMA_CH_4_RD_RATE_LIM_EN                                    0x421070
  79 
  80 #define mmDMA_CH_4_RD_RATE_LIM_RST_TOKEN                             0x421074
  81 
  82 #define mmDMA_CH_4_RD_RATE_LIM_SAT                                   0x421078
  83 
  84 #define mmDMA_CH_4_RD_RATE_LIM_TOUT                                  0x42107C
  85 
  86 #define mmDMA_CH_4_WR_RATE_LIM_EN                                    0x421080
  87 
  88 #define mmDMA_CH_4_WR_RATE_LIM_RST_TOKEN                             0x421084
  89 
  90 #define mmDMA_CH_4_WR_RATE_LIM_SAT                                   0x421088
  91 
  92 #define mmDMA_CH_4_WR_RATE_LIM_TOUT                                  0x42108C
  93 
  94 #define mmDMA_CH_4_CFG2                                              0x421090
  95 
  96 #define mmDMA_CH_4_TDMA_CTL                                          0x421100
  97 
  98 #define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_LO                             0x421104
  99 
 100 #define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_HI                             0x421108
 101 
 102 #define mmDMA_CH_4_TDMA_SRC_ROI_BASE_0                               0x42110C
 103 
 104 #define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_0                               0x421110
 105 
 106 #define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_0                         0x421114
 107 
 108 #define mmDMA_CH_4_TDMA_SRC_START_OFFSET_0                           0x421118
 109 
 110 #define mmDMA_CH_4_TDMA_SRC_STRIDE_0                                 0x42111C
 111 
 112 #define mmDMA_CH_4_TDMA_SRC_ROI_BASE_1                               0x421120
 113 
 114 #define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_1                               0x421124
 115 
 116 #define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_1                         0x421128
 117 
 118 #define mmDMA_CH_4_TDMA_SRC_START_OFFSET_1                           0x42112C
 119 
 120 #define mmDMA_CH_4_TDMA_SRC_STRIDE_1                                 0x421130
 121 
 122 #define mmDMA_CH_4_TDMA_SRC_ROI_BASE_2                               0x421134
 123 
 124 #define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_2                               0x421138
 125 
 126 #define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_2                         0x42113C
 127 
 128 #define mmDMA_CH_4_TDMA_SRC_START_OFFSET_2                           0x421140
 129 
 130 #define mmDMA_CH_4_TDMA_SRC_STRIDE_2                                 0x421144
 131 
 132 #define mmDMA_CH_4_TDMA_SRC_ROI_BASE_3                               0x421148
 133 
 134 #define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_3                               0x42114C
 135 
 136 #define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_3                         0x421150
 137 
 138 #define mmDMA_CH_4_TDMA_SRC_START_OFFSET_3                           0x421154
 139 
 140 #define mmDMA_CH_4_TDMA_SRC_STRIDE_3                                 0x421158
 141 
 142 #define mmDMA_CH_4_TDMA_SRC_ROI_BASE_4                               0x42115C
 143 
 144 #define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_4                               0x421160
 145 
 146 #define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_4                         0x421164
 147 
 148 #define mmDMA_CH_4_TDMA_SRC_START_OFFSET_4                           0x421168
 149 
 150 #define mmDMA_CH_4_TDMA_SRC_STRIDE_4                                 0x42116C
 151 
 152 #define mmDMA_CH_4_TDMA_DST_BASE_ADDR_LO                             0x421170
 153 
 154 #define mmDMA_CH_4_TDMA_DST_BASE_ADDR_HI                             0x421174
 155 
 156 #define mmDMA_CH_4_TDMA_DST_ROI_BASE_0                               0x421178
 157 
 158 #define mmDMA_CH_4_TDMA_DST_ROI_SIZE_0                               0x42117C
 159 
 160 #define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_0                         0x421180
 161 
 162 #define mmDMA_CH_4_TDMA_DST_START_OFFSET_0                           0x421184
 163 
 164 #define mmDMA_CH_4_TDMA_DST_STRIDE_0                                 0x421188
 165 
 166 #define mmDMA_CH_4_TDMA_DST_ROI_BASE_1                               0x42118C
 167 
 168 #define mmDMA_CH_4_TDMA_DST_ROI_SIZE_1                               0x421190
 169 
 170 #define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_1                         0x421194
 171 
 172 #define mmDMA_CH_4_TDMA_DST_START_OFFSET_1                           0x421198
 173 
 174 #define mmDMA_CH_4_TDMA_DST_STRIDE_1                                 0x42119C
 175 
 176 #define mmDMA_CH_4_TDMA_DST_ROI_BASE_2                               0x4211A0
 177 
 178 #define mmDMA_CH_4_TDMA_DST_ROI_SIZE_2                               0x4211A4
 179 
 180 #define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_2                         0x4211A8
 181 
 182 #define mmDMA_CH_4_TDMA_DST_START_OFFSET_2                           0x4211AC
 183 
 184 #define mmDMA_CH_4_TDMA_DST_STRIDE_2                                 0x4211B0
 185 
 186 #define mmDMA_CH_4_TDMA_DST_ROI_BASE_3                               0x4211B4
 187 
 188 #define mmDMA_CH_4_TDMA_DST_ROI_SIZE_3                               0x4211B8
 189 
 190 #define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_3                         0x4211BC
 191 
 192 #define mmDMA_CH_4_TDMA_DST_START_OFFSET_3                           0x4211C0
 193 
 194 #define mmDMA_CH_4_TDMA_DST_STRIDE_3                                 0x4211C4
 195 
 196 #define mmDMA_CH_4_TDMA_DST_ROI_BASE_4                               0x4211C8
 197 
 198 #define mmDMA_CH_4_TDMA_DST_ROI_SIZE_4                               0x4211CC
 199 
 200 #define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_4                         0x4211D0
 201 
 202 #define mmDMA_CH_4_TDMA_DST_START_OFFSET_4                           0x4211D4
 203 
 204 #define mmDMA_CH_4_TDMA_DST_STRIDE_4                                 0x4211D8
 205 
 206 #define mmDMA_CH_4_MEM_INIT_BUSY                                     0x4211FC
 207 
 208 #endif /* ASIC_REG_DMA_CH_4_REGS_H_ */

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