root/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7 
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12 
  13 #ifndef ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_
  14 #define ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_
  15 
  16 /*
  17  *****************************************
  18  *   SRAM_Y0_X3_RTR (Prototype: IC_RTR)
  19  *****************************************
  20  */
  21 
  22 #define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_E_ARB                             0x20D100
  23 
  24 #define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_W_ARB                             0x20D104
  25 
  26 #define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB                             0x20D110
  27 
  28 #define mmSRAM_Y0_X3_RTR_HBW_E_ARB_MAX                               0x20D120
  29 
  30 #define mmSRAM_Y0_X3_RTR_HBW_W_ARB_MAX                               0x20D124
  31 
  32 #define mmSRAM_Y0_X3_RTR_HBW_L_ARB_MAX                               0x20D130
  33 
  34 #define mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB                              0x20D140
  35 
  36 #define mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB                              0x20D144
  37 
  38 #define mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB                              0x20D148
  39 
  40 #define mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB                             0x20D160
  41 
  42 #define mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB                             0x20D164
  43 
  44 #define mmSRAM_Y0_X3_RTR_HBW_WR_RS_L_ARB                             0x20D168
  45 
  46 #define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_E_ARB                             0x20D200
  47 
  48 #define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_W_ARB                             0x20D204
  49 
  50 #define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_L_ARB                             0x20D210
  51 
  52 #define mmSRAM_Y0_X3_RTR_LBW_E_ARB_MAX                               0x20D220
  53 
  54 #define mmSRAM_Y0_X3_RTR_LBW_W_ARB_MAX                               0x20D224
  55 
  56 #define mmSRAM_Y0_X3_RTR_LBW_L_ARB_MAX                               0x20D230
  57 
  58 #define mmSRAM_Y0_X3_RTR_LBW_DATA_E_ARB                              0x20D240
  59 
  60 #define mmSRAM_Y0_X3_RTR_LBW_DATA_W_ARB                              0x20D244
  61 
  62 #define mmSRAM_Y0_X3_RTR_LBW_DATA_L_ARB                              0x20D248
  63 
  64 #define mmSRAM_Y0_X3_RTR_LBW_WR_RS_E_ARB                             0x20D260
  65 
  66 #define mmSRAM_Y0_X3_RTR_LBW_WR_RS_W_ARB                             0x20D264
  67 
  68 #define mmSRAM_Y0_X3_RTR_LBW_WR_RS_L_ARB                             0x20D268
  69 
  70 #define mmSRAM_Y0_X3_RTR_DBG_E_ARB                                   0x20D300
  71 
  72 #define mmSRAM_Y0_X3_RTR_DBG_W_ARB                                   0x20D304
  73 
  74 #define mmSRAM_Y0_X3_RTR_DBG_L_ARB                                   0x20D310
  75 
  76 #define mmSRAM_Y0_X3_RTR_DBG_E_ARB_MAX                               0x20D320
  77 
  78 #define mmSRAM_Y0_X3_RTR_DBG_W_ARB_MAX                               0x20D324
  79 
  80 #define mmSRAM_Y0_X3_RTR_DBG_L_ARB_MAX                               0x20D330
  81 
  82 #endif /* ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ */