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13 #ifndef ASIC_REG_TPC4_QM_REGS_H_
14 #define ASIC_REG_TPC4_QM_REGS_H_
15
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20
21
22 #define mmTPC4_QM_GLBL_CFG0 0xF08000
23
24 #define mmTPC4_QM_GLBL_CFG1 0xF08004
25
26 #define mmTPC4_QM_GLBL_PROT 0xF08008
27
28 #define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C
29
30 #define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08010
31
32 #define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08014
33
34 #define mmTPC4_QM_GLBL_ERR_WDATA 0xF08018
35
36 #define mmTPC4_QM_GLBL_SECURE_PROPS 0xF0801C
37
38 #define mmTPC4_QM_GLBL_NON_SECURE_PROPS 0xF08020
39
40 #define mmTPC4_QM_GLBL_STS0 0xF08024
41
42 #define mmTPC4_QM_GLBL_STS1 0xF08028
43
44 #define mmTPC4_QM_PQ_BASE_LO 0xF08060
45
46 #define mmTPC4_QM_PQ_BASE_HI 0xF08064
47
48 #define mmTPC4_QM_PQ_SIZE 0xF08068
49
50 #define mmTPC4_QM_PQ_PI 0xF0806C
51
52 #define mmTPC4_QM_PQ_CI 0xF08070
53
54 #define mmTPC4_QM_PQ_CFG0 0xF08074
55
56 #define mmTPC4_QM_PQ_CFG1 0xF08078
57
58 #define mmTPC4_QM_PQ_ARUSER 0xF0807C
59
60 #define mmTPC4_QM_PQ_PUSH0 0xF08080
61
62 #define mmTPC4_QM_PQ_PUSH1 0xF08084
63
64 #define mmTPC4_QM_PQ_PUSH2 0xF08088
65
66 #define mmTPC4_QM_PQ_PUSH3 0xF0808C
67
68 #define mmTPC4_QM_PQ_STS0 0xF08090
69
70 #define mmTPC4_QM_PQ_STS1 0xF08094
71
72 #define mmTPC4_QM_PQ_RD_RATE_LIM_EN 0xF080A0
73
74 #define mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF080A4
75
76 #define mmTPC4_QM_PQ_RD_RATE_LIM_SAT 0xF080A8
77
78 #define mmTPC4_QM_PQ_RD_RATE_LIM_TOUT 0xF080AC
79
80 #define mmTPC4_QM_CQ_CFG0 0xF080B0
81
82 #define mmTPC4_QM_CQ_CFG1 0xF080B4
83
84 #define mmTPC4_QM_CQ_ARUSER 0xF080B8
85
86 #define mmTPC4_QM_CQ_PTR_LO 0xF080C0
87
88 #define mmTPC4_QM_CQ_PTR_HI 0xF080C4
89
90 #define mmTPC4_QM_CQ_TSIZE 0xF080C8
91
92 #define mmTPC4_QM_CQ_CTL 0xF080CC
93
94 #define mmTPC4_QM_CQ_PTR_LO_STS 0xF080D4
95
96 #define mmTPC4_QM_CQ_PTR_HI_STS 0xF080D8
97
98 #define mmTPC4_QM_CQ_TSIZE_STS 0xF080DC
99
100 #define mmTPC4_QM_CQ_CTL_STS 0xF080E0
101
102 #define mmTPC4_QM_CQ_STS0 0xF080E4
103
104 #define mmTPC4_QM_CQ_STS1 0xF080E8
105
106 #define mmTPC4_QM_CQ_RD_RATE_LIM_EN 0xF080F0
107
108 #define mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF080F4
109
110 #define mmTPC4_QM_CQ_RD_RATE_LIM_SAT 0xF080F8
111
112 #define mmTPC4_QM_CQ_RD_RATE_LIM_TOUT 0xF080FC
113
114 #define mmTPC4_QM_CQ_IFIFO_CNT 0xF08108
115
116 #define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO 0xF08120
117
118 #define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI 0xF08124
119
120 #define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO 0xF08128
121
122 #define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI 0xF0812C
123
124 #define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO 0xF08130
125
126 #define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI 0xF08134
127
128 #define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO 0xF08138
129
130 #define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI 0xF0813C
131
132 #define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET 0xF08140
133
134 #define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF08144
135
136 #define mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF08148
137
138 #define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF0814C
139
140 #define mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF08150
141
142 #define mmTPC4_QM_CP_LDMA_COMMIT_OFFSET 0xF08154
143
144 #define mmTPC4_QM_CP_FENCE0_RDATA 0xF08158
145
146 #define mmTPC4_QM_CP_FENCE1_RDATA 0xF0815C
147
148 #define mmTPC4_QM_CP_FENCE2_RDATA 0xF08160
149
150 #define mmTPC4_QM_CP_FENCE3_RDATA 0xF08164
151
152 #define mmTPC4_QM_CP_FENCE0_CNT 0xF08168
153
154 #define mmTPC4_QM_CP_FENCE1_CNT 0xF0816C
155
156 #define mmTPC4_QM_CP_FENCE2_CNT 0xF08170
157
158 #define mmTPC4_QM_CP_FENCE3_CNT 0xF08174
159
160 #define mmTPC4_QM_CP_STS 0xF08178
161
162 #define mmTPC4_QM_CP_CURRENT_INST_LO 0xF0817C
163
164 #define mmTPC4_QM_CP_CURRENT_INST_HI 0xF08180
165
166 #define mmTPC4_QM_CP_BARRIER_CFG 0xF08184
167
168 #define mmTPC4_QM_CP_DBG_0 0xF08188
169
170 #define mmTPC4_QM_PQ_BUF_ADDR 0xF08300
171
172 #define mmTPC4_QM_PQ_BUF_RDATA 0xF08304
173
174 #define mmTPC4_QM_CQ_BUF_ADDR 0xF08308
175
176 #define mmTPC4_QM_CQ_BUF_RDATA 0xF0830C
177
178 #endif