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13 #ifndef ASIC_REG_TPC5_CFG_REGS_H_
14 #define ASIC_REG_TPC5_CFG_REGS_H_
15
16
17
18
19
20
21
22 #define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400
23
24 #define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404
25
26 #define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408
27
28 #define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C
29
30 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410
31
32 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414
33
34 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF46418
35
36 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF4641C
37
38 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF46420
39
40 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF46424
41
42 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46428
43
44 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF4642C
45
46 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF46430
47
48 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46434
49
50 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF46438
51
52 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF4643C
53
54 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46440
55
56 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46444
57
58 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF46448
59
60 #define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF4644C
61
62 #define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF46450
63
64 #define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46454
65
66 #define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46458
67
68 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF4645C
69
70 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF46460
71
72 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF46464
73
74 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46468
75
76 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF4646C
77
78 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF46470
79
80 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46474
81
82 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF46478
83
84 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF4647C
85
86 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46480
87
88 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46484
89
90 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF46488
91
92 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF4648C
93
94 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF46490
95
96 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF46494
97
98 #define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46498
99
100 #define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF4649C
101
102 #define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF464A0
103
104 #define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF464A4
105
106 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF464A8
107
108 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF464AC
109
110 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF464B0
111
112 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF464B4
113
114 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF464B8
115
116 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF464BC
117
118 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF464C0
119
120 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF464C4
121
122 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF464C8
123
124 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF464CC
125
126 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF464D0
127
128 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF464D4
129
130 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464D8
131
132 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464DC
133
134 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF464E0
135
136 #define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464E4
137
138 #define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464E8
139
140 #define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464EC
141
142 #define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464F0
143
144 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464F4
145
146 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464F8
147
148 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF464FC
149
150 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF46500
151
152 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF46504
153
154 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF46508
155
156 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF4650C
157
158 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF46510
159
160 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF46514
161
162 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF46518
163
164 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF4651C
165
166 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF46520
167
168 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF46524
169
170 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF46528
171
172 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF4652C
173
174 #define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF46530
175
176 #define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF46534
177
178 #define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF46538
179
180 #define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF4653C
181
182 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF46540
183
184 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF46544
185
186 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF46548
187
188 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF4654C
189
190 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF46550
191
192 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF46554
193
194 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46558
195
196 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF4655C
197
198 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF46560
199
200 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46564
201
202 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF46568
203
204 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF4656C
205
206 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46570
207
208 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46574
209
210 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF46578
211
212 #define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF4657C
213
214 #define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF46580
215
216 #define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46584
217
218 #define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46588
219
220 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF4658C
221
222 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF46590
223
224 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF46594
225
226 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46598
227
228 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF4659C
229
230 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF465A0
231
232 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF465A4
233
234 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF465A8
235
236 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF465AC
237
238 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF465B0
239
240 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF465B4
241
242 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF465B8
243
244 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF465BC
245
246 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF465C0
247
248 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF465C4
249
250 #define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF465C8
251
252 #define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF465CC
253
254 #define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF465D0
255
256 #define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF465D4
257
258 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF465D8
259
260 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF465DC
261
262 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF465E0
263
264 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF465E4
265
266 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF465E8
267
268 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF465EC
269
270 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF465F0
271
272 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF465F4
273
274 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF465F8
275
276 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF465FC
277
278 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF46600
279
280 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF46604
281
282 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46608
283
284 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF4660C
285
286 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF46610
287
288 #define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46614
289
290 #define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF46618
291
292 #define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF4661C
293
294 #define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46620
295
296 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46624
297
298 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF46628
299
300 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF4662C
301
302 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF46630
303
304 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF46634
305
306 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF46638
307
308 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF4663C
309
310 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF46640
311
312 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF46644
313
314 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF46648
315
316 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF4664C
317
318 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF46650
319
320 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF46654
321
322 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF46658
323
324 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF4665C
325
326 #define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46660
327
328 #define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF46664
329
330 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46668
331
332 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF4666C
333
334 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46670
335
336 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF46674
337
338 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF46678
339
340 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF4667C
341
342 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF46680
343
344 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF46684
345
346 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF46688
347
348 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF4668C
349
350 #define mmTPC5_CFG_KERNEL_SRF_0 0xF46690
351
352 #define mmTPC5_CFG_KERNEL_SRF_1 0xF46694
353
354 #define mmTPC5_CFG_KERNEL_SRF_2 0xF46698
355
356 #define mmTPC5_CFG_KERNEL_SRF_3 0xF4669C
357
358 #define mmTPC5_CFG_KERNEL_SRF_4 0xF466A0
359
360 #define mmTPC5_CFG_KERNEL_SRF_5 0xF466A4
361
362 #define mmTPC5_CFG_KERNEL_SRF_6 0xF466A8
363
364 #define mmTPC5_CFG_KERNEL_SRF_7 0xF466AC
365
366 #define mmTPC5_CFG_KERNEL_SRF_8 0xF466B0
367
368 #define mmTPC5_CFG_KERNEL_SRF_9 0xF466B4
369
370 #define mmTPC5_CFG_KERNEL_SRF_10 0xF466B8
371
372 #define mmTPC5_CFG_KERNEL_SRF_11 0xF466BC
373
374 #define mmTPC5_CFG_KERNEL_SRF_12 0xF466C0
375
376 #define mmTPC5_CFG_KERNEL_SRF_13 0xF466C4
377
378 #define mmTPC5_CFG_KERNEL_SRF_14 0xF466C8
379
380 #define mmTPC5_CFG_KERNEL_SRF_15 0xF466CC
381
382 #define mmTPC5_CFG_KERNEL_SRF_16 0xF466D0
383
384 #define mmTPC5_CFG_KERNEL_SRF_17 0xF466D4
385
386 #define mmTPC5_CFG_KERNEL_SRF_18 0xF466D8
387
388 #define mmTPC5_CFG_KERNEL_SRF_19 0xF466DC
389
390 #define mmTPC5_CFG_KERNEL_SRF_20 0xF466E0
391
392 #define mmTPC5_CFG_KERNEL_SRF_21 0xF466E4
393
394 #define mmTPC5_CFG_KERNEL_SRF_22 0xF466E8
395
396 #define mmTPC5_CFG_KERNEL_SRF_23 0xF466EC
397
398 #define mmTPC5_CFG_KERNEL_SRF_24 0xF466F0
399
400 #define mmTPC5_CFG_KERNEL_SRF_25 0xF466F4
401
402 #define mmTPC5_CFG_KERNEL_SRF_26 0xF466F8
403
404 #define mmTPC5_CFG_KERNEL_SRF_27 0xF466FC
405
406 #define mmTPC5_CFG_KERNEL_SRF_28 0xF46700
407
408 #define mmTPC5_CFG_KERNEL_SRF_29 0xF46704
409
410 #define mmTPC5_CFG_KERNEL_SRF_30 0xF46708
411
412 #define mmTPC5_CFG_KERNEL_SRF_31 0xF4670C
413
414 #define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF46710
415
416 #define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46714
417
418 #define mmTPC5_CFG_RESERVED_DESC_END 0xF46738
419
420 #define mmTPC5_CFG_ROUND_CSR 0xF467FC
421
422 #define mmTPC5_CFG_TBUF_BASE_ADDR_LOW 0xF46800
423
424 #define mmTPC5_CFG_TBUF_BASE_ADDR_HIGH 0xF46804
425
426 #define mmTPC5_CFG_SEMAPHORE 0xF46808
427
428 #define mmTPC5_CFG_VFLAGS 0xF4680C
429
430 #define mmTPC5_CFG_SFLAGS 0xF46810
431
432 #define mmTPC5_CFG_LFSR_POLYNOM 0xF46818
433
434 #define mmTPC5_CFG_STATUS 0xF4681C
435
436 #define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46820
437
438 #define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46824
439
440 #define mmTPC5_CFG_SM_BASE_ADDRESS_LOW 0xF46828
441
442 #define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4682C
443
444 #define mmTPC5_CFG_TPC_CMD 0xF46830
445
446 #define mmTPC5_CFG_TPC_EXECUTE 0xF46838
447
448 #define mmTPC5_CFG_TPC_STALL 0xF4683C
449
450 #define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46840
451
452 #define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46844
453
454 #define mmTPC5_CFG_MSS_CONFIG 0xF46854
455
456 #define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46858
457
458 #define mmTPC5_CFG_TPC_INTR_MASK 0xF4685C
459
460 #define mmTPC5_CFG_TSB_CONFIG 0xF46860
461
462 #define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00
463
464 #define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04
465
466 #define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08
467
468 #define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C
469
470 #define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10
471
472 #define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14
473
474 #define mmTPC5_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF46A18
475
476 #define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A1C
477
478 #define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A20
479
480 #define mmTPC5_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF46A24
481
482 #define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A28
483
484 #define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A2C
485
486 #define mmTPC5_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF46A30
487
488 #define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A34
489
490 #define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A38
491
492 #define mmTPC5_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF46A3C
493
494 #define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A40
495
496 #define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A44
497
498 #define mmTPC5_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF46A48
499
500 #define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A4C
501
502 #define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A50
503
504 #define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A54
505
506 #define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A58
507
508 #define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A5C
509
510 #define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A60
511
512 #define mmTPC5_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF46A64
513
514 #define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A68
515
516 #define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A6C
517
518 #define mmTPC5_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF46A70
519
520 #define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A74
521
522 #define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A78
523
524 #define mmTPC5_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF46A7C
525
526 #define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A80
527
528 #define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A84
529
530 #define mmTPC5_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF46A88
531
532 #define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A8C
533
534 #define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A90
535
536 #define mmTPC5_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF46A94
537
538 #define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A98
539
540 #define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A9C
541
542 #define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46AA0
543
544 #define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46AA4
545
546 #define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46AA8
547
548 #define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46AAC
549
550 #define mmTPC5_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF46AB0
551
552 #define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46AB4
553
554 #define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46AB8
555
556 #define mmTPC5_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF46ABC
557
558 #define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46AC0
559
560 #define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46AC4
561
562 #define mmTPC5_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF46AC8
563
564 #define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46ACC
565
566 #define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46AD0
567
568 #define mmTPC5_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF46AD4
569
570 #define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AD8
571
572 #define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46ADC
573
574 #define mmTPC5_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF46AE0
575
576 #define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AE4
577
578 #define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AE8
579
580 #define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AEC
581
582 #define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AF0
583
584 #define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AF4
585
586 #define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46AF8
587
588 #define mmTPC5_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF46AFC
589
590 #define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46B00
591
592 #define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46B04
593
594 #define mmTPC5_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF46B08
595
596 #define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46B0C
597
598 #define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46B10
599
600 #define mmTPC5_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF46B14
601
602 #define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46B18
603
604 #define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46B1C
605
606 #define mmTPC5_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF46B20
607
608 #define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46B24
609
610 #define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46B28
611
612 #define mmTPC5_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF46B2C
613
614 #define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46B30
615
616 #define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46B34
617
618 #define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46B38
619
620 #define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46B3C
621
622 #define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46B40
623
624 #define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46B44
625
626 #define mmTPC5_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF46B48
627
628 #define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46B4C
629
630 #define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46B50
631
632 #define mmTPC5_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF46B54
633
634 #define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B58
635
636 #define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B5C
637
638 #define mmTPC5_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF46B60
639
640 #define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B64
641
642 #define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B68
643
644 #define mmTPC5_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF46B6C
645
646 #define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B70
647
648 #define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B74
649
650 #define mmTPC5_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF46B78
651
652 #define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B7C
653
654 #define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B80
655
656 #define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B84
657
658 #define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B88
659
660 #define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B8C
661
662 #define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B90
663
664 #define mmTPC5_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF46B94
665
666 #define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B98
667
668 #define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B9C
669
670 #define mmTPC5_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF46BA0
671
672 #define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46BA4
673
674 #define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46BA8
675
676 #define mmTPC5_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF46BAC
677
678 #define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46BB0
679
680 #define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46BB4
681
682 #define mmTPC5_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF46BB8
683
684 #define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46BBC
685
686 #define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46BC0
687
688 #define mmTPC5_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF46BC4
689
690 #define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46BC8
691
692 #define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46BCC
693
694 #define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46BD0
695
696 #define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46BD4
697
698 #define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46BD8
699
700 #define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46BDC
701
702 #define mmTPC5_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF46BE0
703
704 #define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46BE4
705
706 #define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46BE8
707
708 #define mmTPC5_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF46BEC
709
710 #define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46BF0
711
712 #define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46BF4
713
714 #define mmTPC5_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF46BF8
715
716 #define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46BFC
717
718 #define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46C00
719
720 #define mmTPC5_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF46C04
721
722 #define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46C08
723
724 #define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46C0C
725
726 #define mmTPC5_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF46C10
727
728 #define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46C14
729
730 #define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46C18
731
732 #define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46C1C
733
734 #define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46C20
735
736 #define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46C24
737
738 #define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46C28
739
740 #define mmTPC5_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF46C2C
741
742 #define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46C30
743
744 #define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46C34
745
746 #define mmTPC5_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF46C38
747
748 #define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46C3C
749
750 #define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46C40
751
752 #define mmTPC5_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF46C44
753
754 #define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46C48
755
756 #define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46C4C
757
758 #define mmTPC5_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF46C50
759
760 #define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46C54
761
762 #define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46C58
763
764 #define mmTPC5_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF46C5C
765
766 #define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46C60
767
768 #define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46C64
769
770 #define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46C68
771
772 #define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46C6C
773
774 #define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46C70
775
776 #define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46C74
777
778 #define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46C78
779
780 #define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46C7C
781
782 #define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46C80
783
784 #define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46C84
785
786 #define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46C88
787
788 #define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46C8C
789
790 #define mmTPC5_CFG_QM_SRF_0 0xF46C90
791
792 #define mmTPC5_CFG_QM_SRF_1 0xF46C94
793
794 #define mmTPC5_CFG_QM_SRF_2 0xF46C98
795
796 #define mmTPC5_CFG_QM_SRF_3 0xF46C9C
797
798 #define mmTPC5_CFG_QM_SRF_4 0xF46CA0
799
800 #define mmTPC5_CFG_QM_SRF_5 0xF46CA4
801
802 #define mmTPC5_CFG_QM_SRF_6 0xF46CA8
803
804 #define mmTPC5_CFG_QM_SRF_7 0xF46CAC
805
806 #define mmTPC5_CFG_QM_SRF_8 0xF46CB0
807
808 #define mmTPC5_CFG_QM_SRF_9 0xF46CB4
809
810 #define mmTPC5_CFG_QM_SRF_10 0xF46CB8
811
812 #define mmTPC5_CFG_QM_SRF_11 0xF46CBC
813
814 #define mmTPC5_CFG_QM_SRF_12 0xF46CC0
815
816 #define mmTPC5_CFG_QM_SRF_13 0xF46CC4
817
818 #define mmTPC5_CFG_QM_SRF_14 0xF46CC8
819
820 #define mmTPC5_CFG_QM_SRF_15 0xF46CCC
821
822 #define mmTPC5_CFG_QM_SRF_16 0xF46CD0
823
824 #define mmTPC5_CFG_QM_SRF_17 0xF46CD4
825
826 #define mmTPC5_CFG_QM_SRF_18 0xF46CD8
827
828 #define mmTPC5_CFG_QM_SRF_19 0xF46CDC
829
830 #define mmTPC5_CFG_QM_SRF_20 0xF46CE0
831
832 #define mmTPC5_CFG_QM_SRF_21 0xF46CE4
833
834 #define mmTPC5_CFG_QM_SRF_22 0xF46CE8
835
836 #define mmTPC5_CFG_QM_SRF_23 0xF46CEC
837
838 #define mmTPC5_CFG_QM_SRF_24 0xF46CF0
839
840 #define mmTPC5_CFG_QM_SRF_25 0xF46CF4
841
842 #define mmTPC5_CFG_QM_SRF_26 0xF46CF8
843
844 #define mmTPC5_CFG_QM_SRF_27 0xF46CFC
845
846 #define mmTPC5_CFG_QM_SRF_28 0xF46D00
847
848 #define mmTPC5_CFG_QM_SRF_29 0xF46D04
849
850 #define mmTPC5_CFG_QM_SRF_30 0xF46D08
851
852 #define mmTPC5_CFG_QM_SRF_31 0xF46D0C
853
854 #define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46D10
855
856 #define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D14
857
858 #define mmTPC5_CFG_ARUSER 0xF46D18
859
860 #define mmTPC5_CFG_AWUSER 0xF46D1C
861
862 #define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF46E00
863
864 #define mmTPC5_CFG_FUNC_MBIST_PAT 0xF46E04
865
866 #define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF46E08
867
868 #define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF46E0C
869
870 #define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF46E10
871
872 #define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF46E14
873
874 #define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF46E18
875
876 #define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF46E1C
877
878 #define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF46E20
879
880 #define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF46E24
881
882 #define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF46E28
883
884 #define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF46E2C
885
886 #endif