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13 #ifndef ASIC_REG_TPC2_CFG_REGS_H_
14 #define ASIC_REG_TPC2_CFG_REGS_H_
15
16
17
18
19
20
21
22 #define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400
23
24 #define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404
25
26 #define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408
27
28 #define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C
29
30 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410
31
32 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414
33
34 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE86418
35
36 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE8641C
37
38 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE86420
39
40 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE86424
41
42 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86428
43
44 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE8642C
45
46 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE86430
47
48 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86434
49
50 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE86438
51
52 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE8643C
53
54 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86440
55
56 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86444
57
58 #define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE86448
59
60 #define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE8644C
61
62 #define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE86450
63
64 #define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86454
65
66 #define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86458
67
68 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE8645C
69
70 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE86460
71
72 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE86464
73
74 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86468
75
76 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE8646C
77
78 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE86470
79
80 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86474
81
82 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE86478
83
84 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE8647C
85
86 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86480
87
88 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86484
89
90 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE86488
91
92 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE8648C
93
94 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE86490
95
96 #define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE86494
97
98 #define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86498
99
100 #define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE8649C
101
102 #define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE864A0
103
104 #define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE864A4
105
106 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE864A8
107
108 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE864AC
109
110 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE864B0
111
112 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE864B4
113
114 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE864B8
115
116 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE864BC
117
118 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE864C0
119
120 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE864C4
121
122 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE864C8
123
124 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE864CC
125
126 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE864D0
127
128 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE864D4
129
130 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864D8
131
132 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864DC
133
134 #define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE864E0
135
136 #define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864E4
137
138 #define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864E8
139
140 #define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864EC
141
142 #define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864F0
143
144 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864F4
145
146 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864F8
147
148 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE864FC
149
150 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE86500
151
152 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE86504
153
154 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE86508
155
156 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE8650C
157
158 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE86510
159
160 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE86514
161
162 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE86518
163
164 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE8651C
165
166 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE86520
167
168 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE86524
169
170 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE86528
171
172 #define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE8652C
173
174 #define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE86530
175
176 #define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE86534
177
178 #define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE86538
179
180 #define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE8653C
181
182 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE86540
183
184 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE86544
185
186 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE86548
187
188 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE8654C
189
190 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE86550
191
192 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE86554
193
194 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86558
195
196 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE8655C
197
198 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE86560
199
200 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86564
201
202 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE86568
203
204 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE8656C
205
206 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86570
207
208 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86574
209
210 #define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE86578
211
212 #define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE8657C
213
214 #define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE86580
215
216 #define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86584
217
218 #define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86588
219
220 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE8658C
221
222 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE86590
223
224 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE86594
225
226 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86598
227
228 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE8659C
229
230 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE865A0
231
232 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE865A4
233
234 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE865A8
235
236 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE865AC
237
238 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE865B0
239
240 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE865B4
241
242 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE865B8
243
244 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE865BC
245
246 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE865C0
247
248 #define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE865C4
249
250 #define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE865C8
251
252 #define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE865CC
253
254 #define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE865D0
255
256 #define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE865D4
257
258 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE865D8
259
260 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE865DC
261
262 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE865E0
263
264 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE865E4
265
266 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE865E8
267
268 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE865EC
269
270 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE865F0
271
272 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE865F4
273
274 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE865F8
275
276 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE865FC
277
278 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE86600
279
280 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE86604
281
282 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86608
283
284 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE8660C
285
286 #define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE86610
287
288 #define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86614
289
290 #define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE86618
291
292 #define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE8661C
293
294 #define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86620
295
296 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86624
297
298 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE86628
299
300 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE8662C
301
302 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE86630
303
304 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE86634
305
306 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE86638
307
308 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE8663C
309
310 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE86640
311
312 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE86644
313
314 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE86648
315
316 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE8664C
317
318 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE86650
319
320 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE86654
321
322 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE86658
323
324 #define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE8665C
325
326 #define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86660
327
328 #define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE86664
329
330 #define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86668
331
332 #define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE8666C
333
334 #define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86670
335
336 #define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE86674
337
338 #define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE86678
339
340 #define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE8667C
341
342 #define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE86680
343
344 #define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE86684
345
346 #define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE86688
347
348 #define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE8668C
349
350 #define mmTPC2_CFG_KERNEL_SRF_0 0xE86690
351
352 #define mmTPC2_CFG_KERNEL_SRF_1 0xE86694
353
354 #define mmTPC2_CFG_KERNEL_SRF_2 0xE86698
355
356 #define mmTPC2_CFG_KERNEL_SRF_3 0xE8669C
357
358 #define mmTPC2_CFG_KERNEL_SRF_4 0xE866A0
359
360 #define mmTPC2_CFG_KERNEL_SRF_5 0xE866A4
361
362 #define mmTPC2_CFG_KERNEL_SRF_6 0xE866A8
363
364 #define mmTPC2_CFG_KERNEL_SRF_7 0xE866AC
365
366 #define mmTPC2_CFG_KERNEL_SRF_8 0xE866B0
367
368 #define mmTPC2_CFG_KERNEL_SRF_9 0xE866B4
369
370 #define mmTPC2_CFG_KERNEL_SRF_10 0xE866B8
371
372 #define mmTPC2_CFG_KERNEL_SRF_11 0xE866BC
373
374 #define mmTPC2_CFG_KERNEL_SRF_12 0xE866C0
375
376 #define mmTPC2_CFG_KERNEL_SRF_13 0xE866C4
377
378 #define mmTPC2_CFG_KERNEL_SRF_14 0xE866C8
379
380 #define mmTPC2_CFG_KERNEL_SRF_15 0xE866CC
381
382 #define mmTPC2_CFG_KERNEL_SRF_16 0xE866D0
383
384 #define mmTPC2_CFG_KERNEL_SRF_17 0xE866D4
385
386 #define mmTPC2_CFG_KERNEL_SRF_18 0xE866D8
387
388 #define mmTPC2_CFG_KERNEL_SRF_19 0xE866DC
389
390 #define mmTPC2_CFG_KERNEL_SRF_20 0xE866E0
391
392 #define mmTPC2_CFG_KERNEL_SRF_21 0xE866E4
393
394 #define mmTPC2_CFG_KERNEL_SRF_22 0xE866E8
395
396 #define mmTPC2_CFG_KERNEL_SRF_23 0xE866EC
397
398 #define mmTPC2_CFG_KERNEL_SRF_24 0xE866F0
399
400 #define mmTPC2_CFG_KERNEL_SRF_25 0xE866F4
401
402 #define mmTPC2_CFG_KERNEL_SRF_26 0xE866F8
403
404 #define mmTPC2_CFG_KERNEL_SRF_27 0xE866FC
405
406 #define mmTPC2_CFG_KERNEL_SRF_28 0xE86700
407
408 #define mmTPC2_CFG_KERNEL_SRF_29 0xE86704
409
410 #define mmTPC2_CFG_KERNEL_SRF_30 0xE86708
411
412 #define mmTPC2_CFG_KERNEL_SRF_31 0xE8670C
413
414 #define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE86710
415
416 #define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86714
417
418 #define mmTPC2_CFG_RESERVED_DESC_END 0xE86738
419
420 #define mmTPC2_CFG_ROUND_CSR 0xE867FC
421
422 #define mmTPC2_CFG_TBUF_BASE_ADDR_LOW 0xE86800
423
424 #define mmTPC2_CFG_TBUF_BASE_ADDR_HIGH 0xE86804
425
426 #define mmTPC2_CFG_SEMAPHORE 0xE86808
427
428 #define mmTPC2_CFG_VFLAGS 0xE8680C
429
430 #define mmTPC2_CFG_SFLAGS 0xE86810
431
432 #define mmTPC2_CFG_LFSR_POLYNOM 0xE86818
433
434 #define mmTPC2_CFG_STATUS 0xE8681C
435
436 #define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86820
437
438 #define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86824
439
440 #define mmTPC2_CFG_SM_BASE_ADDRESS_LOW 0xE86828
441
442 #define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8682C
443
444 #define mmTPC2_CFG_TPC_CMD 0xE86830
445
446 #define mmTPC2_CFG_TPC_EXECUTE 0xE86838
447
448 #define mmTPC2_CFG_TPC_STALL 0xE8683C
449
450 #define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86840
451
452 #define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86844
453
454 #define mmTPC2_CFG_MSS_CONFIG 0xE86854
455
456 #define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86858
457
458 #define mmTPC2_CFG_TPC_INTR_MASK 0xE8685C
459
460 #define mmTPC2_CFG_TSB_CONFIG 0xE86860
461
462 #define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00
463
464 #define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04
465
466 #define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08
467
468 #define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C
469
470 #define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10
471
472 #define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14
473
474 #define mmTPC2_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE86A18
475
476 #define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A1C
477
478 #define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A20
479
480 #define mmTPC2_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE86A24
481
482 #define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A28
483
484 #define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A2C
485
486 #define mmTPC2_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE86A30
487
488 #define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A34
489
490 #define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A38
491
492 #define mmTPC2_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE86A3C
493
494 #define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A40
495
496 #define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A44
497
498 #define mmTPC2_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE86A48
499
500 #define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A4C
501
502 #define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A50
503
504 #define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A54
505
506 #define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A58
507
508 #define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A5C
509
510 #define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A60
511
512 #define mmTPC2_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE86A64
513
514 #define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A68
515
516 #define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A6C
517
518 #define mmTPC2_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE86A70
519
520 #define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A74
521
522 #define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A78
523
524 #define mmTPC2_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE86A7C
525
526 #define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A80
527
528 #define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A84
529
530 #define mmTPC2_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE86A88
531
532 #define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A8C
533
534 #define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A90
535
536 #define mmTPC2_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE86A94
537
538 #define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A98
539
540 #define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A9C
541
542 #define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86AA0
543
544 #define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86AA4
545
546 #define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86AA8
547
548 #define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86AAC
549
550 #define mmTPC2_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE86AB0
551
552 #define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86AB4
553
554 #define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86AB8
555
556 #define mmTPC2_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE86ABC
557
558 #define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86AC0
559
560 #define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86AC4
561
562 #define mmTPC2_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE86AC8
563
564 #define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86ACC
565
566 #define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86AD0
567
568 #define mmTPC2_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE86AD4
569
570 #define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AD8
571
572 #define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86ADC
573
574 #define mmTPC2_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE86AE0
575
576 #define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AE4
577
578 #define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AE8
579
580 #define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AEC
581
582 #define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AF0
583
584 #define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AF4
585
586 #define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86AF8
587
588 #define mmTPC2_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE86AFC
589
590 #define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86B00
591
592 #define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86B04
593
594 #define mmTPC2_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE86B08
595
596 #define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86B0C
597
598 #define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86B10
599
600 #define mmTPC2_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE86B14
601
602 #define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86B18
603
604 #define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86B1C
605
606 #define mmTPC2_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE86B20
607
608 #define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86B24
609
610 #define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86B28
611
612 #define mmTPC2_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE86B2C
613
614 #define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86B30
615
616 #define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86B34
617
618 #define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86B38
619
620 #define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86B3C
621
622 #define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86B40
623
624 #define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86B44
625
626 #define mmTPC2_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE86B48
627
628 #define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86B4C
629
630 #define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86B50
631
632 #define mmTPC2_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE86B54
633
634 #define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B58
635
636 #define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B5C
637
638 #define mmTPC2_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE86B60
639
640 #define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B64
641
642 #define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B68
643
644 #define mmTPC2_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE86B6C
645
646 #define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B70
647
648 #define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B74
649
650 #define mmTPC2_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE86B78
651
652 #define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B7C
653
654 #define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B80
655
656 #define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B84
657
658 #define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B88
659
660 #define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B8C
661
662 #define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B90
663
664 #define mmTPC2_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE86B94
665
666 #define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B98
667
668 #define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B9C
669
670 #define mmTPC2_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE86BA0
671
672 #define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86BA4
673
674 #define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86BA8
675
676 #define mmTPC2_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE86BAC
677
678 #define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86BB0
679
680 #define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86BB4
681
682 #define mmTPC2_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE86BB8
683
684 #define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86BBC
685
686 #define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86BC0
687
688 #define mmTPC2_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE86BC4
689
690 #define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86BC8
691
692 #define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86BCC
693
694 #define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86BD0
695
696 #define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86BD4
697
698 #define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86BD8
699
700 #define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86BDC
701
702 #define mmTPC2_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE86BE0
703
704 #define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86BE4
705
706 #define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86BE8
707
708 #define mmTPC2_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE86BEC
709
710 #define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86BF0
711
712 #define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86BF4
713
714 #define mmTPC2_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE86BF8
715
716 #define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86BFC
717
718 #define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86C00
719
720 #define mmTPC2_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE86C04
721
722 #define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86C08
723
724 #define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86C0C
725
726 #define mmTPC2_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE86C10
727
728 #define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86C14
729
730 #define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86C18
731
732 #define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86C1C
733
734 #define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86C20
735
736 #define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86C24
737
738 #define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86C28
739
740 #define mmTPC2_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE86C2C
741
742 #define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86C30
743
744 #define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86C34
745
746 #define mmTPC2_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE86C38
747
748 #define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86C3C
749
750 #define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86C40
751
752 #define mmTPC2_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE86C44
753
754 #define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86C48
755
756 #define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86C4C
757
758 #define mmTPC2_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE86C50
759
760 #define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86C54
761
762 #define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86C58
763
764 #define mmTPC2_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE86C5C
765
766 #define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86C60
767
768 #define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86C64
769
770 #define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86C68
771
772 #define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86C6C
773
774 #define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86C70
775
776 #define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86C74
777
778 #define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86C78
779
780 #define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86C7C
781
782 #define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86C80
783
784 #define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86C84
785
786 #define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86C88
787
788 #define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86C8C
789
790 #define mmTPC2_CFG_QM_SRF_0 0xE86C90
791
792 #define mmTPC2_CFG_QM_SRF_1 0xE86C94
793
794 #define mmTPC2_CFG_QM_SRF_2 0xE86C98
795
796 #define mmTPC2_CFG_QM_SRF_3 0xE86C9C
797
798 #define mmTPC2_CFG_QM_SRF_4 0xE86CA0
799
800 #define mmTPC2_CFG_QM_SRF_5 0xE86CA4
801
802 #define mmTPC2_CFG_QM_SRF_6 0xE86CA8
803
804 #define mmTPC2_CFG_QM_SRF_7 0xE86CAC
805
806 #define mmTPC2_CFG_QM_SRF_8 0xE86CB0
807
808 #define mmTPC2_CFG_QM_SRF_9 0xE86CB4
809
810 #define mmTPC2_CFG_QM_SRF_10 0xE86CB8
811
812 #define mmTPC2_CFG_QM_SRF_11 0xE86CBC
813
814 #define mmTPC2_CFG_QM_SRF_12 0xE86CC0
815
816 #define mmTPC2_CFG_QM_SRF_13 0xE86CC4
817
818 #define mmTPC2_CFG_QM_SRF_14 0xE86CC8
819
820 #define mmTPC2_CFG_QM_SRF_15 0xE86CCC
821
822 #define mmTPC2_CFG_QM_SRF_16 0xE86CD0
823
824 #define mmTPC2_CFG_QM_SRF_17 0xE86CD4
825
826 #define mmTPC2_CFG_QM_SRF_18 0xE86CD8
827
828 #define mmTPC2_CFG_QM_SRF_19 0xE86CDC
829
830 #define mmTPC2_CFG_QM_SRF_20 0xE86CE0
831
832 #define mmTPC2_CFG_QM_SRF_21 0xE86CE4
833
834 #define mmTPC2_CFG_QM_SRF_22 0xE86CE8
835
836 #define mmTPC2_CFG_QM_SRF_23 0xE86CEC
837
838 #define mmTPC2_CFG_QM_SRF_24 0xE86CF0
839
840 #define mmTPC2_CFG_QM_SRF_25 0xE86CF4
841
842 #define mmTPC2_CFG_QM_SRF_26 0xE86CF8
843
844 #define mmTPC2_CFG_QM_SRF_27 0xE86CFC
845
846 #define mmTPC2_CFG_QM_SRF_28 0xE86D00
847
848 #define mmTPC2_CFG_QM_SRF_29 0xE86D04
849
850 #define mmTPC2_CFG_QM_SRF_30 0xE86D08
851
852 #define mmTPC2_CFG_QM_SRF_31 0xE86D0C
853
854 #define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86D10
855
856 #define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D14
857
858 #define mmTPC2_CFG_ARUSER 0xE86D18
859
860 #define mmTPC2_CFG_AWUSER 0xE86D1C
861
862 #define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE86E00
863
864 #define mmTPC2_CFG_FUNC_MBIST_PAT 0xE86E04
865
866 #define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE86E08
867
868 #define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE86E0C
869
870 #define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE86E10
871
872 #define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE86E14
873
874 #define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE86E18
875
876 #define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE86E1C
877
878 #define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE86E20
879
880 #define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE86E24
881
882 #define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE86E28
883
884 #define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE86E2C
885
886 #endif