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8 #ifndef GOYA_CORESIGHT_H
9 #define GOYA_CORESIGHT_H
10
11 enum goya_debug_stm_regs_index {
12 GOYA_STM_FIRST = 0,
13 GOYA_STM_CPU = GOYA_STM_FIRST,
14 GOYA_STM_DMA_CH_0_CS,
15 GOYA_STM_DMA_CH_1_CS,
16 GOYA_STM_DMA_CH_2_CS,
17 GOYA_STM_DMA_CH_3_CS,
18 GOYA_STM_DMA_CH_4_CS,
19 GOYA_STM_DMA_MACRO_CS,
20 GOYA_STM_MME1_SBA,
21 GOYA_STM_MME3_SBB,
22 GOYA_STM_MME4_WACS2,
23 GOYA_STM_MME4_WACS,
24 GOYA_STM_MMU_CS,
25 GOYA_STM_PCIE,
26 GOYA_STM_PSOC,
27 GOYA_STM_TPC0_EML,
28 GOYA_STM_TPC1_EML,
29 GOYA_STM_TPC2_EML,
30 GOYA_STM_TPC3_EML,
31 GOYA_STM_TPC4_EML,
32 GOYA_STM_TPC5_EML,
33 GOYA_STM_TPC6_EML,
34 GOYA_STM_TPC7_EML,
35 GOYA_STM_LAST = GOYA_STM_TPC7_EML
36 };
37
38 enum goya_debug_etf_regs_index {
39 GOYA_ETF_FIRST = 0,
40 GOYA_ETF_CPU_0 = GOYA_ETF_FIRST,
41 GOYA_ETF_CPU_1,
42 GOYA_ETF_CPU_TRACE,
43 GOYA_ETF_DMA_CH_0_CS,
44 GOYA_ETF_DMA_CH_1_CS,
45 GOYA_ETF_DMA_CH_2_CS,
46 GOYA_ETF_DMA_CH_3_CS,
47 GOYA_ETF_DMA_CH_4_CS,
48 GOYA_ETF_DMA_MACRO_CS,
49 GOYA_ETF_MME1_SBA,
50 GOYA_ETF_MME3_SBB,
51 GOYA_ETF_MME4_WACS2,
52 GOYA_ETF_MME4_WACS,
53 GOYA_ETF_MMU_CS,
54 GOYA_ETF_PCIE,
55 GOYA_ETF_PSOC,
56 GOYA_ETF_TPC0_EML,
57 GOYA_ETF_TPC1_EML,
58 GOYA_ETF_TPC2_EML,
59 GOYA_ETF_TPC3_EML,
60 GOYA_ETF_TPC4_EML,
61 GOYA_ETF_TPC5_EML,
62 GOYA_ETF_TPC6_EML,
63 GOYA_ETF_TPC7_EML,
64 GOYA_ETF_LAST = GOYA_ETF_TPC7_EML
65 };
66
67 enum goya_debug_funnel_regs_index {
68 GOYA_FUNNEL_FIRST = 0,
69 GOYA_FUNNEL_CPU = GOYA_FUNNEL_FIRST,
70 GOYA_FUNNEL_DMA_CH_6_1,
71 GOYA_FUNNEL_DMA_MACRO_3_1,
72 GOYA_FUNNEL_MME0_RTR,
73 GOYA_FUNNEL_MME1_RTR,
74 GOYA_FUNNEL_MME2_RTR,
75 GOYA_FUNNEL_MME3_RTR,
76 GOYA_FUNNEL_MME4_RTR,
77 GOYA_FUNNEL_MME5_RTR,
78 GOYA_FUNNEL_PCIE,
79 GOYA_FUNNEL_PSOC,
80 GOYA_FUNNEL_TPC0_EML,
81 GOYA_FUNNEL_TPC1_EML,
82 GOYA_FUNNEL_TPC1_RTR,
83 GOYA_FUNNEL_TPC2_EML,
84 GOYA_FUNNEL_TPC2_RTR,
85 GOYA_FUNNEL_TPC3_EML,
86 GOYA_FUNNEL_TPC3_RTR,
87 GOYA_FUNNEL_TPC4_EML,
88 GOYA_FUNNEL_TPC4_RTR,
89 GOYA_FUNNEL_TPC5_EML,
90 GOYA_FUNNEL_TPC5_RTR,
91 GOYA_FUNNEL_TPC6_EML,
92 GOYA_FUNNEL_TPC6_RTR,
93 GOYA_FUNNEL_TPC7_EML,
94 GOYA_FUNNEL_LAST = GOYA_FUNNEL_TPC7_EML
95 };
96
97 enum goya_debug_bmon_regs_index {
98 GOYA_BMON_FIRST = 0,
99 GOYA_BMON_CPU_RD = GOYA_BMON_FIRST,
100 GOYA_BMON_CPU_WR,
101 GOYA_BMON_DMA_CH_0_0,
102 GOYA_BMON_DMA_CH_0_1,
103 GOYA_BMON_DMA_CH_1_0,
104 GOYA_BMON_DMA_CH_1_1,
105 GOYA_BMON_DMA_CH_2_0,
106 GOYA_BMON_DMA_CH_2_1,
107 GOYA_BMON_DMA_CH_3_0,
108 GOYA_BMON_DMA_CH_3_1,
109 GOYA_BMON_DMA_CH_4_0,
110 GOYA_BMON_DMA_CH_4_1,
111 GOYA_BMON_DMA_MACRO_0,
112 GOYA_BMON_DMA_MACRO_1,
113 GOYA_BMON_DMA_MACRO_2,
114 GOYA_BMON_DMA_MACRO_3,
115 GOYA_BMON_DMA_MACRO_4,
116 GOYA_BMON_DMA_MACRO_5,
117 GOYA_BMON_DMA_MACRO_6,
118 GOYA_BMON_DMA_MACRO_7,
119 GOYA_BMON_MME1_SBA_0,
120 GOYA_BMON_MME1_SBA_1,
121 GOYA_BMON_MME3_SBB_0,
122 GOYA_BMON_MME3_SBB_1,
123 GOYA_BMON_MME4_WACS2_0,
124 GOYA_BMON_MME4_WACS2_1,
125 GOYA_BMON_MME4_WACS2_2,
126 GOYA_BMON_MME4_WACS_0,
127 GOYA_BMON_MME4_WACS_1,
128 GOYA_BMON_MME4_WACS_2,
129 GOYA_BMON_MME4_WACS_3,
130 GOYA_BMON_MME4_WACS_4,
131 GOYA_BMON_MME4_WACS_5,
132 GOYA_BMON_MME4_WACS_6,
133 GOYA_BMON_MMU_0,
134 GOYA_BMON_MMU_1,
135 GOYA_BMON_PCIE_MSTR_RD,
136 GOYA_BMON_PCIE_MSTR_WR,
137 GOYA_BMON_PCIE_SLV_RD,
138 GOYA_BMON_PCIE_SLV_WR,
139 GOYA_BMON_TPC0_EML_0,
140 GOYA_BMON_TPC0_EML_1,
141 GOYA_BMON_TPC0_EML_2,
142 GOYA_BMON_TPC0_EML_3,
143 GOYA_BMON_TPC1_EML_0,
144 GOYA_BMON_TPC1_EML_1,
145 GOYA_BMON_TPC1_EML_2,
146 GOYA_BMON_TPC1_EML_3,
147 GOYA_BMON_TPC2_EML_0,
148 GOYA_BMON_TPC2_EML_1,
149 GOYA_BMON_TPC2_EML_2,
150 GOYA_BMON_TPC2_EML_3,
151 GOYA_BMON_TPC3_EML_0,
152 GOYA_BMON_TPC3_EML_1,
153 GOYA_BMON_TPC3_EML_2,
154 GOYA_BMON_TPC3_EML_3,
155 GOYA_BMON_TPC4_EML_0,
156 GOYA_BMON_TPC4_EML_1,
157 GOYA_BMON_TPC4_EML_2,
158 GOYA_BMON_TPC4_EML_3,
159 GOYA_BMON_TPC5_EML_0,
160 GOYA_BMON_TPC5_EML_1,
161 GOYA_BMON_TPC5_EML_2,
162 GOYA_BMON_TPC5_EML_3,
163 GOYA_BMON_TPC6_EML_0,
164 GOYA_BMON_TPC6_EML_1,
165 GOYA_BMON_TPC6_EML_2,
166 GOYA_BMON_TPC6_EML_3,
167 GOYA_BMON_TPC7_EML_0,
168 GOYA_BMON_TPC7_EML_1,
169 GOYA_BMON_TPC7_EML_2,
170 GOYA_BMON_TPC7_EML_3,
171 GOYA_BMON_LAST = GOYA_BMON_TPC7_EML_3
172 };
173
174 enum goya_debug_spmu_regs_index {
175 GOYA_SPMU_FIRST = 0,
176 GOYA_SPMU_DMA_CH_0_CS = GOYA_SPMU_FIRST,
177 GOYA_SPMU_DMA_CH_1_CS,
178 GOYA_SPMU_DMA_CH_2_CS,
179 GOYA_SPMU_DMA_CH_3_CS,
180 GOYA_SPMU_DMA_CH_4_CS,
181 GOYA_SPMU_DMA_MACRO_CS,
182 GOYA_SPMU_MME1_SBA,
183 GOYA_SPMU_MME3_SBB,
184 GOYA_SPMU_MME4_WACS2,
185 GOYA_SPMU_MME4_WACS,
186 GOYA_SPMU_MMU_CS,
187 GOYA_SPMU_PCIE,
188 GOYA_SPMU_TPC0_EML,
189 GOYA_SPMU_TPC1_EML,
190 GOYA_SPMU_TPC2_EML,
191 GOYA_SPMU_TPC3_EML,
192 GOYA_SPMU_TPC4_EML,
193 GOYA_SPMU_TPC5_EML,
194 GOYA_SPMU_TPC6_EML,
195 GOYA_SPMU_TPC7_EML,
196 GOYA_SPMU_LAST = GOYA_SPMU_TPC7_EML
197 };
198
199 #endif