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8 #ifndef GOYAP_H_
9 #define GOYAP_H_
10
11 #include <uapi/misc/habanalabs.h>
12 #include "habanalabs.h"
13 #include "include/hl_boot_if.h"
14 #include "include/goya/goya_packets.h"
15 #include "include/goya/goya.h"
16 #include "include/goya/goya_async_events.h"
17 #include "include/goya/goya_fw_if.h"
18
19 #define NUMBER_OF_CMPLT_QUEUES 5
20 #define NUMBER_OF_EXT_HW_QUEUES 5
21 #define NUMBER_OF_CPU_HW_QUEUES 1
22 #define NUMBER_OF_INT_HW_QUEUES 9
23 #define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
24 NUMBER_OF_CPU_HW_QUEUES + \
25 NUMBER_OF_INT_HW_QUEUES)
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30
31
32 #define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + 1)
33
34 #if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
35 #error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
36 #endif
37
38 #if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
39 #error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
40 #endif
41
42 #define QMAN_FENCE_TIMEOUT_USEC 10000
43
44 #define QMAN_STOP_TIMEOUT_USEC 100000
45
46 #define CORESIGHT_TIMEOUT_USEC 100000
47
48 #define GOYA_CPU_TIMEOUT_USEC 10000000
49
50 #define TPC_ENABLED_MASK 0xFF
51
52 #define PLL_HIGH_DEFAULT 1575000000
53
54 #define MAX_POWER_DEFAULT 200000
55
56 #define DRAM_PHYS_DEFAULT_SIZE 0x100000000ull
57
58 #define GOYA_DEFAULT_CARD_NAME "HL1000"
59
60
61
62 #define CPU_FW_IMAGE_SIZE 0x10000000
63 #define MMU_PAGE_TABLES_SIZE 0x0FC00000
64 #define MMU_DRAM_DEFAULT_PAGE_SIZE 0x00200000
65 #define MMU_CACHE_MNG_SIZE 0x00001000
66
67 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
68 #define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
69 #define MMU_DRAM_DEFAULT_PAGE_ADDR (MMU_PAGE_TABLES_ADDR + \
70 MMU_PAGE_TABLES_SIZE)
71 #define MMU_CACHE_MNG_ADDR (MMU_DRAM_DEFAULT_PAGE_ADDR + \
72 MMU_DRAM_DEFAULT_PAGE_SIZE)
73 #define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + \
74 MMU_CACHE_MNG_SIZE)
75
76 #define DRAM_BASE_ADDR_USER 0x20000000
77
78 #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
79 #error "Driver must reserve no more than 512MB"
80 #endif
81
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89
90 #define MME_QMAN_BASE_OFFSET 0x000000
91 #define MME_QMAN_LENGTH 64
92 #define TPC_QMAN_LENGTH 64
93
94 #define TPC0_QMAN_BASE_OFFSET (MME_QMAN_BASE_OFFSET + \
95 (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
96 #define TPC1_QMAN_BASE_OFFSET (TPC0_QMAN_BASE_OFFSET + \
97 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
98 #define TPC2_QMAN_BASE_OFFSET (TPC1_QMAN_BASE_OFFSET + \
99 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
100 #define TPC3_QMAN_BASE_OFFSET (TPC2_QMAN_BASE_OFFSET + \
101 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
102 #define TPC4_QMAN_BASE_OFFSET (TPC3_QMAN_BASE_OFFSET + \
103 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
104 #define TPC5_QMAN_BASE_OFFSET (TPC4_QMAN_BASE_OFFSET + \
105 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
106 #define TPC6_QMAN_BASE_OFFSET (TPC5_QMAN_BASE_OFFSET + \
107 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
108 #define TPC7_QMAN_BASE_OFFSET (TPC6_QMAN_BASE_OFFSET + \
109 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
110
111 #define SRAM_DRIVER_RES_OFFSET (TPC7_QMAN_BASE_OFFSET + \
112 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
113
114 #if (SRAM_DRIVER_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
115 #error "MME/TPC QMANs SRAM space exceeds limit"
116 #endif
117
118 #define SRAM_USER_BASE_OFFSET GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
119
120
121 #define VA_HOST_SPACE_START 0x1000000000000ull
122 #define VA_HOST_SPACE_END 0x3FF8000000000ull
123 #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
124 VA_HOST_SPACE_START)
125
126 #define VA_DDR_SPACE_START 0x800000000ull
127 #define VA_DDR_SPACE_END 0x2000000000ull
128 #define VA_DDR_SPACE_SIZE (VA_DDR_SPACE_END - \
129 VA_DDR_SPACE_START)
130
131 #if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
132 #error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
133 #endif
134
135 #define VA_CPU_ACCESSIBLE_MEM_ADDR 0x8000000000ull
136
137 #define DMA_MAX_TRANSFER_SIZE U32_MAX
138
139 #define HW_CAP_PLL 0x00000001
140 #define HW_CAP_DDR_0 0x00000002
141 #define HW_CAP_DDR_1 0x00000004
142 #define HW_CAP_MME 0x00000008
143 #define HW_CAP_CPU 0x00000010
144 #define HW_CAP_DMA 0x00000020
145 #define HW_CAP_MSIX 0x00000040
146 #define HW_CAP_CPU_Q 0x00000080
147 #define HW_CAP_MMU 0x00000100
148 #define HW_CAP_TPC_MBIST 0x00000200
149 #define HW_CAP_GOLDEN 0x00000400
150 #define HW_CAP_TPC 0x00000800
151
152 enum goya_fw_component {
153 FW_COMP_UBOOT,
154 FW_COMP_PREBOOT
155 };
156
157 struct goya_device {
158
159 spinlock_t hw_queues_lock;
160
161 u64 mme_clk;
162 u64 tpc_clk;
163 u64 ic_clk;
164
165 u64 ddr_bar_cur_addr;
166 u32 events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
167 u32 events_stat_aggregate[GOYA_ASYNC_EVENT_ID_SIZE];
168 u32 hw_cap_initialized;
169 u8 device_cpu_mmu_mappings_done;
170 };
171
172 void goya_get_fixed_properties(struct hl_device *hdev);
173 int goya_mmu_init(struct hl_device *hdev);
174 void goya_init_dma_qmans(struct hl_device *hdev);
175 void goya_init_mme_qmans(struct hl_device *hdev);
176 void goya_init_tpc_qmans(struct hl_device *hdev);
177 int goya_init_cpu_queues(struct hl_device *hdev);
178 void goya_init_security(struct hl_device *hdev);
179 int goya_late_init(struct hl_device *hdev);
180 void goya_late_fini(struct hl_device *hdev);
181
182 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
183 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
184 void goya_update_eq_ci(struct hl_device *hdev, u32 val);
185 void goya_restore_phase_topology(struct hl_device *hdev);
186 int goya_context_switch(struct hl_device *hdev, u32 asid);
187
188 int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
189 u8 i2c_addr, u8 i2c_reg, u32 *val);
190 int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
191 u8 i2c_addr, u8 i2c_reg, u32 val);
192 void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
193
194 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
195 int goya_test_queues(struct hl_device *hdev);
196 int goya_test_cpu_queue(struct hl_device *hdev);
197 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
198 u32 timeout, long *result);
199
200 long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
201 long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
202 long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
203 long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
204 long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
205 void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
206 long value);
207 u64 goya_get_max_power(struct hl_device *hdev);
208 void goya_set_max_power(struct hl_device *hdev, u64 value);
209
210 void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
211 void goya_add_device_attr(struct hl_device *hdev,
212 struct attribute_group *dev_attr_grp);
213 int goya_armcp_info_get(struct hl_device *hdev);
214 int goya_debug_coresight(struct hl_device *hdev, void *data);
215 void goya_halt_coresight(struct hl_device *hdev);
216
217 int goya_suspend(struct hl_device *hdev);
218 int goya_resume(struct hl_device *hdev);
219
220 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
221 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size);
222
223 void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address,
224 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec);
225 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
226 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
227 dma_addr_t *dma_handle, u16 *queue_len);
228 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
229 int goya_send_heartbeat(struct hl_device *hdev);
230 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
231 dma_addr_t *dma_handle);
232 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
233 void *vaddr);
234 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
235
236 #endif