1 /*
2 * This file is provided under a GPLv2 license. When using or
3 * redistributing this file, you may do so under that license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, it can be found <http://www.gnu.org/licenses/>.
20 *
21 * The full GNU General Public License is included in this distribution in
22 * the file called "COPYING".
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * IDT PCIe-switch NTB Linux driver
37 *
38 * Contact Information:
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
40 */
41 /*
42 * NOTE of the IDT 89HPESx SMBus-slave interface driver
43 * This driver primarily is developed to have an access to EEPROM device of
44 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
45 * operations from/to EEPROM, which is located at private (so called Master)
46 * SMBus of switches. Using that interface this the driver creates a simple
47 * binary sysfs-file in the device directory:
48 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
49 * In case if read-only flag is specified in the dts-node of device desription,
50 * User-space applications won't be able to write to the EEPROM sysfs-node.
51 * Additionally IDT 89HPESx SMBus interface has an ability to write/read
52 * data of device CSRs. This driver exposes debugf-file to perform simple IO
53 * operations using that ability for just basic debug purpose. Particularly
54 * next file is created in the specific debugfs-directory:
55 * /sys/kernel/debug/idt_csr/
56 * Format of the debugfs-node is:
57 * $ cat /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>;
58 * <CSR address>:<CSR value>
59 * So reading the content of the file gives current CSR address and it value.
60 * If User-space application wishes to change current CSR address,
61 * it can just write a proper value to the sysfs-file:
62 * $ echo "<CSR address>" > /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>
63 * If it wants to change the CSR value as well, the format of the write
64 * operation is:
65 * $ echo "<CSR address>:<CSR value>" > \
66 * /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>;
67 * CSR address and value can be any of hexadecimal, decimal or octal format.
68 */
69
70 #include <linux/kernel.h>
71 #include <linux/init.h>
72 #include <linux/module.h>
73 #include <linux/types.h>
74 #include <linux/sizes.h>
75 #include <linux/slab.h>
76 #include <linux/mutex.h>
77 #include <linux/sysfs.h>
78 #include <linux/debugfs.h>
79 #include <linux/mod_devicetable.h>
80 #include <linux/property.h>
81 #include <linux/i2c.h>
82 #include <linux/pci_ids.h>
83 #include <linux/delay.h>
84
85 #define IDT_NAME "89hpesx"
86 #define IDT_89HPESX_DESC "IDT 89HPESx SMBus-slave interface driver"
87 #define IDT_89HPESX_VER "1.0"
88
89 MODULE_DESCRIPTION(IDT_89HPESX_DESC);
90 MODULE_VERSION(IDT_89HPESX_VER);
91 MODULE_LICENSE("GPL v2");
92 MODULE_AUTHOR("T-platforms");
93
94 /*
95 * csr_dbgdir - CSR read/write operations Debugfs directory
96 */
97 static struct dentry *csr_dbgdir;
98
99 /*
100 * struct idt_89hpesx_dev - IDT 89HPESx device data structure
101 * @eesize: Size of EEPROM in bytes (calculated from "idt,eecompatible")
102 * @eero: EEPROM Read-only flag
103 * @eeaddr: EEPROM custom address
104 *
105 * @inieecmd: Initial cmd value for EEPROM read/write operations
106 * @inicsrcmd: Initial cmd value for CSR read/write operations
107 * @iniccode: Initialial command code value for IO-operations
108 *
109 * @csr: CSR address to perform read operation
110 *
111 * @smb_write: SMBus write method
112 * @smb_read: SMBus read method
113 * @smb_mtx: SMBus mutex
114 *
115 * @client: i2c client used to perform IO operations
116 *
117 * @ee_file: EEPROM read/write sysfs-file
118 */
119 struct idt_smb_seq;
120 struct idt_89hpesx_dev {
121 u32 eesize;
122 bool eero;
123 u8 eeaddr;
124
125 u8 inieecmd;
126 u8 inicsrcmd;
127 u8 iniccode;
128
129 u16 csr;
130
131 int (*smb_write)(struct idt_89hpesx_dev *, const struct idt_smb_seq *);
132 int (*smb_read)(struct idt_89hpesx_dev *, struct idt_smb_seq *);
133 struct mutex smb_mtx;
134
135 struct i2c_client *client;
136
137 struct bin_attribute *ee_file;
138 struct dentry *csr_dir;
139 };
140
141 /*
142 * struct idt_smb_seq - sequence of data to be read/written from/to IDT 89HPESx
143 * @ccode: SMBus command code
144 * @bytecnt: Byte count of operation
145 * @data: Data to by written
146 */
147 struct idt_smb_seq {
148 u8 ccode;
149 u8 bytecnt;
150 u8 *data;
151 };
152
153 /*
154 * struct idt_eeprom_seq - sequence of data to be read/written from/to EEPROM
155 * @cmd: Transaction CMD
156 * @eeaddr: EEPROM custom address
157 * @memaddr: Internal memory address of EEPROM
158 * @data: Data to be written at the memory address
159 */
160 struct idt_eeprom_seq {
161 u8 cmd;
162 u8 eeaddr;
163 u16 memaddr;
164 u8 data;
165 } __packed;
166
167 /*
168 * struct idt_csr_seq - sequence of data to be read/written from/to CSR
169 * @cmd: Transaction CMD
170 * @csraddr: Internal IDT device CSR address
171 * @data: Data to be read/written from/to the CSR address
172 */
173 struct idt_csr_seq {
174 u8 cmd;
175 u16 csraddr;
176 u32 data;
177 } __packed;
178
179 /*
180 * SMBus command code macros
181 * @CCODE_END: Indicates the end of transaction
182 * @CCODE_START: Indicates the start of transaction
183 * @CCODE_CSR: CSR read/write transaction
184 * @CCODE_EEPROM: EEPROM read/write transaction
185 * @CCODE_BYTE: Supplied data has BYTE length
186 * @CCODE_WORD: Supplied data has WORD length
187 * @CCODE_BLOCK: Supplied data has variable length passed in bytecnt
188 * byte right following CCODE byte
189 */
190 #define CCODE_END ((u8)0x01)
191 #define CCODE_START ((u8)0x02)
192 #define CCODE_CSR ((u8)0x00)
193 #define CCODE_EEPROM ((u8)0x04)
194 #define CCODE_BYTE ((u8)0x00)
195 #define CCODE_WORD ((u8)0x20)
196 #define CCODE_BLOCK ((u8)0x40)
197 #define CCODE_PEC ((u8)0x80)
198
199 /*
200 * EEPROM command macros
201 * @EEPROM_OP_WRITE: EEPROM write operation
202 * @EEPROM_OP_READ: EEPROM read operation
203 * @EEPROM_USA: Use specified address of EEPROM
204 * @EEPROM_NAERR: EEPROM device is not ready to respond
205 * @EEPROM_LAERR: EEPROM arbitration loss error
206 * @EEPROM_MSS: EEPROM misplace start & stop bits error
207 * @EEPROM_WR_CNT: Bytes count to perform write operation
208 * @EEPROM_WRRD_CNT: Bytes count to write before reading
209 * @EEPROM_RD_CNT: Bytes count to perform read operation
210 * @EEPROM_DEF_SIZE: Fall back size of EEPROM
211 * @EEPROM_DEF_ADDR: Defatul EEPROM address
212 * @EEPROM_TOUT: Timeout before retry read operation if eeprom is busy
213 */
214 #define EEPROM_OP_WRITE ((u8)0x00)
215 #define EEPROM_OP_READ ((u8)0x01)
216 #define EEPROM_USA ((u8)0x02)
217 #define EEPROM_NAERR ((u8)0x08)
218 #define EEPROM_LAERR ((u8)0x10)
219 #define EEPROM_MSS ((u8)0x20)
220 #define EEPROM_WR_CNT ((u8)5)
221 #define EEPROM_WRRD_CNT ((u8)4)
222 #define EEPROM_RD_CNT ((u8)5)
223 #define EEPROM_DEF_SIZE ((u16)4096)
224 #define EEPROM_DEF_ADDR ((u8)0x50)
225 #define EEPROM_TOUT (100)
226
227 /*
228 * CSR command macros
229 * @CSR_DWE: Enable all four bytes of the operation
230 * @CSR_OP_WRITE: CSR write operation
231 * @CSR_OP_READ: CSR read operation
232 * @CSR_RERR: Read operation error
233 * @CSR_WERR: Write operation error
234 * @CSR_WR_CNT: Bytes count to perform write operation
235 * @CSR_WRRD_CNT: Bytes count to write before reading
236 * @CSR_RD_CNT: Bytes count to perform read operation
237 * @CSR_MAX: Maximum CSR address
238 * @CSR_DEF: Default CSR address
239 * @CSR_REAL_ADDR: CSR real unshifted address
240 */
241 #define CSR_DWE ((u8)0x0F)
242 #define CSR_OP_WRITE ((u8)0x00)
243 #define CSR_OP_READ ((u8)0x10)
244 #define CSR_RERR ((u8)0x40)
245 #define CSR_WERR ((u8)0x80)
246 #define CSR_WR_CNT ((u8)7)
247 #define CSR_WRRD_CNT ((u8)3)
248 #define CSR_RD_CNT ((u8)7)
249 #define CSR_MAX ((u32)0x3FFFF)
250 #define CSR_DEF ((u16)0x0000)
251 #define CSR_REAL_ADDR(val) ((unsigned int)val << 2)
252
253 /*
254 * IDT 89HPESx basic register
255 * @IDT_VIDDID_CSR: PCIe VID and DID of IDT 89HPESx
256 * @IDT_VID_MASK: Mask of VID
257 */
258 #define IDT_VIDDID_CSR ((u32)0x0000)
259 #define IDT_VID_MASK ((u32)0xFFFF)
260
261 /*
262 * IDT 89HPESx can send NACK when new command is sent before previous one
263 * fininshed execution. In this case driver retries operation
264 * certain times.
265 * @RETRY_CNT: Number of retries before giving up and fail
266 * @idt_smb_safe: Generate a retry loop on corresponding SMBus method
267 */
268 #define RETRY_CNT (128)
269 #define idt_smb_safe(ops, args...) ({ \
270 int __retry = RETRY_CNT; \
271 s32 __sts; \
272 do { \
273 __sts = i2c_smbus_ ## ops ## _data(args); \
274 } while (__retry-- && __sts < 0); \
275 __sts; \
276 })
277
278 /*===========================================================================
279 * i2c bus level IO-operations
280 *===========================================================================
281 */
282
283 /*
284 * idt_smb_write_byte() - SMBus write method when I2C_SMBUS_BYTE_DATA operation
285 * is only available
286 * @pdev: Pointer to the driver data
287 * @seq: Sequence of data to be written
288 */
289 static int idt_smb_write_byte(struct idt_89hpesx_dev *pdev,
290 const struct idt_smb_seq *seq)
291 {
292 s32 sts;
293 u8 ccode;
294 int idx;
295
296 /* Loop over the supplied data sending byte one-by-one */
297 for (idx = 0; idx < seq->bytecnt; idx++) {
298 /* Collect the command code byte */
299 ccode = seq->ccode | CCODE_BYTE;
300 if (idx == 0)
301 ccode |= CCODE_START;
302 if (idx == seq->bytecnt - 1)
303 ccode |= CCODE_END;
304
305 /* Send data to the device */
306 sts = idt_smb_safe(write_byte, pdev->client, ccode,
307 seq->data[idx]);
308 if (sts != 0)
309 return (int)sts;
310 }
311
312 return 0;
313 }
314
315 /*
316 * idt_smb_read_byte() - SMBus read method when I2C_SMBUS_BYTE_DATA operation
317 * is only available
318 * @pdev: Pointer to the driver data
319 * @seq: Buffer to read data to
320 */
321 static int idt_smb_read_byte(struct idt_89hpesx_dev *pdev,
322 struct idt_smb_seq *seq)
323 {
324 s32 sts;
325 u8 ccode;
326 int idx;
327
328 /* Loop over the supplied buffer receiving byte one-by-one */
329 for (idx = 0; idx < seq->bytecnt; idx++) {
330 /* Collect the command code byte */
331 ccode = seq->ccode | CCODE_BYTE;
332 if (idx == 0)
333 ccode |= CCODE_START;
334 if (idx == seq->bytecnt - 1)
335 ccode |= CCODE_END;
336
337 /* Read data from the device */
338 sts = idt_smb_safe(read_byte, pdev->client, ccode);
339 if (sts < 0)
340 return (int)sts;
341
342 seq->data[idx] = (u8)sts;
343 }
344
345 return 0;
346 }
347
348 /*
349 * idt_smb_write_word() - SMBus write method when I2C_SMBUS_BYTE_DATA and
350 * I2C_FUNC_SMBUS_WORD_DATA operations are available
351 * @pdev: Pointer to the driver data
352 * @seq: Sequence of data to be written
353 */
354 static int idt_smb_write_word(struct idt_89hpesx_dev *pdev,
355 const struct idt_smb_seq *seq)
356 {
357 s32 sts;
358 u8 ccode;
359 int idx, evencnt;
360
361 /* Calculate the even count of data to send */
362 evencnt = seq->bytecnt - (seq->bytecnt % 2);
363
364 /* Loop over the supplied data sending two bytes at a time */
365 for (idx = 0; idx < evencnt; idx += 2) {
366 /* Collect the command code byte */
367 ccode = seq->ccode | CCODE_WORD;
368 if (idx == 0)
369 ccode |= CCODE_START;
370 if (idx == evencnt - 2)
371 ccode |= CCODE_END;
372
373 /* Send word data to the device */
374 sts = idt_smb_safe(write_word, pdev->client, ccode,
375 *(u16 *)&seq->data[idx]);
376 if (sts != 0)
377 return (int)sts;
378 }
379
380 /* If there is odd number of bytes then send just one last byte */
381 if (seq->bytecnt != evencnt) {
382 /* Collect the command code byte */
383 ccode = seq->ccode | CCODE_BYTE | CCODE_END;
384 if (idx == 0)
385 ccode |= CCODE_START;
386
387 /* Send byte data to the device */
388 sts = idt_smb_safe(write_byte, pdev->client, ccode,
389 seq->data[idx]);
390 if (sts != 0)
391 return (int)sts;
392 }
393
394 return 0;
395 }
396
397 /*
398 * idt_smb_read_word() - SMBus read method when I2C_SMBUS_BYTE_DATA and
399 * I2C_FUNC_SMBUS_WORD_DATA operations are available
400 * @pdev: Pointer to the driver data
401 * @seq: Buffer to read data to
402 */
403 static int idt_smb_read_word(struct idt_89hpesx_dev *pdev,
404 struct idt_smb_seq *seq)
405 {
406 s32 sts;
407 u8 ccode;
408 int idx, evencnt;
409
410 /* Calculate the even count of data to send */
411 evencnt = seq->bytecnt - (seq->bytecnt % 2);
412
413 /* Loop over the supplied data reading two bytes at a time */
414 for (idx = 0; idx < evencnt; idx += 2) {
415 /* Collect the command code byte */
416 ccode = seq->ccode | CCODE_WORD;
417 if (idx == 0)
418 ccode |= CCODE_START;
419 if (idx == evencnt - 2)
420 ccode |= CCODE_END;
421
422 /* Read word data from the device */
423 sts = idt_smb_safe(read_word, pdev->client, ccode);
424 if (sts < 0)
425 return (int)sts;
426
427 *(u16 *)&seq->data[idx] = (u16)sts;
428 }
429
430 /* If there is odd number of bytes then receive just one last byte */
431 if (seq->bytecnt != evencnt) {
432 /* Collect the command code byte */
433 ccode = seq->ccode | CCODE_BYTE | CCODE_END;
434 if (idx == 0)
435 ccode |= CCODE_START;
436
437 /* Read last data byte from the device */
438 sts = idt_smb_safe(read_byte, pdev->client, ccode);
439 if (sts < 0)
440 return (int)sts;
441
442 seq->data[idx] = (u8)sts;
443 }
444
445 return 0;
446 }
447
448 /*
449 * idt_smb_write_block() - SMBus write method when I2C_SMBUS_BLOCK_DATA
450 * operation is available
451 * @pdev: Pointer to the driver data
452 * @seq: Sequence of data to be written
453 */
454 static int idt_smb_write_block(struct idt_89hpesx_dev *pdev,
455 const struct idt_smb_seq *seq)
456 {
457 u8 ccode;
458
459 /* Return error if too much data passed to send */
460 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
461 return -EINVAL;
462
463 /* Collect the command code byte */
464 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
465
466 /* Send block of data to the device */
467 return idt_smb_safe(write_block, pdev->client, ccode, seq->bytecnt,
468 seq->data);
469 }
470
471 /*
472 * idt_smb_read_block() - SMBus read method when I2C_SMBUS_BLOCK_DATA
473 * operation is available
474 * @pdev: Pointer to the driver data
475 * @seq: Buffer to read data to
476 */
477 static int idt_smb_read_block(struct idt_89hpesx_dev *pdev,
478 struct idt_smb_seq *seq)
479 {
480 s32 sts;
481 u8 ccode;
482
483 /* Return error if too much data passed to send */
484 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
485 return -EINVAL;
486
487 /* Collect the command code byte */
488 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
489
490 /* Read block of data from the device */
491 sts = idt_smb_safe(read_block, pdev->client, ccode, seq->data);
492 if (sts != seq->bytecnt)
493 return (sts < 0 ? sts : -ENODATA);
494
495 return 0;
496 }
497
498 /*
499 * idt_smb_write_i2c_block() - SMBus write method when I2C_SMBUS_I2C_BLOCK_DATA
500 * operation is available
501 * @pdev: Pointer to the driver data
502 * @seq: Sequence of data to be written
503 *
504 * NOTE It's usual SMBus write block operation, except the actual data length is
505 * sent as first byte of data
506 */
507 static int idt_smb_write_i2c_block(struct idt_89hpesx_dev *pdev,
508 const struct idt_smb_seq *seq)
509 {
510 u8 ccode, buf[I2C_SMBUS_BLOCK_MAX + 1];
511
512 /* Return error if too much data passed to send */
513 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
514 return -EINVAL;
515
516 /* Collect the data to send. Length byte must be added prior the data */
517 buf[0] = seq->bytecnt;
518 memcpy(&buf[1], seq->data, seq->bytecnt);
519
520 /* Collect the command code byte */
521 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
522
523 /* Send length and block of data to the device */
524 return idt_smb_safe(write_i2c_block, pdev->client, ccode,
525 seq->bytecnt + 1, buf);
526 }
527
528 /*
529 * idt_smb_read_i2c_block() - SMBus read method when I2C_SMBUS_I2C_BLOCK_DATA
530 * operation is available
531 * @pdev: Pointer to the driver data
532 * @seq: Buffer to read data to
533 *
534 * NOTE It's usual SMBus read block operation, except the actual data length is
535 * retrieved as first byte of data
536 */
537 static int idt_smb_read_i2c_block(struct idt_89hpesx_dev *pdev,
538 struct idt_smb_seq *seq)
539 {
540 u8 ccode, buf[I2C_SMBUS_BLOCK_MAX + 1];
541 s32 sts;
542
543 /* Return error if too much data passed to send */
544 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
545 return -EINVAL;
546
547 /* Collect the command code byte */
548 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
549
550 /* Read length and block of data from the device */
551 sts = idt_smb_safe(read_i2c_block, pdev->client, ccode,
552 seq->bytecnt + 1, buf);
553 if (sts != seq->bytecnt + 1)
554 return (sts < 0 ? sts : -ENODATA);
555 if (buf[0] != seq->bytecnt)
556 return -ENODATA;
557
558 /* Copy retrieved data to the output data buffer */
559 memcpy(seq->data, &buf[1], seq->bytecnt);
560
561 return 0;
562 }
563
564 /*===========================================================================
565 * EEPROM IO-operations
566 *===========================================================================
567 */
568
569 /*
570 * idt_eeprom_read_byte() - read just one byte from EEPROM
571 * @pdev: Pointer to the driver data
572 * @memaddr: Start EEPROM memory address
573 * @data: Data to be written to EEPROM
574 */
575 static int idt_eeprom_read_byte(struct idt_89hpesx_dev *pdev, u16 memaddr,
576 u8 *data)
577 {
578 struct device *dev = &pdev->client->dev;
579 struct idt_eeprom_seq eeseq;
580 struct idt_smb_seq smbseq;
581 int ret, retry;
582
583 /* Initialize SMBus sequence fields */
584 smbseq.ccode = pdev->iniccode | CCODE_EEPROM;
585 smbseq.data = (u8 *)&eeseq;
586
587 /*
588 * Sometimes EEPROM may respond with NACK if it's busy with previous
589 * operation, so we need to perform a few attempts of read cycle
590 */
591 retry = RETRY_CNT;
592 do {
593 /* Send EEPROM memory address to read data from */
594 smbseq.bytecnt = EEPROM_WRRD_CNT;
595 eeseq.cmd = pdev->inieecmd | EEPROM_OP_READ;
596 eeseq.eeaddr = pdev->eeaddr;
597 eeseq.memaddr = cpu_to_le16(memaddr);
598 ret = pdev->smb_write(pdev, &smbseq);
599 if (ret != 0) {
600 dev_err(dev, "Failed to init eeprom addr 0x%02hhx",
601 memaddr);
602 break;
603 }
604
605 /* Perform read operation */
606 smbseq.bytecnt = EEPROM_RD_CNT;
607 ret = pdev->smb_read(pdev, &smbseq);
608 if (ret != 0) {
609 dev_err(dev, "Failed to read eeprom data 0x%02hhx",
610 memaddr);
611 break;
612 }
613
614 /* Restart read operation if the device is busy */
615 if (retry && (eeseq.cmd & EEPROM_NAERR)) {
616 dev_dbg(dev, "EEPROM busy, retry reading after %d ms",
617 EEPROM_TOUT);
618 msleep(EEPROM_TOUT);
619 continue;
620 }
621
622 /* Check whether IDT successfully read data from EEPROM */
623 if (eeseq.cmd & (EEPROM_NAERR | EEPROM_LAERR | EEPROM_MSS)) {
624 dev_err(dev,
625 "Communication with eeprom failed, cmd 0x%hhx",
626 eeseq.cmd);
627 ret = -EREMOTEIO;
628 break;
629 }
630
631 /* Save retrieved data and exit the loop */
632 *data = eeseq.data;
633 break;
634 } while (retry--);
635
636 /* Return the status of operation */
637 return ret;
638 }
639
640 /*
641 * idt_eeprom_write() - EEPROM write operation
642 * @pdev: Pointer to the driver data
643 * @memaddr: Start EEPROM memory address
644 * @len: Length of data to be written
645 * @data: Data to be written to EEPROM
646 */
647 static int idt_eeprom_write(struct idt_89hpesx_dev *pdev, u16 memaddr, u16 len,
648 const u8 *data)
649 {
650 struct device *dev = &pdev->client->dev;
651 struct idt_eeprom_seq eeseq;
652 struct idt_smb_seq smbseq;
653 int ret;
654 u16 idx;
655
656 /* Initialize SMBus sequence fields */
657 smbseq.ccode = pdev->iniccode | CCODE_EEPROM;
658 smbseq.data = (u8 *)&eeseq;
659
660 /* Send data byte-by-byte, checking if it is successfully written */
661 for (idx = 0; idx < len; idx++, memaddr++) {
662 /* Lock IDT SMBus device */
663 mutex_lock(&pdev->smb_mtx);
664
665 /* Perform write operation */
666 smbseq.bytecnt = EEPROM_WR_CNT;
667 eeseq.cmd = pdev->inieecmd | EEPROM_OP_WRITE;
668 eeseq.eeaddr = pdev->eeaddr;
669 eeseq.memaddr = cpu_to_le16(memaddr);
670 eeseq.data = data[idx];
671 ret = pdev->smb_write(pdev, &smbseq);
672 if (ret != 0) {
673 dev_err(dev,
674 "Failed to write 0x%04hx:0x%02hhx to eeprom",
675 memaddr, data[idx]);
676 goto err_mutex_unlock;
677 }
678
679 /*
680 * Check whether the data is successfully written by reading
681 * from the same EEPROM memory address.
682 */
683 eeseq.data = ~data[idx];
684 ret = idt_eeprom_read_byte(pdev, memaddr, &eeseq.data);
685 if (ret != 0)
686 goto err_mutex_unlock;
687
688 /* Check whether the read byte is the same as written one */
689 if (eeseq.data != data[idx]) {
690 dev_err(dev, "Values don't match 0x%02hhx != 0x%02hhx",
691 eeseq.data, data[idx]);
692 ret = -EREMOTEIO;
693 goto err_mutex_unlock;
694 }
695
696 /* Unlock IDT SMBus device */
697 err_mutex_unlock:
698 mutex_unlock(&pdev->smb_mtx);
699 if (ret != 0)
700 return ret;
701 }
702
703 return 0;
704 }
705
706 /*
707 * idt_eeprom_read() - EEPROM read operation
708 * @pdev: Pointer to the driver data
709 * @memaddr: Start EEPROM memory address
710 * @len: Length of data to read
711 * @buf: Buffer to read data to
712 */
713 static int idt_eeprom_read(struct idt_89hpesx_dev *pdev, u16 memaddr, u16 len,
714 u8 *buf)
715 {
716 int ret;
717 u16 idx;
718
719 /* Read data byte-by-byte, retrying if it wasn't successful */
720 for (idx = 0; idx < len; idx++, memaddr++) {
721 /* Lock IDT SMBus device */
722 mutex_lock(&pdev->smb_mtx);
723
724 /* Just read the byte to the buffer */
725 ret = idt_eeprom_read_byte(pdev, memaddr, &buf[idx]);
726
727 /* Unlock IDT SMBus device */
728 mutex_unlock(&pdev->smb_mtx);
729
730 /* Return error if read operation failed */
731 if (ret != 0)
732 return ret;
733 }
734
735 return 0;
736 }
737
738 /*===========================================================================
739 * CSR IO-operations
740 *===========================================================================
741 */
742
743 /*
744 * idt_csr_write() - CSR write operation
745 * @pdev: Pointer to the driver data
746 * @csraddr: CSR address (with no two LS bits)
747 * @data: Data to be written to CSR
748 */
749 static int idt_csr_write(struct idt_89hpesx_dev *pdev, u16 csraddr,
750 const u32 data)
751 {
752 struct device *dev = &pdev->client->dev;
753 struct idt_csr_seq csrseq;
754 struct idt_smb_seq smbseq;
755 int ret;
756
757 /* Initialize SMBus sequence fields */
758 smbseq.ccode = pdev->iniccode | CCODE_CSR;
759 smbseq.data = (u8 *)&csrseq;
760
761 /* Lock IDT SMBus device */
762 mutex_lock(&pdev->smb_mtx);
763
764 /* Perform write operation */
765 smbseq.bytecnt = CSR_WR_CNT;
766 csrseq.cmd = pdev->inicsrcmd | CSR_OP_WRITE;
767 csrseq.csraddr = cpu_to_le16(csraddr);
768 csrseq.data = cpu_to_le32(data);
769 ret = pdev->smb_write(pdev, &smbseq);
770 if (ret != 0) {
771 dev_err(dev, "Failed to write 0x%04x: 0x%04x to csr",
772 CSR_REAL_ADDR(csraddr), data);
773 goto err_mutex_unlock;
774 }
775
776 /* Send CSR address to read data from */
777 smbseq.bytecnt = CSR_WRRD_CNT;
778 csrseq.cmd = pdev->inicsrcmd | CSR_OP_READ;
779 ret = pdev->smb_write(pdev, &smbseq);
780 if (ret != 0) {
781 dev_err(dev, "Failed to init csr address 0x%04x",
782 CSR_REAL_ADDR(csraddr));
783 goto err_mutex_unlock;
784 }
785
786 /* Perform read operation */
787 smbseq.bytecnt = CSR_RD_CNT;
788 ret = pdev->smb_read(pdev, &smbseq);
789 if (ret != 0) {
790 dev_err(dev, "Failed to read csr 0x%04x",
791 CSR_REAL_ADDR(csraddr));
792 goto err_mutex_unlock;
793 }
794
795 /* Check whether IDT successfully retrieved CSR data */
796 if (csrseq.cmd & (CSR_RERR | CSR_WERR)) {
797 dev_err(dev, "IDT failed to perform CSR r/w");
798 ret = -EREMOTEIO;
799 goto err_mutex_unlock;
800 }
801
802 /* Unlock IDT SMBus device */
803 err_mutex_unlock:
804 mutex_unlock(&pdev->smb_mtx);
805
806 return ret;
807 }
808
809 /*
810 * idt_csr_read() - CSR read operation
811 * @pdev: Pointer to the driver data
812 * @csraddr: CSR address (with no two LS bits)
813 * @data: Data to be written to CSR
814 */
815 static int idt_csr_read(struct idt_89hpesx_dev *pdev, u16 csraddr, u32 *data)
816 {
817 struct device *dev = &pdev->client->dev;
818 struct idt_csr_seq csrseq;
819 struct idt_smb_seq smbseq;
820 int ret;
821
822 /* Initialize SMBus sequence fields */
823 smbseq.ccode = pdev->iniccode | CCODE_CSR;
824 smbseq.data = (u8 *)&csrseq;
825
826 /* Lock IDT SMBus device */
827 mutex_lock(&pdev->smb_mtx);
828
829 /* Send CSR register address before reading it */
830 smbseq.bytecnt = CSR_WRRD_CNT;
831 csrseq.cmd = pdev->inicsrcmd | CSR_OP_READ;
832 csrseq.csraddr = cpu_to_le16(csraddr);
833 ret = pdev->smb_write(pdev, &smbseq);
834 if (ret != 0) {
835 dev_err(dev, "Failed to init csr address 0x%04x",
836 CSR_REAL_ADDR(csraddr));
837 goto err_mutex_unlock;
838 }
839
840 /* Perform read operation */
841 smbseq.bytecnt = CSR_RD_CNT;
842 ret = pdev->smb_read(pdev, &smbseq);
843 if (ret != 0) {
844 dev_err(dev, "Failed to read csr 0x%04hx",
845 CSR_REAL_ADDR(csraddr));
846 goto err_mutex_unlock;
847 }
848
849 /* Check whether IDT successfully retrieved CSR data */
850 if (csrseq.cmd & (CSR_RERR | CSR_WERR)) {
851 dev_err(dev, "IDT failed to perform CSR r/w");
852 ret = -EREMOTEIO;
853 goto err_mutex_unlock;
854 }
855
856 /* Save data retrieved from IDT */
857 *data = le32_to_cpu(csrseq.data);
858
859 /* Unlock IDT SMBus device */
860 err_mutex_unlock:
861 mutex_unlock(&pdev->smb_mtx);
862
863 return ret;
864 }
865
866 /*===========================================================================
867 * Sysfs/debugfs-nodes IO-operations
868 *===========================================================================
869 */
870
871 /*
872 * eeprom_write() - EEPROM sysfs-node write callback
873 * @filep: Pointer to the file system node
874 * @kobj: Pointer to the kernel object related to the sysfs-node
875 * @attr: Attributes of the file
876 * @buf: Buffer to write data to
877 * @off: Offset at which data should be written to
878 * @count: Number of bytes to write
879 */
880 static ssize_t eeprom_write(struct file *filp, struct kobject *kobj,
881 struct bin_attribute *attr,
882 char *buf, loff_t off, size_t count)
883 {
884 struct idt_89hpesx_dev *pdev;
885 int ret;
886
887 /* Retrieve driver data */
888 pdev = dev_get_drvdata(kobj_to_dev(kobj));
889
890 /* Perform EEPROM write operation */
891 ret = idt_eeprom_write(pdev, (u16)off, (u16)count, (u8 *)buf);
892 return (ret != 0 ? ret : count);
893 }
894
895 /*
896 * eeprom_read() - EEPROM sysfs-node read callback
897 * @filep: Pointer to the file system node
898 * @kobj: Pointer to the kernel object related to the sysfs-node
899 * @attr: Attributes of the file
900 * @buf: Buffer to write data to
901 * @off: Offset at which data should be written to
902 * @count: Number of bytes to write
903 */
904 static ssize_t eeprom_read(struct file *filp, struct kobject *kobj,
905 struct bin_attribute *attr,
906 char *buf, loff_t off, size_t count)
907 {
908 struct idt_89hpesx_dev *pdev;
909 int ret;
910
911 /* Retrieve driver data */
912 pdev = dev_get_drvdata(kobj_to_dev(kobj));
913
914 /* Perform EEPROM read operation */
915 ret = idt_eeprom_read(pdev, (u16)off, (u16)count, (u8 *)buf);
916 return (ret != 0 ? ret : count);
917 }
918
919 /*
920 * idt_dbgfs_csr_write() - CSR debugfs-node write callback
921 * @filep: Pointer to the file system file descriptor
922 * @buf: Buffer to read data from
923 * @count: Size of the buffer
924 * @offp: Offset within the file
925 *
926 * It accepts either "0x<reg addr>:0x<value>" for saving register address
927 * and writing value to specified DWORD register or "0x<reg addr>" for
928 * just saving register address in order to perform next read operation.
929 *
930 * WARNING No spaces are allowed. Incoming string must be strictly formated as:
931 * "<reg addr>:<value>". Register address must be aligned within 4 bytes
932 * (one DWORD).
933 */
934 static ssize_t idt_dbgfs_csr_write(struct file *filep, const char __user *ubuf,
935 size_t count, loff_t *offp)
936 {
937 struct idt_89hpesx_dev *pdev = filep->private_data;
938 char *colon_ch, *csraddr_str, *csrval_str;
939 int ret, csraddr_len;
940 u32 csraddr, csrval;
941 char *buf;
942
943 /* Copy data from User-space */
944 buf = kmalloc(count + 1, GFP_KERNEL);
945 if (!buf)
946 return -ENOMEM;
947
948 ret = simple_write_to_buffer(buf, count, offp, ubuf, count);
949 if (ret < 0)
950 goto free_buf;
951 buf[count] = 0;
952
953 /* Find position of colon in the buffer */
954 colon_ch = strnchr(buf, count, ':');
955
956 /*
957 * If there is colon passed then new CSR value should be parsed as
958 * well, so allocate buffer for CSR address substring.
959 * If no colon is found, then string must have just one number with
960 * no new CSR value
961 */
962 if (colon_ch != NULL) {
963 csraddr_len = colon_ch - buf;
964 csraddr_str =
965 kmalloc(csraddr_len + 1, GFP_KERNEL);
966 if (csraddr_str == NULL) {
967 ret = -ENOMEM;
968 goto free_buf;
969 }
970 /* Copy the register address to the substring buffer */
971 strncpy(csraddr_str, buf, csraddr_len);
972 csraddr_str[csraddr_len] = '\0';
973 /* Register value must follow the colon */
974 csrval_str = colon_ch + 1;
975 } else /* if (str_colon == NULL) */ {
976 csraddr_str = (char *)buf; /* Just to shut warning up */
977 csraddr_len = strnlen(csraddr_str, count);
978 csrval_str = NULL;
979 }
980
981 /* Convert CSR address to u32 value */
982 ret = kstrtou32(csraddr_str, 0, &csraddr);
983 if (ret != 0)
984 goto free_csraddr_str;
985
986 /* Check whether passed register address is valid */
987 if (csraddr > CSR_MAX || !IS_ALIGNED(csraddr, SZ_4)) {
988 ret = -EINVAL;
989 goto free_csraddr_str;
990 }
991
992 /* Shift register address to the right so to have u16 address */
993 pdev->csr = (csraddr >> 2);
994
995 /* Parse new CSR value and send it to IDT, if colon has been found */
996 if (colon_ch != NULL) {
997 ret = kstrtou32(csrval_str, 0, &csrval);
998 if (ret != 0)
999 goto free_csraddr_str;
1000
1001 ret = idt_csr_write(pdev, pdev->csr, csrval);
1002 if (ret != 0)
1003 goto free_csraddr_str;
1004 }
1005
1006 /* Free memory only if colon has been found */
1007 free_csraddr_str:
1008 if (colon_ch != NULL)
1009 kfree(csraddr_str);
1010
1011 /* Free buffer allocated for data retrieved from User-space */
1012 free_buf:
1013 kfree(buf);
1014
1015 return (ret != 0 ? ret : count);
1016 }
1017
1018 /*
1019 * idt_dbgfs_csr_read() - CSR debugfs-node read callback
1020 * @filep: Pointer to the file system file descriptor
1021 * @buf: Buffer to write data to
1022 * @count: Size of the buffer
1023 * @offp: Offset within the file
1024 *
1025 * It just prints the pair "0x<reg addr>:0x<value>" to passed buffer.
1026 */
1027 #define CSRBUF_SIZE ((size_t)32)
1028 static ssize_t idt_dbgfs_csr_read(struct file *filep, char __user *ubuf,
1029 size_t count, loff_t *offp)
1030 {
1031 struct idt_89hpesx_dev *pdev = filep->private_data;
1032 u32 csraddr, csrval;
1033 char buf[CSRBUF_SIZE];
1034 int ret, size;
1035
1036 /* Perform CSR read operation */
1037 ret = idt_csr_read(pdev, pdev->csr, &csrval);
1038 if (ret != 0)
1039 return ret;
1040
1041 /* Shift register address to the left so to have real address */
1042 csraddr = ((u32)pdev->csr << 2);
1043
1044 /* Print the "0x<reg addr>:0x<value>" to buffer */
1045 size = snprintf(buf, CSRBUF_SIZE, "0x%05x:0x%08x\n",
1046 (unsigned int)csraddr, (unsigned int)csrval);
1047
1048 /* Copy data to User-space */
1049 return simple_read_from_buffer(ubuf, count, offp, buf, size);
1050 }
1051
1052 /*
1053 * eeprom_attribute - EEPROM sysfs-node attributes
1054 *
1055 * NOTE Size will be changed in compliance with OF node. EEPROM attribute will
1056 * be read-only as well if the corresponding flag is specified in OF node.
1057 */
1058 static BIN_ATTR_RW(eeprom, EEPROM_DEF_SIZE);
1059
1060 /*
1061 * csr_dbgfs_ops - CSR debugfs-node read/write operations
1062 */
1063 static const struct file_operations csr_dbgfs_ops = {
1064 .owner = THIS_MODULE,
1065 .open = simple_open,
1066 .write = idt_dbgfs_csr_write,
1067 .read = idt_dbgfs_csr_read
1068 };
1069
1070 /*===========================================================================
1071 * Driver init/deinit methods
1072 *===========================================================================
1073 */
1074
1075 /*
1076 * idt_set_defval() - disable EEPROM access by default
1077 * @pdev: Pointer to the driver data
1078 */
1079 static void idt_set_defval(struct idt_89hpesx_dev *pdev)
1080 {
1081 /* If OF info is missing then use next values */
1082 pdev->eesize = 0;
1083 pdev->eero = true;
1084 pdev->inieecmd = 0;
1085 pdev->eeaddr = 0;
1086 }
1087
1088 static const struct i2c_device_id ee_ids[];
1089
1090 /*
1091 * idt_ee_match_id() - check whether the node belongs to compatible EEPROMs
1092 */
1093 static const struct i2c_device_id *idt_ee_match_id(struct fwnode_handle *fwnode)
1094 {
1095 const struct i2c_device_id *id = ee_ids;
1096 const char *compatible, *p;
1097 char devname[I2C_NAME_SIZE];
1098 int ret;
1099
1100 ret = fwnode_property_read_string(fwnode, "compatible", &compatible);
1101 if (ret)
1102 return NULL;
1103
1104 p = strchr(compatible, ',');
1105 strlcpy(devname, p ? p + 1 : compatible, sizeof(devname));
1106 /* Search through the device name */
1107 while (id->name[0]) {
1108 if (strcmp(devname, id->name) == 0)
1109 return id;
1110 id++;
1111 }
1112 return NULL;
1113 }
1114
1115 /*
1116 * idt_get_fw_data() - get IDT i2c-device parameters from device tree
1117 * @pdev: Pointer to the driver data
1118 */
1119 static void idt_get_fw_data(struct idt_89hpesx_dev *pdev)
1120 {
1121 struct device *dev = &pdev->client->dev;
1122 struct fwnode_handle *fwnode;
1123 const struct i2c_device_id *ee_id = NULL;
1124 u32 eeprom_addr;
1125 int ret;
1126
1127 device_for_each_child_node(dev, fwnode) {
1128 ee_id = idt_ee_match_id(fwnode);
1129 if (!ee_id) {
1130 dev_warn(dev, "Skip unsupported EEPROM device");
1131 continue;
1132 } else
1133 break;
1134 }
1135
1136 /* If there is no fwnode EEPROM device, then set zero size */
1137 if (!ee_id) {
1138 dev_warn(dev, "No fwnode, EEPROM access disabled");
1139 idt_set_defval(pdev);
1140 return;
1141 }
1142
1143 /* Retrieve EEPROM size */
1144 pdev->eesize = (u32)ee_id->driver_data;
1145
1146 /* Get custom EEPROM address from 'reg' attribute */
1147 ret = fwnode_property_read_u32(fwnode, "reg", &eeprom_addr);
1148 if (ret || (eeprom_addr == 0)) {
1149 dev_warn(dev, "No EEPROM reg found, use default address 0x%x",
1150 EEPROM_DEF_ADDR);
1151 pdev->inieecmd = 0;
1152 pdev->eeaddr = EEPROM_DEF_ADDR << 1;
1153 } else {
1154 pdev->inieecmd = EEPROM_USA;
1155 pdev->eeaddr = eeprom_addr << 1;
1156 }
1157
1158 /* Check EEPROM 'read-only' flag */
1159 if (fwnode_property_read_bool(fwnode, "read-only"))
1160 pdev->eero = true;
1161 else /* if (!fwnode_property_read_bool(node, "read-only")) */
1162 pdev->eero = false;
1163
1164 dev_info(dev, "EEPROM of %d bytes found by 0x%x",
1165 pdev->eesize, pdev->eeaddr);
1166 }
1167
1168 /*
1169 * idt_create_pdev() - create and init data structure of the driver
1170 * @client: i2c client of IDT PCIe-switch device
1171 */
1172 static struct idt_89hpesx_dev *idt_create_pdev(struct i2c_client *client)
1173 {
1174 struct idt_89hpesx_dev *pdev;
1175
1176 /* Allocate memory for driver data */
1177 pdev = devm_kmalloc(&client->dev, sizeof(struct idt_89hpesx_dev),
1178 GFP_KERNEL);
1179 if (pdev == NULL)
1180 return ERR_PTR(-ENOMEM);
1181
1182 /* Initialize basic fields of the data */
1183 pdev->client = client;
1184 i2c_set_clientdata(client, pdev);
1185
1186 /* Read firmware nodes information */
1187 idt_get_fw_data(pdev);
1188
1189 /* Initialize basic CSR CMD field - use full DWORD-sized r/w ops */
1190 pdev->inicsrcmd = CSR_DWE;
1191 pdev->csr = CSR_DEF;
1192
1193 /* Enable Packet Error Checking if it's supported by adapter */
1194 if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_PEC)) {
1195 pdev->iniccode = CCODE_PEC;
1196 client->flags |= I2C_CLIENT_PEC;
1197 } else /* PEC is unsupported */ {
1198 pdev->iniccode = 0;
1199 }
1200
1201 return pdev;
1202 }
1203
1204 /*
1205 * idt_free_pdev() - free data structure of the driver
1206 * @pdev: Pointer to the driver data
1207 */
1208 static void idt_free_pdev(struct idt_89hpesx_dev *pdev)
1209 {
1210 /* Clear driver data from device private field */
1211 i2c_set_clientdata(pdev->client, NULL);
1212 }
1213
1214 /*
1215 * idt_set_smbus_ops() - set supported SMBus operations
1216 * @pdev: Pointer to the driver data
1217 * Return status of smbus check operations
1218 */
1219 static int idt_set_smbus_ops(struct idt_89hpesx_dev *pdev)
1220 {
1221 struct i2c_adapter *adapter = pdev->client->adapter;
1222 struct device *dev = &pdev->client->dev;
1223
1224 /* Check i2c adapter read functionality */
1225 if (i2c_check_functionality(adapter,
1226 I2C_FUNC_SMBUS_READ_BLOCK_DATA)) {
1227 pdev->smb_read = idt_smb_read_block;
1228 dev_dbg(dev, "SMBus block-read op chosen");
1229 } else if (i2c_check_functionality(adapter,
1230 I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
1231 pdev->smb_read = idt_smb_read_i2c_block;
1232 dev_dbg(dev, "SMBus i2c-block-read op chosen");
1233 } else if (i2c_check_functionality(adapter,
1234 I2C_FUNC_SMBUS_READ_WORD_DATA) &&
1235 i2c_check_functionality(adapter,
1236 I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
1237 pdev->smb_read = idt_smb_read_word;
1238 dev_warn(dev, "Use slow word/byte SMBus read ops");
1239 } else if (i2c_check_functionality(adapter,
1240 I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
1241 pdev->smb_read = idt_smb_read_byte;
1242 dev_warn(dev, "Use slow byte SMBus read op");
1243 } else /* no supported smbus read operations */ {
1244 dev_err(dev, "No supported SMBus read op");
1245 return -EPFNOSUPPORT;
1246 }
1247
1248 /* Check i2c adapter write functionality */
1249 if (i2c_check_functionality(adapter,
1250 I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)) {
1251 pdev->smb_write = idt_smb_write_block;
1252 dev_dbg(dev, "SMBus block-write op chosen");
1253 } else if (i2c_check_functionality(adapter,
1254 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
1255 pdev->smb_write = idt_smb_write_i2c_block;
1256 dev_dbg(dev, "SMBus i2c-block-write op chosen");
1257 } else if (i2c_check_functionality(adapter,
1258 I2C_FUNC_SMBUS_WRITE_WORD_DATA) &&
1259 i2c_check_functionality(adapter,
1260 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
1261 pdev->smb_write = idt_smb_write_word;
1262 dev_warn(dev, "Use slow word/byte SMBus write op");
1263 } else if (i2c_check_functionality(adapter,
1264 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
1265 pdev->smb_write = idt_smb_write_byte;
1266 dev_warn(dev, "Use slow byte SMBus write op");
1267 } else /* no supported smbus write operations */ {
1268 dev_err(dev, "No supported SMBus write op");
1269 return -EPFNOSUPPORT;
1270 }
1271
1272 /* Initialize IDT SMBus slave interface mutex */
1273 mutex_init(&pdev->smb_mtx);
1274
1275 return 0;
1276 }
1277
1278 /*
1279 * idt_check_dev() - check whether it's really IDT 89HPESx device
1280 * @pdev: Pointer to the driver data
1281 * Return status of i2c adapter check operation
1282 */
1283 static int idt_check_dev(struct idt_89hpesx_dev *pdev)
1284 {
1285 struct device *dev = &pdev->client->dev;
1286 u32 viddid;
1287 int ret;
1288
1289 /* Read VID and DID directly from IDT memory space */
1290 ret = idt_csr_read(pdev, IDT_VIDDID_CSR, &viddid);
1291 if (ret != 0) {
1292 dev_err(dev, "Failed to read VID/DID");
1293 return ret;
1294 }
1295
1296 /* Check whether it's IDT device */
1297 if ((viddid & IDT_VID_MASK) != PCI_VENDOR_ID_IDT) {
1298 dev_err(dev, "Got unsupported VID/DID: 0x%08x", viddid);
1299 return -ENODEV;
1300 }
1301
1302 dev_info(dev, "Found IDT 89HPES device VID:0x%04x, DID:0x%04x",
1303 (viddid & IDT_VID_MASK), (viddid >> 16));
1304
1305 return 0;
1306 }
1307
1308 /*
1309 * idt_create_sysfs_files() - create sysfs attribute files
1310 * @pdev: Pointer to the driver data
1311 * Return status of operation
1312 */
1313 static int idt_create_sysfs_files(struct idt_89hpesx_dev *pdev)
1314 {
1315 struct device *dev = &pdev->client->dev;
1316 int ret;
1317
1318 /* Don't do anything if EEPROM isn't accessible */
1319 if (pdev->eesize == 0) {
1320 dev_dbg(dev, "Skip creating sysfs-files");
1321 return 0;
1322 }
1323
1324 /* Allocate memory for attribute file */
1325 pdev->ee_file = devm_kmalloc(dev, sizeof(*pdev->ee_file), GFP_KERNEL);
1326 if (!pdev->ee_file)
1327 return -ENOMEM;
1328
1329 /* Copy the declared EEPROM attr structure to change some of fields */
1330 memcpy(pdev->ee_file, &bin_attr_eeprom, sizeof(*pdev->ee_file));
1331
1332 /* In case of read-only EEPROM get rid of write ability */
1333 if (pdev->eero) {
1334 pdev->ee_file->attr.mode &= ~0200;
1335 pdev->ee_file->write = NULL;
1336 }
1337 /* Create EEPROM sysfs file */
1338 pdev->ee_file->size = pdev->eesize;
1339 ret = sysfs_create_bin_file(&dev->kobj, pdev->ee_file);
1340 if (ret != 0) {
1341 dev_err(dev, "Failed to create EEPROM sysfs-node");
1342 return ret;
1343 }
1344
1345 return 0;
1346 }
1347
1348 /*
1349 * idt_remove_sysfs_files() - remove sysfs attribute files
1350 * @pdev: Pointer to the driver data
1351 */
1352 static void idt_remove_sysfs_files(struct idt_89hpesx_dev *pdev)
1353 {
1354 struct device *dev = &pdev->client->dev;
1355
1356 /* Don't do anything if EEPROM wasn't accessible */
1357 if (pdev->eesize == 0)
1358 return;
1359
1360 /* Remove EEPROM sysfs file */
1361 sysfs_remove_bin_file(&dev->kobj, pdev->ee_file);
1362 }
1363
1364 /*
1365 * idt_create_dbgfs_files() - create debugfs files
1366 * @pdev: Pointer to the driver data
1367 */
1368 #define CSRNAME_LEN ((size_t)32)
1369 static void idt_create_dbgfs_files(struct idt_89hpesx_dev *pdev)
1370 {
1371 struct i2c_client *cli = pdev->client;
1372 char fname[CSRNAME_LEN];
1373
1374 /* Create Debugfs directory for CSR file */
1375 snprintf(fname, CSRNAME_LEN, "%d-%04hx", cli->adapter->nr, cli->addr);
1376 pdev->csr_dir = debugfs_create_dir(fname, csr_dbgdir);
1377
1378 /* Create Debugfs file for CSR read/write operations */
1379 debugfs_create_file(cli->name, 0600, pdev->csr_dir, pdev,
1380 &csr_dbgfs_ops);
1381 }
1382
1383 /*
1384 * idt_remove_dbgfs_files() - remove debugfs files
1385 * @pdev: Pointer to the driver data
1386 */
1387 static void idt_remove_dbgfs_files(struct idt_89hpesx_dev *pdev)
1388 {
1389 /* Remove CSR directory and it sysfs-node */
1390 debugfs_remove_recursive(pdev->csr_dir);
1391 }
1392
1393 /*
1394 * idt_probe() - IDT 89HPESx driver probe() callback method
1395 */
1396 static int idt_probe(struct i2c_client *client, const struct i2c_device_id *id)
1397 {
1398 struct idt_89hpesx_dev *pdev;
1399 int ret;
1400
1401 /* Create driver data */
1402 pdev = idt_create_pdev(client);
1403 if (IS_ERR(pdev))
1404 return PTR_ERR(pdev);
1405
1406 /* Set SMBus operations */
1407 ret = idt_set_smbus_ops(pdev);
1408 if (ret != 0)
1409 goto err_free_pdev;
1410
1411 /* Check whether it is truly IDT 89HPESx device */
1412 ret = idt_check_dev(pdev);
1413 if (ret != 0)
1414 goto err_free_pdev;
1415
1416 /* Create sysfs files */
1417 ret = idt_create_sysfs_files(pdev);
1418 if (ret != 0)
1419 goto err_free_pdev;
1420
1421 /* Create debugfs files */
1422 idt_create_dbgfs_files(pdev);
1423
1424 return 0;
1425
1426 err_free_pdev:
1427 idt_free_pdev(pdev);
1428
1429 return ret;
1430 }
1431
1432 /*
1433 * idt_remove() - IDT 89HPESx driver remove() callback method
1434 */
1435 static int idt_remove(struct i2c_client *client)
1436 {
1437 struct idt_89hpesx_dev *pdev = i2c_get_clientdata(client);
1438
1439 /* Remove debugfs files first */
1440 idt_remove_dbgfs_files(pdev);
1441
1442 /* Remove sysfs files */
1443 idt_remove_sysfs_files(pdev);
1444
1445 /* Discard driver data structure */
1446 idt_free_pdev(pdev);
1447
1448 return 0;
1449 }
1450
1451 /*
1452 * ee_ids - array of supported EEPROMs
1453 */
1454 static const struct i2c_device_id ee_ids[] = {
1455 { "24c32", 4096},
1456 { "24c64", 8192},
1457 { "24c128", 16384},
1458 { "24c256", 32768},
1459 { "24c512", 65536},
1460 {}
1461 };
1462 MODULE_DEVICE_TABLE(i2c, ee_ids);
1463
1464 /*
1465 * idt_ids - supported IDT 89HPESx devices
1466 */
1467 static const struct i2c_device_id idt_ids[] = {
1468 { "89hpes8nt2", 0 },
1469 { "89hpes12nt3", 0 },
1470
1471 { "89hpes24nt6ag2", 0 },
1472 { "89hpes32nt8ag2", 0 },
1473 { "89hpes32nt8bg2", 0 },
1474 { "89hpes12nt12g2", 0 },
1475 { "89hpes16nt16g2", 0 },
1476 { "89hpes24nt24g2", 0 },
1477 { "89hpes32nt24ag2", 0 },
1478 { "89hpes32nt24bg2", 0 },
1479
1480 { "89hpes12n3", 0 },
1481 { "89hpes12n3a", 0 },
1482 { "89hpes24n3", 0 },
1483 { "89hpes24n3a", 0 },
1484
1485 { "89hpes32h8", 0 },
1486 { "89hpes32h8g2", 0 },
1487 { "89hpes48h12", 0 },
1488 { "89hpes48h12g2", 0 },
1489 { "89hpes48h12ag2", 0 },
1490 { "89hpes16h16", 0 },
1491 { "89hpes22h16", 0 },
1492 { "89hpes22h16g2", 0 },
1493 { "89hpes34h16", 0 },
1494 { "89hpes34h16g2", 0 },
1495 { "89hpes64h16", 0 },
1496 { "89hpes64h16g2", 0 },
1497 { "89hpes64h16ag2", 0 },
1498
1499 /* { "89hpes3t3", 0 }, // No SMBus-slave iface */
1500 { "89hpes12t3g2", 0 },
1501 { "89hpes24t3g2", 0 },
1502 /* { "89hpes4t4", 0 }, // No SMBus-slave iface */
1503 { "89hpes16t4", 0 },
1504 { "89hpes4t4g2", 0 },
1505 { "89hpes10t4g2", 0 },
1506 { "89hpes16t4g2", 0 },
1507 { "89hpes16t4ag2", 0 },
1508 { "89hpes5t5", 0 },
1509 { "89hpes6t5", 0 },
1510 { "89hpes8t5", 0 },
1511 { "89hpes8t5a", 0 },
1512 { "89hpes24t6", 0 },
1513 { "89hpes6t6g2", 0 },
1514 { "89hpes24t6g2", 0 },
1515 { "89hpes16t7", 0 },
1516 { "89hpes32t8", 0 },
1517 { "89hpes32t8g2", 0 },
1518 { "89hpes48t12", 0 },
1519 { "89hpes48t12g2", 0 },
1520 { /* END OF LIST */ }
1521 };
1522 MODULE_DEVICE_TABLE(i2c, idt_ids);
1523
1524 static const struct of_device_id idt_of_match[] = {
1525 { .compatible = "idt,89hpes8nt2", },
1526 { .compatible = "idt,89hpes12nt3", },
1527
1528 { .compatible = "idt,89hpes24nt6ag2", },
1529 { .compatible = "idt,89hpes32nt8ag2", },
1530 { .compatible = "idt,89hpes32nt8bg2", },
1531 { .compatible = "idt,89hpes12nt12g2", },
1532 { .compatible = "idt,89hpes16nt16g2", },
1533 { .compatible = "idt,89hpes24nt24g2", },
1534 { .compatible = "idt,89hpes32nt24ag2", },
1535 { .compatible = "idt,89hpes32nt24bg2", },
1536
1537 { .compatible = "idt,89hpes12n3", },
1538 { .compatible = "idt,89hpes12n3a", },
1539 { .compatible = "idt,89hpes24n3", },
1540 { .compatible = "idt,89hpes24n3a", },
1541
1542 { .compatible = "idt,89hpes32h8", },
1543 { .compatible = "idt,89hpes32h8g2", },
1544 { .compatible = "idt,89hpes48h12", },
1545 { .compatible = "idt,89hpes48h12g2", },
1546 { .compatible = "idt,89hpes48h12ag2", },
1547 { .compatible = "idt,89hpes16h16", },
1548 { .compatible = "idt,89hpes22h16", },
1549 { .compatible = "idt,89hpes22h16g2", },
1550 { .compatible = "idt,89hpes34h16", },
1551 { .compatible = "idt,89hpes34h16g2", },
1552 { .compatible = "idt,89hpes64h16", },
1553 { .compatible = "idt,89hpes64h16g2", },
1554 { .compatible = "idt,89hpes64h16ag2", },
1555
1556 { .compatible = "idt,89hpes12t3g2", },
1557 { .compatible = "idt,89hpes24t3g2", },
1558
1559 { .compatible = "idt,89hpes16t4", },
1560 { .compatible = "idt,89hpes4t4g2", },
1561 { .compatible = "idt,89hpes10t4g2", },
1562 { .compatible = "idt,89hpes16t4g2", },
1563 { .compatible = "idt,89hpes16t4ag2", },
1564 { .compatible = "idt,89hpes5t5", },
1565 { .compatible = "idt,89hpes6t5", },
1566 { .compatible = "idt,89hpes8t5", },
1567 { .compatible = "idt,89hpes8t5a", },
1568 { .compatible = "idt,89hpes24t6", },
1569 { .compatible = "idt,89hpes6t6g2", },
1570 { .compatible = "idt,89hpes24t6g2", },
1571 { .compatible = "idt,89hpes16t7", },
1572 { .compatible = "idt,89hpes32t8", },
1573 { .compatible = "idt,89hpes32t8g2", },
1574 { .compatible = "idt,89hpes48t12", },
1575 { .compatible = "idt,89hpes48t12g2", },
1576 { },
1577 };
1578 MODULE_DEVICE_TABLE(of, idt_of_match);
1579
1580 /*
1581 * idt_driver - IDT 89HPESx driver structure
1582 */
1583 static struct i2c_driver idt_driver = {
1584 .driver = {
1585 .name = IDT_NAME,
1586 .of_match_table = idt_of_match,
1587 },
1588 .probe = idt_probe,
1589 .remove = idt_remove,
1590 .id_table = idt_ids,
1591 };
1592
1593 /*
1594 * idt_init() - IDT 89HPESx driver init() callback method
1595 */
1596 static int __init idt_init(void)
1597 {
1598 /* Create Debugfs directory first */
1599 if (debugfs_initialized())
1600 csr_dbgdir = debugfs_create_dir("idt_csr", NULL);
1601
1602 /* Add new i2c-device driver */
1603 return i2c_add_driver(&idt_driver);
1604 }
1605 module_init(idt_init);
1606
1607 /*
1608 * idt_exit() - IDT 89HPESx driver exit() callback method
1609 */
1610 static void __exit idt_exit(void)
1611 {
1612 /* Discard debugfs directory and all files if any */
1613 debugfs_remove_recursive(csr_dbgdir);
1614
1615 /* Unregister i2c-device driver */
1616 i2c_del_driver(&idt_driver);
1617 }
1618 module_exit(idt_exit);