This source file includes following definitions.
- alcor_write8
- alcor_write16
- alcor_write32
- alcor_write32be
- alcor_read8
- alcor_read32
- alcor_read32be
- alcor_pci_find_cap_offset
- alcor_pci_init_check_aspm
- alcor_pci_aspm_ctrl
- alcor_mask_sd_irqs
- alcor_unmask_sd_irqs
- alcor_mask_ms_irqs
- alcor_unmask_ms_irqs
- alcor_pci_probe
- alcor_pci_remove
- alcor_suspend
- alcor_resume
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8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/irq.h>
12 #include <linux/mfd/core.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm.h>
17
18 #include <linux/alcor_pci.h>
19
20 #define DRV_NAME_ALCOR_PCI "alcor_pci"
21
22 static DEFINE_IDA(alcor_pci_idr);
23
24 static struct mfd_cell alcor_pci_cells[] = {
25 [ALCOR_SD_CARD] = {
26 .name = DRV_NAME_ALCOR_PCI_SDMMC,
27 },
28 [ALCOR_MS_CARD] = {
29 .name = DRV_NAME_ALCOR_PCI_MS,
30 },
31 };
32
33 static const struct alcor_dev_cfg alcor_cfg = {
34 .dma = 0,
35 };
36
37 static const struct alcor_dev_cfg au6621_cfg = {
38 .dma = 1,
39 };
40
41 static const struct pci_device_id pci_ids[] = {
42 { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6601),
43 .driver_data = (kernel_ulong_t)&alcor_cfg },
44 { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6621),
45 .driver_data = (kernel_ulong_t)&au6621_cfg },
46 { },
47 };
48 MODULE_DEVICE_TABLE(pci, pci_ids);
49
50 void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr)
51 {
52 writeb(val, priv->iobase + addr);
53 }
54 EXPORT_SYMBOL_GPL(alcor_write8);
55
56 void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr)
57 {
58 writew(val, priv->iobase + addr);
59 }
60 EXPORT_SYMBOL_GPL(alcor_write16);
61
62 void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
63 {
64 writel(val, priv->iobase + addr);
65 }
66 EXPORT_SYMBOL_GPL(alcor_write32);
67
68 void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
69 {
70 iowrite32be(val, priv->iobase + addr);
71 }
72 EXPORT_SYMBOL_GPL(alcor_write32be);
73
74 u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr)
75 {
76 return readb(priv->iobase + addr);
77 }
78 EXPORT_SYMBOL_GPL(alcor_read8);
79
80 u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr)
81 {
82 return readl(priv->iobase + addr);
83 }
84 EXPORT_SYMBOL_GPL(alcor_read32);
85
86 u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr)
87 {
88 return ioread32be(priv->iobase + addr);
89 }
90 EXPORT_SYMBOL_GPL(alcor_read32be);
91
92 static int alcor_pci_find_cap_offset(struct alcor_pci_priv *priv,
93 struct pci_dev *pci)
94 {
95 int where;
96 u8 val8;
97 u32 val32;
98
99 where = ALCOR_CAP_START_OFFSET;
100 pci_read_config_byte(pci, where, &val8);
101 if (!val8)
102 return 0;
103
104 where = (int)val8;
105 while (1) {
106 pci_read_config_dword(pci, where, &val32);
107 if (val32 == 0xffffffff) {
108 dev_dbg(priv->dev, "find_cap_offset invalid value %x.\n",
109 val32);
110 return 0;
111 }
112
113 if ((val32 & 0xff) == 0x10) {
114 dev_dbg(priv->dev, "pcie cap offset: %x\n", where);
115 return where;
116 }
117
118 if ((val32 & 0xff00) == 0x00) {
119 dev_dbg(priv->dev, "pci_find_cap_offset invalid value %x.\n",
120 val32);
121 break;
122 }
123 where = (int)((val32 >> 8) & 0xff);
124 }
125
126 return 0;
127 }
128
129 static void alcor_pci_init_check_aspm(struct alcor_pci_priv *priv)
130 {
131 struct pci_dev *pci;
132 int where;
133 u32 val32;
134
135 priv->pdev_cap_off = alcor_pci_find_cap_offset(priv, priv->pdev);
136 priv->parent_cap_off = alcor_pci_find_cap_offset(priv,
137 priv->parent_pdev);
138
139 if ((priv->pdev_cap_off == 0) || (priv->parent_cap_off == 0)) {
140 dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
141 priv->pdev_cap_off, priv->parent_cap_off);
142 return;
143 }
144
145
146 pci = priv->pdev;
147 where = priv->pdev_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
148 pci_read_config_dword(pci, where, &val32);
149 priv->pdev_aspm_cap = (u8)(val32 >> 10) & 0x03;
150
151 pci = priv->parent_pdev;
152 where = priv->parent_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
153 pci_read_config_dword(pci, where, &val32);
154 priv->parent_aspm_cap = (u8)(val32 >> 10) & 0x03;
155
156 if (priv->pdev_aspm_cap != priv->parent_aspm_cap) {
157 u8 aspm_cap;
158
159 dev_dbg(priv->dev, "pdev_aspm_cap: %x, parent_aspm_cap: %x\n",
160 priv->pdev_aspm_cap, priv->parent_aspm_cap);
161 aspm_cap = priv->pdev_aspm_cap & priv->parent_aspm_cap;
162 priv->pdev_aspm_cap = aspm_cap;
163 priv->parent_aspm_cap = aspm_cap;
164 }
165
166 dev_dbg(priv->dev, "ext_config_dev_aspm: %x, pdev_aspm_cap: %x\n",
167 priv->ext_config_dev_aspm, priv->pdev_aspm_cap);
168 priv->ext_config_dev_aspm &= priv->pdev_aspm_cap;
169 }
170
171 static void alcor_pci_aspm_ctrl(struct alcor_pci_priv *priv, u8 aspm_enable)
172 {
173 struct pci_dev *pci;
174 u8 aspm_ctrl, i;
175 int where;
176 u32 val32;
177
178 if ((!priv->pdev_cap_off) || (!priv->parent_cap_off)) {
179 dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
180 priv->pdev_cap_off, priv->parent_cap_off);
181 return;
182 }
183
184 if (!priv->pdev_aspm_cap)
185 return;
186
187 aspm_ctrl = 0;
188 if (aspm_enable) {
189 aspm_ctrl = priv->ext_config_dev_aspm;
190
191 if (!aspm_ctrl) {
192 dev_dbg(priv->dev, "aspm_ctrl == 0\n");
193 return;
194 }
195 }
196
197 for (i = 0; i < 2; i++) {
198
199 if (i) {
200 pci = priv->parent_pdev;
201 where = priv->parent_cap_off
202 + ALCOR_PCIE_LINK_CTRL_OFFSET;
203 } else {
204 pci = priv->pdev;
205 where = priv->pdev_cap_off
206 + ALCOR_PCIE_LINK_CTRL_OFFSET;
207 }
208
209 pci_read_config_dword(pci, where, &val32);
210 val32 &= (~0x03);
211 val32 |= (aspm_ctrl & priv->pdev_aspm_cap);
212 pci_write_config_byte(pci, where, (u8)val32);
213 }
214
215 }
216
217 static inline void alcor_mask_sd_irqs(struct alcor_pci_priv *priv)
218 {
219 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
220 }
221
222 static inline void alcor_unmask_sd_irqs(struct alcor_pci_priv *priv)
223 {
224 alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
225 AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
226 AU6601_INT_OVER_CURRENT_ERR,
227 AU6601_REG_INT_ENABLE);
228 }
229
230 static inline void alcor_mask_ms_irqs(struct alcor_pci_priv *priv)
231 {
232 alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
233 }
234
235 static inline void alcor_unmask_ms_irqs(struct alcor_pci_priv *priv)
236 {
237 alcor_write32(priv, 0x3d00fa, AU6601_MS_INT_ENABLE);
238 }
239
240 static int alcor_pci_probe(struct pci_dev *pdev,
241 const struct pci_device_id *ent)
242 {
243 struct alcor_dev_cfg *cfg;
244 struct alcor_pci_priv *priv;
245 int ret, i, bar = 0;
246
247 cfg = (void *)ent->driver_data;
248
249 ret = pcim_enable_device(pdev);
250 if (ret)
251 return ret;
252
253 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
254 if (!priv)
255 return -ENOMEM;
256
257 ret = ida_simple_get(&alcor_pci_idr, 0, 0, GFP_KERNEL);
258 if (ret < 0)
259 return ret;
260 priv->id = ret;
261
262 priv->pdev = pdev;
263 priv->parent_pdev = pdev->bus->self;
264 priv->dev = &pdev->dev;
265 priv->cfg = cfg;
266 priv->irq = pdev->irq;
267
268 ret = pci_request_regions(pdev, DRV_NAME_ALCOR_PCI);
269 if (ret) {
270 dev_err(&pdev->dev, "Cannot request region\n");
271 return -ENOMEM;
272 }
273
274 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
275 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
276 ret = -ENODEV;
277 goto error_release_regions;
278 }
279
280 priv->iobase = pcim_iomap(pdev, bar, 0);
281 if (!priv->iobase) {
282 ret = -ENOMEM;
283 goto error_release_regions;
284 }
285
286
287 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
288 alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
289
290 ret = dma_set_mask_and_coherent(priv->dev, AU6601_SDMA_MASK);
291 if (ret) {
292 dev_err(priv->dev, "Failed to set DMA mask\n");
293 goto error_release_regions;
294 }
295
296 pci_set_master(pdev);
297 pci_set_drvdata(pdev, priv);
298 alcor_pci_init_check_aspm(priv);
299
300 for (i = 0; i < ARRAY_SIZE(alcor_pci_cells); i++) {
301 alcor_pci_cells[i].platform_data = priv;
302 alcor_pci_cells[i].pdata_size = sizeof(*priv);
303 }
304 ret = mfd_add_devices(&pdev->dev, priv->id, alcor_pci_cells,
305 ARRAY_SIZE(alcor_pci_cells), NULL, 0, NULL);
306 if (ret < 0)
307 goto error_release_regions;
308
309 alcor_pci_aspm_ctrl(priv, 0);
310
311 return 0;
312
313 error_release_regions:
314 pci_release_regions(pdev);
315 return ret;
316 }
317
318 static void alcor_pci_remove(struct pci_dev *pdev)
319 {
320 struct alcor_pci_priv *priv;
321
322 priv = pci_get_drvdata(pdev);
323
324 alcor_pci_aspm_ctrl(priv, 1);
325
326 mfd_remove_devices(&pdev->dev);
327
328 ida_simple_remove(&alcor_pci_idr, priv->id);
329
330 pci_release_regions(pdev);
331 pci_set_drvdata(pdev, NULL);
332 }
333
334 #ifdef CONFIG_PM_SLEEP
335 static int alcor_suspend(struct device *dev)
336 {
337 struct alcor_pci_priv *priv = dev_get_drvdata(dev);
338
339 alcor_pci_aspm_ctrl(priv, 1);
340 return 0;
341 }
342
343 static int alcor_resume(struct device *dev)
344 {
345
346 struct alcor_pci_priv *priv = dev_get_drvdata(dev);
347
348 alcor_pci_aspm_ctrl(priv, 0);
349 return 0;
350 }
351 #endif
352
353 static SIMPLE_DEV_PM_OPS(alcor_pci_pm_ops, alcor_suspend, alcor_resume);
354
355 static struct pci_driver alcor_driver = {
356 .name = DRV_NAME_ALCOR_PCI,
357 .id_table = pci_ids,
358 .probe = alcor_pci_probe,
359 .remove = alcor_pci_remove,
360 .driver = {
361 .pm = &alcor_pci_pm_ops
362 },
363 };
364
365 module_pci_driver(alcor_driver);
366
367 MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
368 MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
369 MODULE_LICENSE("GPL");