root/drivers/misc/cxl/cxl.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. cxl_adapter_link_ok
  2. _cxl_p1_addr
  3. cxl_p1_write
  4. cxl_p1_read
  5. _cxl_p1n_addr
  6. cxl_p1n_write
  7. cxl_p1n_read
  8. _cxl_p2n_addr
  9. cxl_p2n_write
  10. cxl_p2n_read
  11. cxl_is_power8
  12. cxl_is_power9
  13. cxl_debugfs_init
  14. cxl_debugfs_exit
  15. cxl_debugfs_adapter_add
  16. cxl_debugfs_adapter_remove
  17. cxl_debugfs_afu_add
  18. cxl_debugfs_afu_remove
  19. cxl_debugfs_add_adapter_regs_psl9
  20. cxl_debugfs_add_adapter_regs_psl8
  21. cxl_debugfs_add_afu_regs_psl9
  22. cxl_debugfs_add_afu_regs_psl8
   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2014 IBM Corp.
   4  */
   5 
   6 #ifndef _CXL_H_
   7 #define _CXL_H_
   8 
   9 #include <linux/interrupt.h>
  10 #include <linux/semaphore.h>
  11 #include <linux/device.h>
  12 #include <linux/types.h>
  13 #include <linux/cdev.h>
  14 #include <linux/pid.h>
  15 #include <linux/io.h>
  16 #include <linux/pci.h>
  17 #include <linux/fs.h>
  18 #include <asm/cputable.h>
  19 #include <asm/mmu.h>
  20 #include <asm/reg.h>
  21 #include <misc/cxl-base.h>
  22 
  23 #include <misc/cxl.h>
  24 #include <uapi/misc/cxl.h>
  25 
  26 extern uint cxl_verbose;
  27 
  28 #define CXL_TIMEOUT 5
  29 
  30 /*
  31  * Bump version each time a user API change is made, whether it is
  32  * backwards compatible ot not.
  33  */
  34 #define CXL_API_VERSION 3
  35 #define CXL_API_VERSION_COMPATIBLE 1
  36 
  37 /*
  38  * Opaque types to avoid accidentally passing registers for the wrong MMIO
  39  *
  40  * At the end of the day, I'm not married to using typedef here, but it might
  41  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  42  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  43  *
  44  * I'm quite happy if these are changed back to #defines before upstreaming, it
  45  * should be little more than a regexp search+replace operation in this file.
  46  */
  47 typedef struct {
  48         const int x;
  49 } cxl_p1_reg_t;
  50 typedef struct {
  51         const int x;
  52 } cxl_p1n_reg_t;
  53 typedef struct {
  54         const int x;
  55 } cxl_p2n_reg_t;
  56 #define cxl_reg_off(reg) \
  57         (reg.x)
  58 
  59 /* Memory maps. Ref CXL Appendix A */
  60 
  61 /* PSL Privilege 1 Memory Map */
  62 /* Configuration and Control area - CAIA 1&2 */
  63 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  64 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  65 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  66 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  67 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  68 /* Downloading */
  69 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  70 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  71 
  72 /* PSL Lookaside Buffer Management Area - CAIA 1 */
  73 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  74 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  75 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  76 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  77 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  78 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  79 
  80 /* 0x00C0:7EFF Implementation dependent area */
  81 /* PSL registers - CAIA 1 */
  82 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  83 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  84 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  85 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  86 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  87 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  88 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  89 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  90 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  91 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  92 /* PSL registers - CAIA 2 */
  93 static const cxl_p1_reg_t CXL_PSL9_CONTROL  = {0x0020};
  94 static const cxl_p1_reg_t CXL_XSL9_INV      = {0x0110};
  95 static const cxl_p1_reg_t CXL_XSL9_DBG      = {0x0130};
  96 static const cxl_p1_reg_t CXL_XSL9_DEF      = {0x0140};
  97 static const cxl_p1_reg_t CXL_XSL9_DSNCTL   = {0x0168};
  98 static const cxl_p1_reg_t CXL_PSL9_FIR1     = {0x0300};
  99 static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
 100 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
 101 static const cxl_p1_reg_t CXL_PSL9_DEBUG    = {0x0320};
 102 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
 103 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL  = {0x0350};
 104 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
 105 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
 106 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
 107 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
 108 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
 109 static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
 110 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
 111 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
 112 static const cxl_p1_reg_t CXL_XSL9_ILPP  = {0x0590};
 113 
 114 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
 115 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
 116 
 117 /* PSL Slice Privilege 1 Memory Map */
 118 /* Configuration Area - CAIA 1&2 */
 119 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 120 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 121 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 122 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 123 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 124 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 125 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
 126 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 127 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
 128 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 129 /* Pointer Area - CAIA 1&2 */
 130 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 131 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 132 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 133 /* Control Area - CAIA 1&2 */
 134 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 135 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 136 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 137 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 138 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
 139 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 140 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 141 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
 142 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 143 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 144 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 145 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 146 
 147 /* PSL Slice Privilege 2 Memory Map */
 148 /* Configuration and Control Area - CAIA 1&2 */
 149 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 150 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 151 /* Configuration and Control Area - CAIA 1 */
 152 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 153 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 154 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 155 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 156 /* Configuration and Control Area - CAIA 1 */
 157 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 158 /* Segment Lookaside Buffer Management - CAIA 1 */
 159 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 160 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 161 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 162 /* Interrupt Registers - CAIA 1&2 */
 163 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 164 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 165 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 166 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 167 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 168 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 169 /* AFU Registers - CAIA 1&2 */
 170 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 171 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 172 /* Work Element Descriptor - CAIA 1&2 */
 173 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 174 /* 0x0C0:FFF Implementation Dependent Area */
 175 
 176 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 177 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 178 #define CXL_PSL_SPAP_Size_Shift 4
 179 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
 180 
 181 /****** CXL_PSL_Control ****************************************************/
 182 #define CXL_PSL_Control_tb              (0x1ull << (63-63))
 183 #define CXL_PSL_Control_Fr              (0x1ull << (63-31))
 184 #define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
 185 #define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
 186 
 187 /****** CXL_PSL_DLCNTL *****************************************************/
 188 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 189 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 190 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 191 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 192 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 193 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 194 
 195 /****** CXL_PSL_SR_An ******************************************************/
 196 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 197 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 198 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 199 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
 200 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
 201 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
 202 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
 203 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 204 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 205 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 206 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 207 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 208 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 209 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 210 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 211 
 212 /****** CXL_PSL_ID_An ****************************************************/
 213 #define CXL_PSL_ID_An_F (1ull << (63-31))
 214 #define CXL_PSL_ID_An_L (1ull << (63-30))
 215 
 216 /****** CXL_PSL_SERR_An ****************************************************/
 217 #define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
 218 #define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
 219 #define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
 220 #define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
 221 #define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
 222 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
 223 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
 224 #define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
 225 #define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
 226 #define CXL_PSL_SERR_An_IRQS    ( \
 227         CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
 228         CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
 229         CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
 230 #define CXL_PSL_SERR_An_afuto_mask      (1ull << (63-32))
 231 #define CXL_PSL_SERR_An_afudis_mask     (1ull << (63-33))
 232 #define CXL_PSL_SERR_An_afuov_mask      (1ull << (63-34))
 233 #define CXL_PSL_SERR_An_badsrc_mask     (1ull << (63-35))
 234 #define CXL_PSL_SERR_An_badctx_mask     (1ull << (63-36))
 235 #define CXL_PSL_SERR_An_llcmdis_mask    (1ull << (63-37))
 236 #define CXL_PSL_SERR_An_llcmdto_mask    (1ull << (63-38))
 237 #define CXL_PSL_SERR_An_afupar_mask     (1ull << (63-39))
 238 #define CXL_PSL_SERR_An_afudup_mask     (1ull << (63-40))
 239 #define CXL_PSL_SERR_An_IRQ_MASKS       ( \
 240         CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
 241         CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
 242         CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
 243 
 244 #define CXL_PSL_SERR_An_AE      (1ull << (63-30))
 245 
 246 /****** CXL_PSL_SCNTL_An ****************************************************/
 247 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 248 /* Programming Modes: */
 249 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 250 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 251 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 252 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 253 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 254 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 255 /* Purge Status (ro) */
 256 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 257 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 258 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 259 /* Purge */
 260 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 261 /* Suspend Status (ro) */
 262 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 263 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 264 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 265 /* Suspend Control */
 266 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 267 
 268 /* AFU Slice Enable Status (ro) */
 269 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 270 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 271 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 272 /* AFU Slice Enable */
 273 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 274 /* AFU Slice Reset status (ro) */
 275 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 276 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 277 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 278 /* AFU Slice Reset */
 279 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 280 
 281 /****** CXL_SSTP0/1_An ******************************************************/
 282 /* These top bits are for the segment that CONTAINS the segment table */
 283 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 284 #define CXL_SSTP0_An_KS             (1ull << (63-2))
 285 #define CXL_SSTP0_An_KP             (1ull << (63-3))
 286 #define CXL_SSTP0_An_N              (1ull << (63-4))
 287 #define CXL_SSTP0_An_L              (1ull << (63-5))
 288 #define CXL_SSTP0_An_C              (1ull << (63-6))
 289 #define CXL_SSTP0_An_TA             (1ull << (63-7))
 290 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 291 /* And finally, the virtual address & size of the segment table: */
 292 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 293 #define CXL_SSTP0_An_SegTableSize_MASK \
 294         (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 295 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 296 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 297 #define CXL_SSTP1_An_V              (1ull << (63-63))
 298 
 299 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
 300 /* write: */
 301 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 302 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 303 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 304 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 305 /* read: */
 306 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 307 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 308 
 309 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
 310 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 311 
 312 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
 313 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 314 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 315 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 316 
 317 /****** CXL_PSL_AFUSEL ******************************************************/
 318 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 319 
 320 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
 321 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 322 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 323 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 324 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 325 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 326 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 327 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 328 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 329 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 330 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 331 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 332 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 333 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 334 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 335 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 336 
 337 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
 338 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3))  /* Translation fault */
 339 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 340 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 341 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 342 #define CXL_PSL9_DSISR_An_S (1ull << (63-38))  /* TF for a write operation */
 343 #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
 344 /*
 345  * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
 346  * Status (0:7) Encoding
 347  */
 348 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
 349 #define CXL_PSL9_DSISR_An_SF      0x0000000000000080ULL  /* Segment Fault                        0b10000000 */
 350 #define CXL_PSL9_DSISR_An_PF_SLR  0x0000000000000088ULL  /* PTE not found (Single Level Radix)   0b10001000 */
 351 #define CXL_PSL9_DSISR_An_PF_RGC  0x000000000000008CULL  /* PTE not found (Radix Guest (child))  0b10001100 */
 352 #define CXL_PSL9_DSISR_An_PF_RGP  0x0000000000000090ULL  /* PTE not found (Radix Guest (parent)) 0b10010000 */
 353 #define CXL_PSL9_DSISR_An_PF_HRH  0x0000000000000094ULL  /* PTE not found (HPT/Radix Host)       0b10010100 */
 354 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL  /* PTE not found (STEG VA)              0b10011100 */
 355 #define CXL_PSL9_DSISR_An_URTCH   0x00000000000000B4ULL  /* Unsupported Radix Tree Configuration 0b10110100 */
 356 
 357 /****** CXL_PSL_TFC_An ******************************************************/
 358 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 359 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 360 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 361 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 362 
 363 /****** CXL_PSL_DEBUG *****************************************************/
 364 #define CXL_PSL_DEBUG_CDC  (1ull << (63-27)) /* Coherent Data cache support */
 365 
 366 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
 367 #define CXL_XSL9_IERAT_MLPID    (1ull << (63-0))  /* Match LPID */
 368 #define CXL_XSL9_IERAT_MPID     (1ull << (63-1))  /* Match PID */
 369 #define CXL_XSL9_IERAT_PRS      (1ull << (63-4))  /* PRS bit for Radix invalidations */
 370 #define CXL_XSL9_IERAT_INVR     (1ull << (63-3))  /* Invalidate Radix */
 371 #define CXL_XSL9_IERAT_IALL     (1ull << (63-8))  /* Invalidate All */
 372 #define CXL_XSL9_IERAT_IINPROG  (1ull << (63-63)) /* Invalidate in progress */
 373 
 374 /* cxl_process_element->software_status */
 375 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 376 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 377 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 378 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 379 
 380 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 381  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 382  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 383  * of the hang pulse frequency.
 384  */
 385 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 386 
 387 /* SPA->sw_command_status */
 388 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 389 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 390 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 391 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 392 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 393 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 394 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 395 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 396 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 397 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 398 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 399 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 400 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 401 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 402 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 403 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 404 
 405 #define CXL_MAX_SLICES 4
 406 #define MAX_AFU_MMIO_REGS 3
 407 
 408 #define CXL_MODE_TIME_SLICED 0x4
 409 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 410 
 411 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
 412 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
 413 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
 414 
 415 #define CXL_PSL9_TRACEID_MAX 0xAU
 416 #define CXL_PSL9_TRACESTATE_FIN 0x3U
 417 
 418 enum cxl_context_status {
 419         CLOSED,
 420         OPENED,
 421         STARTED
 422 };
 423 
 424 enum prefault_modes {
 425         CXL_PREFAULT_NONE,
 426         CXL_PREFAULT_WED,
 427         CXL_PREFAULT_ALL,
 428 };
 429 
 430 enum cxl_attrs {
 431         CXL_ADAPTER_ATTRS,
 432         CXL_AFU_MASTER_ATTRS,
 433         CXL_AFU_ATTRS,
 434 };
 435 
 436 struct cxl_sste {
 437         __be64 esid_data;
 438         __be64 vsid_data;
 439 };
 440 
 441 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 442 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 443 
 444 struct cxl_afu_native {
 445         void __iomem *p1n_mmio;
 446         void __iomem *afu_desc_mmio;
 447         irq_hw_number_t psl_hwirq;
 448         unsigned int psl_virq;
 449         struct mutex spa_mutex;
 450         /*
 451          * Only the first part of the SPA is used for the process element
 452          * linked list. The only other part that software needs to worry about
 453          * is sw_command_status, which we store a separate pointer to.
 454          * Everything else in the SPA is only used by hardware
 455          */
 456         struct cxl_process_element *spa;
 457         __be64 *sw_command_status;
 458         unsigned int spa_size;
 459         int spa_order;
 460         int spa_max_procs;
 461         u64 pp_offset;
 462 };
 463 
 464 struct cxl_afu_guest {
 465         struct cxl_afu *parent;
 466         u64 handle;
 467         phys_addr_t p2n_phys;
 468         u64 p2n_size;
 469         int max_ints;
 470         bool handle_err;
 471         struct delayed_work work_err;
 472         int previous_state;
 473 };
 474 
 475 struct cxl_afu {
 476         struct cxl_afu_native *native;
 477         struct cxl_afu_guest *guest;
 478         irq_hw_number_t serr_hwirq;
 479         unsigned int serr_virq;
 480         char *psl_irq_name;
 481         char *err_irq_name;
 482         void __iomem *p2n_mmio;
 483         phys_addr_t psn_phys;
 484         u64 pp_size;
 485 
 486         struct cxl *adapter;
 487         struct device dev;
 488         struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 489         struct device *chardev_s, *chardev_m, *chardev_d;
 490         struct idr contexts_idr;
 491         struct dentry *debugfs;
 492         struct mutex contexts_lock;
 493         spinlock_t afu_cntl_lock;
 494 
 495         /* -1: AFU deconfigured/locked, >= 0: number of readers */
 496         atomic_t configured_state;
 497 
 498         /* AFU error buffer fields and bin attribute for sysfs */
 499         u64 eb_len, eb_offset;
 500         struct bin_attribute attr_eb;
 501 
 502         /* pointer to the vphb */
 503         struct pci_controller *phb;
 504 
 505         int pp_irqs;
 506         int irqs_max;
 507         int num_procs;
 508         int max_procs_virtualised;
 509         int slice;
 510         int modes_supported;
 511         int current_mode;
 512         int crs_num;
 513         u64 crs_len;
 514         u64 crs_offset;
 515         struct list_head crs;
 516         enum prefault_modes prefault_mode;
 517         bool psa;
 518         bool pp_psa;
 519         bool enabled;
 520 };
 521 
 522 
 523 struct cxl_irq_name {
 524         struct list_head list;
 525         char *name;
 526 };
 527 
 528 struct irq_avail {
 529         irq_hw_number_t offset;
 530         irq_hw_number_t range;
 531         unsigned long   *bitmap;
 532 };
 533 
 534 /*
 535  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 536  * of these per AFU.  If in AFU directed there can be lots of these.
 537  */
 538 struct cxl_context {
 539         struct cxl_afu *afu;
 540 
 541         /* Problem state MMIO */
 542         phys_addr_t psn_phys;
 543         u64 psn_size;
 544 
 545         /* Used to unmap any mmaps when force detaching */
 546         struct address_space *mapping;
 547         struct mutex mapping_lock;
 548         struct page *ff_page;
 549         bool mmio_err_ff;
 550         bool kernelapi;
 551 
 552         spinlock_t sste_lock; /* Protects segment table entries */
 553         struct cxl_sste *sstp;
 554         u64 sstp0, sstp1;
 555         unsigned int sst_size, sst_lru;
 556 
 557         wait_queue_head_t wq;
 558         /* use mm context associated with this pid for ds faults */
 559         struct pid *pid;
 560         spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 561         /* Only used in PR mode */
 562         u64 process_token;
 563 
 564         /* driver private data */
 565         void *priv;
 566 
 567         unsigned long *irq_bitmap; /* Accessed from IRQ context */
 568         struct cxl_irq_ranges irqs;
 569         struct list_head irq_names;
 570         u64 fault_addr;
 571         u64 fault_dsisr;
 572         u64 afu_err;
 573 
 574         /*
 575          * This status and it's lock pretects start and detach context
 576          * from racing.  It also prevents detach from racing with
 577          * itself
 578          */
 579         enum cxl_context_status status;
 580         struct mutex status_mutex;
 581 
 582 
 583         /* XXX: Is it possible to need multiple work items at once? */
 584         struct work_struct fault_work;
 585         u64 dsisr;
 586         u64 dar;
 587 
 588         struct cxl_process_element *elem;
 589 
 590         /*
 591          * pe is the process element handle, assigned by this driver when the
 592          * context is initialized.
 593          *
 594          * external_pe is the PE shown outside of cxl.
 595          * On bare-metal, pe=external_pe, because we decide what the handle is.
 596          * In a guest, we only find out about the pe used by pHyp when the
 597          * context is attached, and that's the value we want to report outside
 598          * of cxl.
 599          */
 600         int pe;
 601         int external_pe;
 602 
 603         u32 irq_count;
 604         bool pe_inserted;
 605         bool master;
 606         bool kernel;
 607         bool pending_irq;
 608         bool pending_fault;
 609         bool pending_afu_err;
 610 
 611         /* Used by AFU drivers for driver specific event delivery */
 612         struct cxl_afu_driver_ops *afu_driver_ops;
 613         atomic_t afu_driver_events;
 614 
 615         struct rcu_head rcu;
 616 
 617         struct mm_struct *mm;
 618 
 619         u16 tidr;
 620         bool assign_tidr;
 621 };
 622 
 623 struct cxl_irq_info;
 624 
 625 struct cxl_service_layer_ops {
 626         int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
 627         int (*invalidate_all)(struct cxl *adapter);
 628         int (*afu_regs_init)(struct cxl_afu *afu);
 629         int (*sanitise_afu_regs)(struct cxl_afu *afu);
 630         int (*register_serr_irq)(struct cxl_afu *afu);
 631         void (*release_serr_irq)(struct cxl_afu *afu);
 632         irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 633         irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
 634         int (*activate_dedicated_process)(struct cxl_afu *afu);
 635         int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
 636         int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
 637         void (*update_dedicated_ivtes)(struct cxl_context *ctx);
 638         void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
 639         void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
 640         void (*psl_irq_dump_registers)(struct cxl_context *ctx);
 641         void (*err_irq_dump_registers)(struct cxl *adapter);
 642         void (*debugfs_stop_trace)(struct cxl *adapter);
 643         void (*write_timebase_ctrl)(struct cxl *adapter);
 644         u64 (*timebase_read)(struct cxl *adapter);
 645         int capi_mode;
 646         bool needs_reset_before_disable;
 647 };
 648 
 649 struct cxl_native {
 650         u64 afu_desc_off;
 651         u64 afu_desc_size;
 652         void __iomem *p1_mmio;
 653         void __iomem *p2_mmio;
 654         irq_hw_number_t err_hwirq;
 655         unsigned int err_virq;
 656         u64 ps_off;
 657         bool no_data_cache; /* set if no data cache on the card */
 658         const struct cxl_service_layer_ops *sl_ops;
 659 };
 660 
 661 struct cxl_guest {
 662         struct platform_device *pdev;
 663         int irq_nranges;
 664         struct cdev cdev;
 665         irq_hw_number_t irq_base_offset;
 666         struct irq_avail *irq_avail;
 667         spinlock_t irq_alloc_lock;
 668         u64 handle;
 669         char *status;
 670         u16 vendor;
 671         u16 device;
 672         u16 subsystem_vendor;
 673         u16 subsystem;
 674 };
 675 
 676 struct cxl {
 677         struct cxl_native *native;
 678         struct cxl_guest *guest;
 679         spinlock_t afu_list_lock;
 680         struct cxl_afu *afu[CXL_MAX_SLICES];
 681         struct device dev;
 682         struct dentry *trace;
 683         struct dentry *psl_err_chk;
 684         struct dentry *debugfs;
 685         char *irq_name;
 686         struct bin_attribute cxl_attr;
 687         int adapter_num;
 688         int user_irqs;
 689         u64 ps_size;
 690         u16 psl_rev;
 691         u16 base_image;
 692         u8 vsec_status;
 693         u8 caia_major;
 694         u8 caia_minor;
 695         u8 slices;
 696         bool user_image_loaded;
 697         bool perst_loads_image;
 698         bool perst_select_user;
 699         bool perst_same_image;
 700         bool psl_timebase_synced;
 701         bool tunneled_ops_supported;
 702 
 703         /*
 704          * number of contexts mapped on to this card. Possible values are:
 705          * >0: Number of contexts mapped and new one can be mapped.
 706          *  0: No active contexts and new ones can be mapped.
 707          * -1: No contexts mapped and new ones cannot be mapped.
 708          */
 709         atomic_t contexts_num;
 710 };
 711 
 712 int cxl_pci_alloc_one_irq(struct cxl *adapter);
 713 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
 714 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 715 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 716 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 717 int cxl_update_image_control(struct cxl *adapter);
 718 int cxl_pci_reset(struct cxl *adapter);
 719 void cxl_pci_release_afu(struct device *dev);
 720 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 721 
 722 /* common == phyp + powernv - CAIA 1&2 */
 723 struct cxl_process_element_common {
 724         __be32 tid;
 725         __be32 pid;
 726         __be64 csrp;
 727         union {
 728                 struct {
 729                         __be64 aurp0;
 730                         __be64 aurp1;
 731                         __be64 sstp0;
 732                         __be64 sstp1;
 733                 } psl8;  /* CAIA 1 */
 734                 struct {
 735                         u8     reserved2[8];
 736                         u8     reserved3[8];
 737                         u8     reserved4[8];
 738                         u8     reserved5[8];
 739                 } psl9;  /* CAIA 2 */
 740         } u;
 741         __be64 amr;
 742         u8     reserved6[4];
 743         __be64 wed;
 744 } __packed;
 745 
 746 /* just powernv - CAIA 1&2 */
 747 struct cxl_process_element {
 748         __be64 sr;
 749         __be64 SPOffset;
 750         union {
 751                 __be64 sdr;          /* CAIA 1 */
 752                 u8     reserved1[8]; /* CAIA 2 */
 753         } u;
 754         __be64 haurp;
 755         __be32 ctxtime;
 756         __be16 ivte_offsets[4];
 757         __be16 ivte_ranges[4];
 758         __be32 lpid;
 759         struct cxl_process_element_common common;
 760         __be32 software_state;
 761 } __packed;
 762 
 763 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
 764 {
 765         struct pci_dev *pdev;
 766 
 767         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 768                 pdev = to_pci_dev(cxl->dev.parent);
 769                 return !pci_channel_offline(pdev);
 770         }
 771         return true;
 772 }
 773 
 774 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 775 {
 776         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 777         return cxl->native->p1_mmio + cxl_reg_off(reg);
 778 }
 779 
 780 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 781 {
 782         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 783                 out_be64(_cxl_p1_addr(cxl, reg), val);
 784 }
 785 
 786 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 787 {
 788         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 789                 return in_be64(_cxl_p1_addr(cxl, reg));
 790         else
 791                 return ~0ULL;
 792 }
 793 
 794 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 795 {
 796         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 797         return afu->native->p1n_mmio + cxl_reg_off(reg);
 798 }
 799 
 800 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 801 {
 802         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 803                 out_be64(_cxl_p1n_addr(afu, reg), val);
 804 }
 805 
 806 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 807 {
 808         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 809                 return in_be64(_cxl_p1n_addr(afu, reg));
 810         else
 811                 return ~0ULL;
 812 }
 813 
 814 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 815 {
 816         return afu->p2n_mmio + cxl_reg_off(reg);
 817 }
 818 
 819 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 820 {
 821         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 822                 out_be64(_cxl_p2n_addr(afu, reg), val);
 823 }
 824 
 825 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 826 {
 827         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 828                 return in_be64(_cxl_p2n_addr(afu, reg));
 829         else
 830                 return ~0ULL;
 831 }
 832 
 833 static inline bool cxl_is_power8(void)
 834 {
 835         if ((pvr_version_is(PVR_POWER8E)) ||
 836             (pvr_version_is(PVR_POWER8NVL)) ||
 837             (pvr_version_is(PVR_POWER8)))
 838                 return true;
 839         return false;
 840 }
 841 
 842 static inline bool cxl_is_power9(void)
 843 {
 844         if (pvr_version_is(PVR_POWER9))
 845                 return true;
 846         return false;
 847 }
 848 
 849 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 850                                 loff_t off, size_t count);
 851 
 852 
 853 struct cxl_calls {
 854         void (*cxl_slbia)(struct mm_struct *mm);
 855         struct module *owner;
 856 };
 857 int register_cxl_calls(struct cxl_calls *calls);
 858 void unregister_cxl_calls(struct cxl_calls *calls);
 859 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
 860 
 861 void cxl_remove_adapter_nr(struct cxl *adapter);
 862 
 863 void cxl_release_spa(struct cxl_afu *afu);
 864 
 865 dev_t cxl_get_dev(void);
 866 int cxl_file_init(void);
 867 void cxl_file_exit(void);
 868 int cxl_register_adapter(struct cxl *adapter);
 869 int cxl_register_afu(struct cxl_afu *afu);
 870 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 871 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 872 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 873 void cxl_chardev_afu_remove(struct cxl_afu *afu);
 874 
 875 void cxl_context_detach_all(struct cxl_afu *afu);
 876 void cxl_context_free(struct cxl_context *ctx);
 877 void cxl_context_detach(struct cxl_context *ctx);
 878 
 879 int cxl_sysfs_adapter_add(struct cxl *adapter);
 880 void cxl_sysfs_adapter_remove(struct cxl *adapter);
 881 int cxl_sysfs_afu_add(struct cxl_afu *afu);
 882 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 883 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 884 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 885 
 886 struct cxl *cxl_alloc_adapter(void);
 887 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
 888 int cxl_afu_select_best_mode(struct cxl_afu *afu);
 889 
 890 int cxl_native_register_psl_irq(struct cxl_afu *afu);
 891 void cxl_native_release_psl_irq(struct cxl_afu *afu);
 892 int cxl_native_register_psl_err_irq(struct cxl *adapter);
 893 void cxl_native_release_psl_err_irq(struct cxl *adapter);
 894 int cxl_native_register_serr_irq(struct cxl_afu *afu);
 895 void cxl_native_release_serr_irq(struct cxl_afu *afu);
 896 int afu_register_irqs(struct cxl_context *ctx, u32 count);
 897 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 898 void afu_irq_name_free(struct cxl_context *ctx);
 899 
 900 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 901 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 902 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
 903 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
 904 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 905 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 906 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
 907 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
 908 
 909 #ifdef CONFIG_DEBUG_FS
 910 
 911 void cxl_debugfs_init(void);
 912 void cxl_debugfs_exit(void);
 913 void cxl_debugfs_adapter_add(struct cxl *adapter);
 914 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 915 void cxl_debugfs_afu_add(struct cxl_afu *afu);
 916 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 917 void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
 918 void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
 919 void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
 920 void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
 921 
 922 #else /* CONFIG_DEBUG_FS */
 923 
 924 static inline void __init cxl_debugfs_init(void)
 925 {
 926 }
 927 
 928 static inline void cxl_debugfs_exit(void)
 929 {
 930 }
 931 
 932 static inline void cxl_debugfs_adapter_add(struct cxl *adapter)
 933 {
 934 }
 935 
 936 static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
 937 {
 938 }
 939 
 940 static inline void cxl_debugfs_afu_add(struct cxl_afu *afu)
 941 {
 942 }
 943 
 944 static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
 945 {
 946 }
 947 
 948 static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
 949                                                     struct dentry *dir)
 950 {
 951 }
 952 
 953 static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
 954                                                     struct dentry *dir)
 955 {
 956 }
 957 
 958 static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
 959 {
 960 }
 961 
 962 static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
 963 {
 964 }
 965 
 966 #endif /* CONFIG_DEBUG_FS */
 967 
 968 void cxl_handle_fault(struct work_struct *work);
 969 void cxl_prefault(struct cxl_context *ctx, u64 wed);
 970 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
 971 
 972 struct cxl *get_cxl_adapter(int num);
 973 int cxl_alloc_sst(struct cxl_context *ctx);
 974 void cxl_dump_debug_buffer(void *addr, size_t size);
 975 
 976 void init_cxl_native(void);
 977 
 978 struct cxl_context *cxl_context_alloc(void);
 979 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
 980 void cxl_context_set_mapping(struct cxl_context *ctx,
 981                         struct address_space *mapping);
 982 void cxl_context_free(struct cxl_context *ctx);
 983 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
 984 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
 985                          irq_handler_t handler, void *cookie, const char *name);
 986 void cxl_unmap_irq(unsigned int virq, void *cookie);
 987 int __detach_context(struct cxl_context *ctx);
 988 
 989 /*
 990  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
 991  * in PAPR.
 992  * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
 993  * On a guest environment, PSL_PID_An is located on the upper 32 bits and
 994  * PSL_TID_An register in the lower 32 bits.
 995  */
 996 struct cxl_irq_info {
 997         u64 dsisr;
 998         u64 dar;
 999         u64 dsr;
1000         u64 reserved;
1001         u64 afu_err;
1002         u64 errstat;
1003         u64 proc_handle;
1004         u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1005 };
1006 
1007 void cxl_assign_psn_space(struct cxl_context *ctx);
1008 int cxl_invalidate_all_psl9(struct cxl *adapter);
1009 int cxl_invalidate_all_psl8(struct cxl *adapter);
1010 irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1011 irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1012 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1013 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1014                         void *cookie, irq_hw_number_t *dest_hwirq,
1015                         unsigned int *dest_virq, const char *name);
1016 
1017 int cxl_check_error(struct cxl_afu *afu);
1018 int cxl_afu_slbia(struct cxl_afu *afu);
1019 int cxl_data_cache_flush(struct cxl *adapter);
1020 int cxl_afu_disable(struct cxl_afu *afu);
1021 int cxl_psl_purge(struct cxl_afu *afu);
1022 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1023                           u32 *phb_index, u64 *capp_unit_id);
1024 int cxl_slot_is_switched(struct pci_dev *dev);
1025 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
1026 u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1027 
1028 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1029 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1030 void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
1031 void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
1032 int cxl_pci_vphb_add(struct cxl_afu *afu);
1033 void cxl_pci_vphb_remove(struct cxl_afu *afu);
1034 void cxl_release_mapping(struct cxl_context *ctx);
1035 
1036 extern struct pci_driver cxl_pci_driver;
1037 extern struct platform_driver cxl_of_driver;
1038 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1039 
1040 int afu_open(struct inode *inode, struct file *file);
1041 int afu_release(struct inode *inode, struct file *file);
1042 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1043 int afu_mmap(struct file *file, struct vm_area_struct *vm);
1044 __poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
1045 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1046 extern const struct file_operations afu_fops;
1047 
1048 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1049 void cxl_guest_remove_adapter(struct cxl *adapter);
1050 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1051 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1052 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1053 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1054 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1055 void cxl_guest_remove_afu(struct cxl_afu *afu);
1056 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1057 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1058 int cxl_guest_add_chardev(struct cxl *adapter);
1059 void cxl_guest_remove_chardev(struct cxl *adapter);
1060 void cxl_guest_reload_module(struct cxl *adapter);
1061 int cxl_of_probe(struct platform_device *pdev);
1062 
1063 struct cxl_backend_ops {
1064         struct module *module;
1065         int (*adapter_reset)(struct cxl *adapter);
1066         int (*alloc_one_irq)(struct cxl *adapter);
1067         void (*release_one_irq)(struct cxl *adapter, int hwirq);
1068         int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1069                                 struct cxl *adapter, unsigned int num);
1070         void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1071                                 struct cxl *adapter);
1072         int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1073                         unsigned int virq);
1074         irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1075                                         u64 dsisr, u64 errstat);
1076         irqreturn_t (*psl_interrupt)(int irq, void *data);
1077         int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1078         void (*irq_wait)(struct cxl_context *ctx);
1079         int (*attach_process)(struct cxl_context *ctx, bool kernel,
1080                         u64 wed, u64 amr);
1081         int (*detach_process)(struct cxl_context *ctx);
1082         void (*update_ivtes)(struct cxl_context *ctx);
1083         bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1084         bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1085         void (*release_afu)(struct device *dev);
1086         ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1087                                 loff_t off, size_t count);
1088         int (*afu_check_and_enable)(struct cxl_afu *afu);
1089         int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1090         int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1091         int (*afu_reset)(struct cxl_afu *afu);
1092         int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1093         int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1094         int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1095         int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1096         int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1097         int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1098         int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1099         ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1100 };
1101 extern const struct cxl_backend_ops cxl_native_ops;
1102 extern const struct cxl_backend_ops cxl_guest_ops;
1103 extern const struct cxl_backend_ops *cxl_ops;
1104 
1105 /* check if the given pci_dev is on the the cxl vphb bus */
1106 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1107 
1108 /* decode AFU error bits in the PSL register PSL_SERR_An */
1109 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1110 
1111 /*
1112  * Increments the number of attached contexts on an adapter.
1113  * In case an adapter_context_lock is taken the return -EBUSY.
1114  */
1115 int cxl_adapter_context_get(struct cxl *adapter);
1116 
1117 /* Decrements the number of attached contexts on an adapter */
1118 void cxl_adapter_context_put(struct cxl *adapter);
1119 
1120 /* If no active contexts then prevents contexts from being attached */
1121 int cxl_adapter_context_lock(struct cxl *adapter);
1122 
1123 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1124 void cxl_adapter_context_unlock(struct cxl *adapter);
1125 
1126 /* Increases the reference count to "struct mm_struct" */
1127 void cxl_context_mm_count_get(struct cxl_context *ctx);
1128 
1129 /* Decrements the reference count to "struct mm_struct" */
1130 void cxl_context_mm_count_put(struct cxl_context *ctx);
1131 
1132 #endif
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