This source file includes following definitions.
- cirrus_bo
- cirrus_bo_reserve
- cirrus_bo_unreserve
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8 #ifndef __CIRRUS_DRV_H__
9 #define __CIRRUS_DRV_H__
10
11 #include <video/vga.h>
12
13 #include <drm/drm_encoder.h>
14 #include <drm/drm_fb_helper.h>
15
16 #include <drm/ttm/ttm_bo_api.h>
17 #include <drm/ttm/ttm_bo_driver.h>
18 #include <drm/ttm/ttm_placement.h>
19 #include <drm/ttm/ttm_memory.h>
20 #include <drm/ttm/ttm_module.h>
21
22 #include <drm/drm_gem.h>
23
24 #define DRIVER_AUTHOR "Matthew Garrett"
25
26 #define DRIVER_NAME "cirrus"
27 #define DRIVER_DESC "qemu Cirrus emulation"
28 #define DRIVER_DATE "20110418"
29
30 #define DRIVER_MAJOR 1
31 #define DRIVER_MINOR 0
32 #define DRIVER_PATCHLEVEL 0
33
34 #define CIRRUSFB_CONN_LIMIT 1
35
36 #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg))
37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg))
38 #define RREG32(reg) ioread32(((void __iomem *)cdev->rmmio) + (reg))
39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)cdev->rmmio) + (reg))
40
41 #define SEQ_INDEX 4
42 #define SEQ_DATA 5
43
44 #define WREG_SEQ(reg, v) \
45 do { \
46 WREG8(SEQ_INDEX, reg); \
47 WREG8(SEQ_DATA, v); \
48 } while (0) \
49
50 #define CRT_INDEX 0x14
51 #define CRT_DATA 0x15
52
53 #define WREG_CRT(reg, v) \
54 do { \
55 WREG8(CRT_INDEX, reg); \
56 WREG8(CRT_DATA, v); \
57 } while (0) \
58
59 #define GFX_INDEX 0xe
60 #define GFX_DATA 0xf
61
62 #define WREG_GFX(reg, v) \
63 do { \
64 WREG8(GFX_INDEX, reg); \
65 WREG8(GFX_DATA, v); \
66 } while (0) \
67
68
69
70
71
72
73 #define VGA_DAC_MASK 0x6
74
75 #define WREG_HDR(v) \
76 do { \
77 RREG8(VGA_DAC_MASK); \
78 RREG8(VGA_DAC_MASK); \
79 RREG8(VGA_DAC_MASK); \
80 RREG8(VGA_DAC_MASK); \
81 WREG8(VGA_DAC_MASK, v); \
82 } while (0) \
83
84
85 #define CIRRUS_MAX_FB_HEIGHT 4096
86 #define CIRRUS_MAX_FB_WIDTH 4096
87
88 #define CIRRUS_DPMS_CLEARED (-1)
89
90 #define to_cirrus_crtc(x) container_of(x, struct cirrus_crtc, base)
91 #define to_cirrus_encoder(x) container_of(x, struct cirrus_encoder, base)
92
93 struct cirrus_crtc {
94 struct drm_crtc base;
95 int last_dpms;
96 bool enabled;
97 };
98
99 struct cirrus_fbdev;
100 struct cirrus_mode_info {
101 struct cirrus_crtc *crtc;
102
103 struct cirrus_fbdev *gfbdev;
104 };
105
106 struct cirrus_encoder {
107 struct drm_encoder base;
108 int last_dpms;
109 };
110
111 struct cirrus_connector {
112 struct drm_connector base;
113 };
114
115 struct cirrus_mc {
116 resource_size_t vram_size;
117 resource_size_t vram_base;
118 };
119
120 struct cirrus_device {
121 struct drm_device *dev;
122 unsigned long flags;
123
124 resource_size_t rmmio_base;
125 resource_size_t rmmio_size;
126 void __iomem *rmmio;
127
128 struct cirrus_mc mc;
129 struct cirrus_mode_info mode_info;
130
131 int num_crtc;
132 int fb_mtrr;
133
134 struct {
135 struct ttm_bo_device bdev;
136 } ttm;
137 bool mm_inited;
138 };
139
140
141 struct cirrus_fbdev {
142 struct drm_fb_helper helper;
143 struct drm_framebuffer *gfb;
144 void *sysram;
145 int size;
146 int x1, y1, x2, y2;
147 spinlock_t dirty_lock;
148 };
149
150 struct cirrus_bo {
151 struct ttm_buffer_object bo;
152 struct ttm_placement placement;
153 struct ttm_bo_kmap_obj kmap;
154 struct drm_gem_object gem;
155 struct ttm_place placements[3];
156 int pin_count;
157 };
158 #define gem_to_cirrus_bo(gobj) container_of((gobj), struct cirrus_bo, gem)
159
160 static inline struct cirrus_bo *
161 cirrus_bo(struct ttm_buffer_object *bo)
162 {
163 return container_of(bo, struct cirrus_bo, bo);
164 }
165
166
167 #define to_cirrus_obj(x) container_of(x, struct cirrus_gem_object, base)
168
169
170 int cirrus_device_init(struct cirrus_device *cdev,
171 struct drm_device *ddev,
172 struct pci_dev *pdev,
173 uint32_t flags);
174 void cirrus_device_fini(struct cirrus_device *cdev);
175 void cirrus_gem_free_object(struct drm_gem_object *obj);
176 int cirrus_dumb_mmap_offset(struct drm_file *file,
177 struct drm_device *dev,
178 uint32_t handle,
179 uint64_t *offset);
180 int cirrus_gem_create(struct drm_device *dev,
181 u32 size, bool iskernel,
182 struct drm_gem_object **obj);
183 int cirrus_dumb_create(struct drm_file *file,
184 struct drm_device *dev,
185 struct drm_mode_create_dumb *args);
186
187 int cirrus_framebuffer_init(struct drm_device *dev,
188 struct drm_framebuffer *gfb,
189 const struct drm_mode_fb_cmd2 *mode_cmd,
190 struct drm_gem_object *obj);
191
192 bool cirrus_check_framebuffer(struct cirrus_device *cdev, int width, int height,
193 int bpp, int pitch);
194
195
196 int cirrus_modeset_init(struct cirrus_device *cdev);
197 void cirrus_modeset_fini(struct cirrus_device *cdev);
198
199
200 int cirrus_fbdev_init(struct cirrus_device *cdev);
201 void cirrus_fbdev_fini(struct cirrus_device *cdev);
202
203
204
205
206 void cirrus_driver_irq_preinstall(struct drm_device *dev);
207 int cirrus_driver_irq_postinstall(struct drm_device *dev);
208 void cirrus_driver_irq_uninstall(struct drm_device *dev);
209 irqreturn_t cirrus_driver_irq_handler(int irq, void *arg);
210
211
212 int cirrus_driver_load(struct drm_device *dev, unsigned long flags);
213 void cirrus_driver_unload(struct drm_device *dev);
214 extern struct drm_ioctl_desc cirrus_ioctls[];
215 extern int cirrus_max_ioctl;
216
217 int cirrus_mm_init(struct cirrus_device *cirrus);
218 void cirrus_mm_fini(struct cirrus_device *cirrus);
219 void cirrus_ttm_placement(struct cirrus_bo *bo, int domain);
220 int cirrus_bo_create(struct drm_device *dev, int size, int align,
221 uint32_t flags, struct cirrus_bo **pcirrusbo);
222 int cirrus_mmap(struct file *filp, struct vm_area_struct *vma);
223
224 static inline int cirrus_bo_reserve(struct cirrus_bo *bo, bool no_wait)
225 {
226 int ret;
227
228 ret = ttm_bo_reserve(&bo->bo, true, no_wait, NULL);
229 if (ret) {
230 if (ret != -ERESTARTSYS && ret != -EBUSY)
231 DRM_ERROR("reserve failed %p\n", bo);
232 return ret;
233 }
234 return 0;
235 }
236
237 static inline void cirrus_bo_unreserve(struct cirrus_bo *bo)
238 {
239 ttm_bo_unreserve(&bo->bo);
240 }
241
242 int cirrus_bo_push_sysram(struct cirrus_bo *bo);
243 int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr);
244
245 extern int cirrus_bpp;
246
247 #endif