root/drivers/gpu/drm/imx/ipuv3-plane.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __IPUV3_PLANE_H__
   3 #define __IPUV3_PLANE_H__
   4 
   5 #include <drm/drm_crtc.h> /* drm_plane */
   6 
   7 struct drm_plane;
   8 struct drm_device;
   9 struct ipu_soc;
  10 struct drm_crtc;
  11 struct drm_framebuffer;
  12 
  13 struct ipuv3_channel;
  14 struct dmfc_channel;
  15 struct ipu_dp;
  16 
  17 struct ipu_plane {
  18         struct drm_plane        base;
  19 
  20         struct ipu_soc          *ipu;
  21         struct ipuv3_channel    *ipu_ch;
  22         struct ipuv3_channel    *alpha_ch;
  23         struct dmfc_channel     *dmfc;
  24         struct ipu_dp           *dp;
  25 
  26         int                     dma;
  27         int                     dp_flow;
  28 
  29         bool                    disabling;
  30 };
  31 
  32 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
  33                                  int dma, int dp, unsigned int possible_crtcs,
  34                                  enum drm_plane_type type);
  35 
  36 /* Init IDMAC, DMFC, DP */
  37 int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
  38                        struct drm_display_mode *mode,
  39                        struct drm_framebuffer *fb, int crtc_x, int crtc_y,
  40                        unsigned int crtc_w, unsigned int crtc_h,
  41                        uint32_t src_x, uint32_t src_y, uint32_t src_w,
  42                        uint32_t src_h, bool interlaced);
  43 
  44 int ipu_plane_get_resources(struct ipu_plane *plane);
  45 void ipu_plane_put_resources(struct ipu_plane *plane);
  46 
  47 int ipu_plane_irq(struct ipu_plane *plane);
  48 
  49 void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel);
  50 void ipu_plane_disable_deferred(struct drm_plane *plane);
  51 bool ipu_plane_atomic_update_pending(struct drm_plane *plane);
  52 
  53 #endif