1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef _DPU_HW_CTL_H
6 #define _DPU_HW_CTL_H
7
8 #include "dpu_hw_mdss.h"
9 #include "dpu_hw_util.h"
10 #include "dpu_hw_catalog.h"
11 #include "dpu_hw_sspp.h"
12 #include "dpu_hw_blk.h"
13
14 /**
15 * dpu_ctl_mode_sel: Interface mode selection
16 * DPU_CTL_MODE_SEL_VID: Video mode interface
17 * DPU_CTL_MODE_SEL_CMD: Command mode interface
18 */
19 enum dpu_ctl_mode_sel {
20 DPU_CTL_MODE_SEL_VID = 0,
21 DPU_CTL_MODE_SEL_CMD
22 };
23
24 struct dpu_hw_ctl;
25 /**
26 * struct dpu_hw_stage_cfg - blending stage cfg
27 * @stage : SSPP_ID at each stage
28 * @multirect_index: index of the rectangle of SSPP.
29 */
30 struct dpu_hw_stage_cfg {
31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
32 enum dpu_sspp_multirect_index multirect_index
33 [DPU_STAGE_MAX][PIPES_PER_STAGE];
34 };
35
36 /**
37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
38 * @intf : Interface id
39 * @mode_3d: 3d mux configuration
40 * @intf_mode_sel: Interface mode, cmd / vid
41 * @stream_sel: Stream selection for multi-stream interfaces
42 */
43 struct dpu_hw_intf_cfg {
44 enum dpu_intf intf;
45 enum dpu_3d_blend_mode mode_3d;
46 enum dpu_ctl_mode_sel intf_mode_sel;
47 int stream_sel;
48 };
49
50 /**
51 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
52 * Assumption is these functions will be called after clocks are enabled
53 */
54 struct dpu_hw_ctl_ops {
55 /**
56 * kickoff hw operation for Sw controlled interfaces
57 * DSI cmd mode and WB interface are SW controlled
58 * @ctx : ctl path ctx pointer
59 */
60 void (*trigger_start)(struct dpu_hw_ctl *ctx);
61
62 /**
63 * kickoff prepare is in progress hw operation for sw
64 * controlled interfaces: DSI cmd mode and WB interface
65 * are SW controlled
66 * @ctx : ctl path ctx pointer
67 */
68 void (*trigger_pending)(struct dpu_hw_ctl *ctx);
69
70 /**
71 * Clear the value of the cached pending_flush_mask
72 * No effect on hardware
73 * @ctx : ctl path ctx pointer
74 */
75 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
76
77 /**
78 * Query the value of the cached pending_flush_mask
79 * No effect on hardware
80 * @ctx : ctl path ctx pointer
81 */
82 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
83
84 /**
85 * OR in the given flushbits to the cached pending_flush_mask
86 * No effect on hardware
87 * @ctx : ctl path ctx pointer
88 * @flushbits : module flushmask
89 */
90 void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
91 u32 flushbits);
92
93 /**
94 * Write the value of the pending_flush_mask to hardware
95 * @ctx : ctl path ctx pointer
96 */
97 void (*trigger_flush)(struct dpu_hw_ctl *ctx);
98
99 /**
100 * Read the value of the flush register
101 * @ctx : ctl path ctx pointer
102 * @Return: value of the ctl flush register.
103 */
104 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
105
106 /**
107 * Setup ctl_path interface config
108 * @ctx
109 * @cfg : interface config structure pointer
110 */
111 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
112 struct dpu_hw_intf_cfg *cfg);
113
114 int (*reset)(struct dpu_hw_ctl *c);
115
116 /*
117 * wait_reset_status - checks ctl reset status
118 * @ctx : ctl path ctx pointer
119 *
120 * This function checks the ctl reset status bit.
121 * If the reset bit is set, it keeps polling the status till the hw
122 * reset is complete.
123 * Returns: 0 on success or -error if reset incomplete within interval
124 */
125 int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
126
127 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx,
128 enum dpu_sspp blk);
129
130 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
131 enum dpu_lm blk);
132
133 int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx,
134 u32 *flushbits,
135 enum dpu_intf blk);
136
137 /**
138 * Set all blend stages to disabled
139 * @ctx : ctl path ctx pointer
140 */
141 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
142
143 /**
144 * Configure layer mixer to pipe configuration
145 * @ctx : ctl path ctx pointer
146 * @lm : layer mixer enumeration
147 * @cfg : blend stage configuration
148 */
149 void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
150 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
151 };
152
153 /**
154 * struct dpu_hw_ctl : CTL PATH driver object
155 * @base: hardware block base structure
156 * @hw: block register map object
157 * @idx: control path index
158 * @caps: control path capabilities
159 * @mixer_count: number of mixers
160 * @mixer_hw_caps: mixer hardware capabilities
161 * @pending_flush_mask: storage for pending ctl_flush managed via ops
162 * @ops: operation list
163 */
164 struct dpu_hw_ctl {
165 struct dpu_hw_blk base;
166 struct dpu_hw_blk_reg_map hw;
167
168 /* ctl path */
169 int idx;
170 const struct dpu_ctl_cfg *caps;
171 int mixer_count;
172 const struct dpu_lm_cfg *mixer_hw_caps;
173 u32 pending_flush_mask;
174
175 /* ops */
176 struct dpu_hw_ctl_ops ops;
177 };
178
179 /**
180 * dpu_hw_ctl - convert base object dpu_hw_base to container
181 * @hw: Pointer to base hardware block
182 * return: Pointer to hardware block container
183 */
184 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
185 {
186 return container_of(hw, struct dpu_hw_ctl, base);
187 }
188
189 /**
190 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object.
191 * should be called before accessing every ctl path registers.
192 * @idx: ctl_path index for which driver object is required
193 * @addr: mapped register io address of MDP
194 * @m : pointer to mdss catalog data
195 */
196 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
197 void __iomem *addr,
198 struct dpu_mdss_cfg *m);
199
200 /**
201 * dpu_hw_ctl_destroy(): Destroys ctl driver context
202 * should be called to free the context
203 */
204 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);
205
206 #endif /*_DPU_HW_CTL_H */