1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef _DPU_HW_INTERRUPTS_H
6 #define _DPU_HW_INTERRUPTS_H
7
8 #include <linux/types.h>
9
10 #include "dpu_hwio.h"
11 #include "dpu_hw_catalog.h"
12 #include "dpu_hw_util.h"
13 #include "dpu_hw_mdss.h"
14
15 /**
16 * dpu_intr_type - HW Interrupt Type
17 * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done
18 * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done
19 * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done
20 * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer
21 * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer
22 * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh
23 * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check
24 * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection
25 * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun
26 * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC
27 * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow
28 * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done
29 * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset
30 * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done
31 * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset
32 * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer
33 * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static
34 * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static
35 * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static
36 * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static
37 * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static
38 * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static
39 * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static
40 * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static
41 * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt
42 * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight
43 * @DPU_IRQ_TYPE_CTL_START: Control start
44 * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion
45 */
46 enum dpu_intr_type {
47 DPU_IRQ_TYPE_WB_ROT_COMP,
48 DPU_IRQ_TYPE_WB_WFD_COMP,
49 DPU_IRQ_TYPE_PING_PONG_COMP,
50 DPU_IRQ_TYPE_PING_PONG_RD_PTR,
51 DPU_IRQ_TYPE_PING_PONG_WR_PTR,
52 DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
53 DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
54 DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
55 DPU_IRQ_TYPE_INTF_UNDER_RUN,
56 DPU_IRQ_TYPE_INTF_VSYNC,
57 DPU_IRQ_TYPE_CWB_OVERFLOW,
58 DPU_IRQ_TYPE_HIST_VIG_DONE,
59 DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
60 DPU_IRQ_TYPE_HIST_DSPP_DONE,
61 DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
62 DPU_IRQ_TYPE_WD_TIMER,
63 DPU_IRQ_TYPE_SFI_VIDEO_IN,
64 DPU_IRQ_TYPE_SFI_VIDEO_OUT,
65 DPU_IRQ_TYPE_SFI_CMD_0_IN,
66 DPU_IRQ_TYPE_SFI_CMD_0_OUT,
67 DPU_IRQ_TYPE_SFI_CMD_1_IN,
68 DPU_IRQ_TYPE_SFI_CMD_1_OUT,
69 DPU_IRQ_TYPE_SFI_CMD_2_IN,
70 DPU_IRQ_TYPE_SFI_CMD_2_OUT,
71 DPU_IRQ_TYPE_PROG_LINE,
72 DPU_IRQ_TYPE_AD4_BL_DONE,
73 DPU_IRQ_TYPE_CTL_START,
74 DPU_IRQ_TYPE_RESERVED,
75 };
76
77 struct dpu_hw_intr;
78
79 /**
80 * Interrupt operations.
81 */
82 struct dpu_hw_intr_ops {
83 /**
84 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
85 * Used for all irq related ops
86 * @intr_type: Interrupt type defined in dpu_intr_type
87 * @instance_idx: HW interrupt block instance
88 * @return: irq_idx or -EINVAL for lookup fail
89 */
90 int (*irq_idx_lookup)(
91 enum dpu_intr_type intr_type,
92 u32 instance_idx);
93
94 /**
95 * enable_irq - Enable IRQ based on lookup IRQ index
96 * @intr: HW interrupt handle
97 * @irq_idx: Lookup irq index return from irq_idx_lookup
98 * @return: 0 for success, otherwise failure
99 */
100 int (*enable_irq)(
101 struct dpu_hw_intr *intr,
102 int irq_idx);
103
104 /**
105 * disable_irq - Disable IRQ based on lookup IRQ index
106 * @intr: HW interrupt handle
107 * @irq_idx: Lookup irq index return from irq_idx_lookup
108 * @return: 0 for success, otherwise failure
109 */
110 int (*disable_irq)(
111 struct dpu_hw_intr *intr,
112 int irq_idx);
113
114 /**
115 * clear_all_irqs - Clears all the interrupts (i.e. acknowledges
116 * any asserted IRQs). Useful during reset.
117 * @intr: HW interrupt handle
118 * @return: 0 for success, otherwise failure
119 */
120 int (*clear_all_irqs)(
121 struct dpu_hw_intr *intr);
122
123 /**
124 * disable_all_irqs - Disables all the interrupts. Useful during reset.
125 * @intr: HW interrupt handle
126 * @return: 0 for success, otherwise failure
127 */
128 int (*disable_all_irqs)(
129 struct dpu_hw_intr *intr);
130
131 /**
132 * dispatch_irqs - IRQ dispatcher will call the given callback
133 * function when a matching interrupt status bit is
134 * found in the irq mapping table.
135 * @intr: HW interrupt handle
136 * @cbfunc: Callback function pointer
137 * @arg: Argument to pass back during callback
138 */
139 void (*dispatch_irqs)(
140 struct dpu_hw_intr *intr,
141 void (*cbfunc)(void *arg, int irq_idx),
142 void *arg);
143
144 /**
145 * get_interrupt_statuses - Gets and store value from all interrupt
146 * status registers that are currently fired.
147 * @intr: HW interrupt handle
148 */
149 void (*get_interrupt_statuses)(
150 struct dpu_hw_intr *intr);
151
152 /**
153 * clear_intr_status_nolock() - clears the HW interrupts without lock
154 * @intr: HW interrupt handle
155 * @irq_idx: Lookup irq index return from irq_idx_lookup
156 */
157 void (*clear_intr_status_nolock)(
158 struct dpu_hw_intr *intr,
159 int irq_idx);
160
161 /**
162 * get_interrupt_status - Gets HW interrupt status, and clear if set,
163 * based on given lookup IRQ index.
164 * @intr: HW interrupt handle
165 * @irq_idx: Lookup irq index return from irq_idx_lookup
166 * @clear: True to clear irq after read
167 */
168 u32 (*get_interrupt_status)(
169 struct dpu_hw_intr *intr,
170 int irq_idx,
171 bool clear);
172 };
173
174 /**
175 * struct dpu_hw_intr: hw interrupts handling data structure
176 * @hw: virtual address mapping
177 * @ops: function pointer mapping for IRQ handling
178 * @cache_irq_mask: array of IRQ enable masks reg storage created during init
179 * @save_irq_status: array of IRQ status reg storage created during init
180 * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
181 * @irq_lock: spinlock for accessing IRQ resources
182 */
183 struct dpu_hw_intr {
184 struct dpu_hw_blk_reg_map hw;
185 struct dpu_hw_intr_ops ops;
186 u32 *cache_irq_mask;
187 u32 *save_irq_status;
188 u32 irq_idx_tbl_size;
189 spinlock_t irq_lock;
190 };
191
192 /**
193 * dpu_hw_intr_init(): Initializes the interrupts hw object
194 * @addr: mapped register io address of MDP
195 * @m : pointer to mdss catalog data
196 */
197 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
198 struct dpu_mdss_cfg *m);
199
200 /**
201 * dpu_hw_intr_destroy(): Cleanup interrutps hw object
202 * @intr: pointer to interrupts hw object
203 */
204 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
205 #endif