This source file includes following definitions.
- mdp5_hw_init
- mdp5_get_existing_global_state
- mdp5_get_global_state
- mdp5_global_duplicate_state
- mdp5_global_destroy_state
- mdp5_global_obj_init
- mdp5_enable_commit
- mdp5_disable_commit
- mdp5_prepare_commit
- mdp5_flush_commit
- mdp5_wait_flush
- mdp5_complete_commit
- mdp5_round_pixclk
- mdp5_set_split_display
- mdp5_set_encoder_mode
- mdp5_kms_destroy
- smp_show
- mdp5_kms_debugfs_init
- mdp5_disable
- mdp5_enable
- construct_encoder
- get_dsi_id_from_intf
- modeset_init_intf
- modeset_init
- read_mdp_hw_revision
- get_clk
- get_encoder_from_crtc
- mdp5_get_scanoutpos
- mdp5_get_vblank_counter
- mdp5_kms_init
- mdp5_destroy
- construct_pipes
- hwpipe_init
- hwmixer_init
- interface_init
- mdp5_init
- mdp5_bind
- mdp5_unbind
- mdp5_setup_interconnect
- mdp5_dev_probe
- mdp5_dev_remove
- mdp5_runtime_suspend
- mdp5_runtime_resume
- msm_mdp_register
- msm_mdp_unregister
1
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5
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7
8 #include <linux/delay.h>
9 #include <linux/interconnect.h>
10 #include <linux/of_irq.h>
11
12 #include <drm/drm_debugfs.h>
13 #include <drm/drm_drv.h>
14 #include <drm/drm_file.h>
15 #include <drm/drm_vblank.h>
16
17 #include "msm_drv.h"
18 #include "msm_gem.h"
19 #include "msm_mmu.h"
20 #include "mdp5_kms.h"
21
22 static const char *iommu_ports[] = {
23 "mdp_0",
24 };
25
26 static int mdp5_hw_init(struct msm_kms *kms)
27 {
28 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
29 struct device *dev = &mdp5_kms->pdev->dev;
30 unsigned long flags;
31
32 pm_runtime_get_sync(dev);
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
59 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
60 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
61
62 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
63
64 pm_runtime_put_sync(dev);
65
66 return 0;
67 }
68
69
70
71
72
73
74
75
76 struct mdp5_global_state *
77 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
78 {
79 return to_mdp5_global_state(mdp5_kms->glob_state.state);
80 }
81
82
83
84
85
86 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
87 {
88 struct msm_drm_private *priv = s->dev->dev_private;
89 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
90 struct drm_private_state *priv_state;
91 int ret;
92
93 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
94 if (ret)
95 return ERR_PTR(ret);
96
97 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
98 if (IS_ERR(priv_state))
99 return ERR_CAST(priv_state);
100
101 return to_mdp5_global_state(priv_state);
102 }
103
104 static struct drm_private_state *
105 mdp5_global_duplicate_state(struct drm_private_obj *obj)
106 {
107 struct mdp5_global_state *state;
108
109 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
110 if (!state)
111 return NULL;
112
113 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
114
115 return &state->base;
116 }
117
118 static void mdp5_global_destroy_state(struct drm_private_obj *obj,
119 struct drm_private_state *state)
120 {
121 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
122
123 kfree(mdp5_state);
124 }
125
126 static const struct drm_private_state_funcs mdp5_global_state_funcs = {
127 .atomic_duplicate_state = mdp5_global_duplicate_state,
128 .atomic_destroy_state = mdp5_global_destroy_state,
129 };
130
131 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
132 {
133 struct mdp5_global_state *state;
134
135 drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
136
137 state = kzalloc(sizeof(*state), GFP_KERNEL);
138 if (!state)
139 return -ENOMEM;
140
141 state->mdp5_kms = mdp5_kms;
142
143 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,
144 &state->base,
145 &mdp5_global_state_funcs);
146 return 0;
147 }
148
149 static void mdp5_enable_commit(struct msm_kms *kms)
150 {
151 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
152 pm_runtime_get_sync(&mdp5_kms->pdev->dev);
153 }
154
155 static void mdp5_disable_commit(struct msm_kms *kms)
156 {
157 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
158 pm_runtime_put_sync(&mdp5_kms->pdev->dev);
159 }
160
161 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
162 {
163 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
164 struct mdp5_global_state *global_state;
165
166 global_state = mdp5_get_existing_global_state(mdp5_kms);
167
168 if (mdp5_kms->smp)
169 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);
170 }
171
172 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
173 {
174
175 }
176
177 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
178 {
179 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
180 struct drm_crtc *crtc;
181
182 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)
183 mdp5_crtc_wait_for_commit_done(crtc);
184 }
185
186 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
187 {
188 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
189 struct mdp5_global_state *global_state;
190
191 global_state = mdp5_get_existing_global_state(mdp5_kms);
192
193 if (mdp5_kms->smp)
194 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
195 }
196
197 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
198 struct drm_encoder *encoder)
199 {
200 return rate;
201 }
202
203 static int mdp5_set_split_display(struct msm_kms *kms,
204 struct drm_encoder *encoder,
205 struct drm_encoder *slave_encoder,
206 bool is_cmd_mode)
207 {
208 if (is_cmd_mode)
209 return mdp5_cmd_encoder_set_split_display(encoder,
210 slave_encoder);
211 else
212 return mdp5_vid_encoder_set_split_display(encoder,
213 slave_encoder);
214 }
215
216 static void mdp5_set_encoder_mode(struct msm_kms *kms,
217 struct drm_encoder *encoder,
218 bool cmd_mode)
219 {
220 mdp5_encoder_set_intf_mode(encoder, cmd_mode);
221 }
222
223 static void mdp5_kms_destroy(struct msm_kms *kms)
224 {
225 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
226 struct msm_gem_address_space *aspace = kms->aspace;
227 int i;
228
229 for (i = 0; i < mdp5_kms->num_hwmixers; i++)
230 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
231
232 for (i = 0; i < mdp5_kms->num_hwpipes; i++)
233 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
234
235 if (aspace) {
236 aspace->mmu->funcs->detach(aspace->mmu,
237 iommu_ports, ARRAY_SIZE(iommu_ports));
238 msm_gem_address_space_put(aspace);
239 }
240 }
241
242 #ifdef CONFIG_DEBUG_FS
243 static int smp_show(struct seq_file *m, void *arg)
244 {
245 struct drm_info_node *node = (struct drm_info_node *) m->private;
246 struct drm_device *dev = node->minor->dev;
247 struct msm_drm_private *priv = dev->dev_private;
248 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
249 struct drm_printer p = drm_seq_file_printer(m);
250
251 if (!mdp5_kms->smp) {
252 drm_printf(&p, "no SMP pool\n");
253 return 0;
254 }
255
256 mdp5_smp_dump(mdp5_kms->smp, &p);
257
258 return 0;
259 }
260
261 static struct drm_info_list mdp5_debugfs_list[] = {
262 {"smp", smp_show },
263 };
264
265 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
266 {
267 struct drm_device *dev = minor->dev;
268 int ret;
269
270 ret = drm_debugfs_create_files(mdp5_debugfs_list,
271 ARRAY_SIZE(mdp5_debugfs_list),
272 minor->debugfs_root, minor);
273
274 if (ret) {
275 DRM_DEV_ERROR(dev->dev, "could not install mdp5_debugfs_list\n");
276 return ret;
277 }
278
279 return 0;
280 }
281 #endif
282
283 static const struct mdp_kms_funcs kms_funcs = {
284 .base = {
285 .hw_init = mdp5_hw_init,
286 .irq_preinstall = mdp5_irq_preinstall,
287 .irq_postinstall = mdp5_irq_postinstall,
288 .irq_uninstall = mdp5_irq_uninstall,
289 .irq = mdp5_irq,
290 .enable_vblank = mdp5_enable_vblank,
291 .disable_vblank = mdp5_disable_vblank,
292 .flush_commit = mdp5_flush_commit,
293 .enable_commit = mdp5_enable_commit,
294 .disable_commit = mdp5_disable_commit,
295 .prepare_commit = mdp5_prepare_commit,
296 .wait_flush = mdp5_wait_flush,
297 .complete_commit = mdp5_complete_commit,
298 .get_format = mdp_get_format,
299 .round_pixclk = mdp5_round_pixclk,
300 .set_split_display = mdp5_set_split_display,
301 .set_encoder_mode = mdp5_set_encoder_mode,
302 .destroy = mdp5_kms_destroy,
303 #ifdef CONFIG_DEBUG_FS
304 .debugfs_init = mdp5_kms_debugfs_init,
305 #endif
306 },
307 .set_irqmask = mdp5_set_irqmask,
308 };
309
310 int mdp5_disable(struct mdp5_kms *mdp5_kms)
311 {
312 DBG("");
313
314 mdp5_kms->enable_count--;
315 WARN_ON(mdp5_kms->enable_count < 0);
316
317 clk_disable_unprepare(mdp5_kms->ahb_clk);
318 clk_disable_unprepare(mdp5_kms->axi_clk);
319 clk_disable_unprepare(mdp5_kms->core_clk);
320 if (mdp5_kms->lut_clk)
321 clk_disable_unprepare(mdp5_kms->lut_clk);
322
323 return 0;
324 }
325
326 int mdp5_enable(struct mdp5_kms *mdp5_kms)
327 {
328 DBG("");
329
330 mdp5_kms->enable_count++;
331
332 clk_prepare_enable(mdp5_kms->ahb_clk);
333 clk_prepare_enable(mdp5_kms->axi_clk);
334 clk_prepare_enable(mdp5_kms->core_clk);
335 if (mdp5_kms->lut_clk)
336 clk_prepare_enable(mdp5_kms->lut_clk);
337
338 return 0;
339 }
340
341 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
342 struct mdp5_interface *intf,
343 struct mdp5_ctl *ctl)
344 {
345 struct drm_device *dev = mdp5_kms->dev;
346 struct msm_drm_private *priv = dev->dev_private;
347 struct drm_encoder *encoder;
348
349 encoder = mdp5_encoder_init(dev, intf, ctl);
350 if (IS_ERR(encoder)) {
351 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");
352 return encoder;
353 }
354
355 priv->encoders[priv->num_encoders++] = encoder;
356
357 return encoder;
358 }
359
360 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
361 {
362 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
363 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
364 int id = 0, i;
365
366 for (i = 0; i < intf_cnt; i++) {
367 if (intfs[i] == INTF_DSI) {
368 if (intf_num == i)
369 return id;
370
371 id++;
372 }
373 }
374
375 return -EINVAL;
376 }
377
378 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
379 struct mdp5_interface *intf)
380 {
381 struct drm_device *dev = mdp5_kms->dev;
382 struct msm_drm_private *priv = dev->dev_private;
383 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
384 struct mdp5_ctl *ctl;
385 struct drm_encoder *encoder;
386 int ret = 0;
387
388 switch (intf->type) {
389 case INTF_eDP:
390 if (!priv->edp)
391 break;
392
393 ctl = mdp5_ctlm_request(ctlm, intf->num);
394 if (!ctl) {
395 ret = -EINVAL;
396 break;
397 }
398
399 encoder = construct_encoder(mdp5_kms, intf, ctl);
400 if (IS_ERR(encoder)) {
401 ret = PTR_ERR(encoder);
402 break;
403 }
404
405 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
406 break;
407 case INTF_HDMI:
408 if (!priv->hdmi)
409 break;
410
411 ctl = mdp5_ctlm_request(ctlm, intf->num);
412 if (!ctl) {
413 ret = -EINVAL;
414 break;
415 }
416
417 encoder = construct_encoder(mdp5_kms, intf, ctl);
418 if (IS_ERR(encoder)) {
419 ret = PTR_ERR(encoder);
420 break;
421 }
422
423 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
424 break;
425 case INTF_DSI:
426 {
427 const struct mdp5_cfg_hw *hw_cfg =
428 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
429 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
430
431 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
432 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",
433 intf->num);
434 ret = -EINVAL;
435 break;
436 }
437
438 if (!priv->dsi[dsi_id])
439 break;
440
441 ctl = mdp5_ctlm_request(ctlm, intf->num);
442 if (!ctl) {
443 ret = -EINVAL;
444 break;
445 }
446
447 encoder = construct_encoder(mdp5_kms, intf, ctl);
448 if (IS_ERR(encoder)) {
449 ret = PTR_ERR(encoder);
450 break;
451 }
452
453 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
454 break;
455 }
456 default:
457 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);
458 ret = -EINVAL;
459 break;
460 }
461
462 return ret;
463 }
464
465 static int modeset_init(struct mdp5_kms *mdp5_kms)
466 {
467 struct drm_device *dev = mdp5_kms->dev;
468 struct msm_drm_private *priv = dev->dev_private;
469 const struct mdp5_cfg_hw *hw_cfg;
470 unsigned int num_crtcs;
471 int i, ret, pi = 0, ci = 0;
472 struct drm_plane *primary[MAX_BASES] = { NULL };
473 struct drm_plane *cursor[MAX_BASES] = { NULL };
474
475 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
476
477
478
479
480
481 for (i = 0; i < mdp5_kms->num_intfs; i++) {
482 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
483 if (ret)
484 goto fail;
485 }
486
487
488
489
490
491
492 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers);
493
494
495
496
497
498
499 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
500 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
501 struct drm_plane *plane;
502 enum drm_plane_type type;
503
504 if (i < num_crtcs)
505 type = DRM_PLANE_TYPE_PRIMARY;
506 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
507 type = DRM_PLANE_TYPE_CURSOR;
508 else
509 type = DRM_PLANE_TYPE_OVERLAY;
510
511 plane = mdp5_plane_init(dev, type);
512 if (IS_ERR(plane)) {
513 ret = PTR_ERR(plane);
514 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
515 goto fail;
516 }
517 priv->planes[priv->num_planes++] = plane;
518
519 if (type == DRM_PLANE_TYPE_PRIMARY)
520 primary[pi++] = plane;
521 if (type == DRM_PLANE_TYPE_CURSOR)
522 cursor[ci++] = plane;
523 }
524
525 for (i = 0; i < num_crtcs; i++) {
526 struct drm_crtc *crtc;
527
528 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i);
529 if (IS_ERR(crtc)) {
530 ret = PTR_ERR(crtc);
531 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
532 goto fail;
533 }
534 priv->crtcs[priv->num_crtcs++] = crtc;
535 }
536
537
538
539
540
541 for (i = 0; i < priv->num_encoders; i++) {
542 struct drm_encoder *encoder = priv->encoders[i];
543
544 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
545 }
546
547 return 0;
548
549 fail:
550 return ret;
551 }
552
553 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
554 u32 *major, u32 *minor)
555 {
556 struct device *dev = &mdp5_kms->pdev->dev;
557 u32 version;
558
559 pm_runtime_get_sync(dev);
560 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
561 pm_runtime_put_sync(dev);
562
563 *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
564 *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
565
566 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor);
567 }
568
569 static int get_clk(struct platform_device *pdev, struct clk **clkp,
570 const char *name, bool mandatory)
571 {
572 struct device *dev = &pdev->dev;
573 struct clk *clk = msm_clk_get(pdev, name);
574 if (IS_ERR(clk) && mandatory) {
575 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
576 return PTR_ERR(clk);
577 }
578 if (IS_ERR(clk))
579 DBG("skipping %s", name);
580 else
581 *clkp = clk;
582
583 return 0;
584 }
585
586 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
587 {
588 struct drm_device *dev = crtc->dev;
589 struct drm_encoder *encoder;
590
591 drm_for_each_encoder(encoder, dev)
592 if (encoder->crtc == crtc)
593 return encoder;
594
595 return NULL;
596 }
597
598 static bool mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe,
599 bool in_vblank_irq, int *vpos, int *hpos,
600 ktime_t *stime, ktime_t *etime,
601 const struct drm_display_mode *mode)
602 {
603 struct msm_drm_private *priv = dev->dev_private;
604 struct drm_crtc *crtc;
605 struct drm_encoder *encoder;
606 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
607
608 crtc = priv->crtcs[pipe];
609 if (!crtc) {
610 DRM_ERROR("Invalid crtc %d\n", pipe);
611 return false;
612 }
613
614 encoder = get_encoder_from_crtc(crtc);
615 if (!encoder) {
616 DRM_ERROR("no encoder found for crtc %d\n", pipe);
617 return false;
618 }
619
620 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
621 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
622
623
624
625
626
627
628
629 vactive_start = vsw + vbp + 1;
630
631 vactive_end = vactive_start + mode->crtc_vdisplay;
632
633
634 vfp_end = mode->crtc_vtotal;
635
636 if (stime)
637 *stime = ktime_get();
638
639 line = mdp5_encoder_get_linecount(encoder);
640
641 if (line < vactive_start) {
642 line -= vactive_start;
643 } else if (line > vactive_end) {
644 line = line - vfp_end - vactive_start;
645 } else {
646 line -= vactive_start;
647 }
648
649 *vpos = line;
650 *hpos = 0;
651
652 if (etime)
653 *etime = ktime_get();
654
655 return true;
656 }
657
658 static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
659 {
660 struct msm_drm_private *priv = dev->dev_private;
661 struct drm_crtc *crtc;
662 struct drm_encoder *encoder;
663
664 if (pipe >= priv->num_crtcs)
665 return 0;
666
667 crtc = priv->crtcs[pipe];
668 if (!crtc)
669 return 0;
670
671 encoder = get_encoder_from_crtc(crtc);
672 if (!encoder)
673 return 0;
674
675 return mdp5_encoder_get_framecount(encoder);
676 }
677
678 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
679 {
680 struct msm_drm_private *priv = dev->dev_private;
681 struct platform_device *pdev;
682 struct mdp5_kms *mdp5_kms;
683 struct mdp5_cfg *config;
684 struct msm_kms *kms;
685 struct msm_gem_address_space *aspace;
686 int irq, i, ret;
687 struct device *iommu_dev;
688
689
690 kms = priv->kms;
691 if (!kms)
692 return NULL;
693
694 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
695
696 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
697
698 pdev = mdp5_kms->pdev;
699
700 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
701 if (irq < 0) {
702 ret = irq;
703 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret);
704 goto fail;
705 }
706
707 kms->irq = irq;
708
709 config = mdp5_cfg_get_config(mdp5_kms->cfg);
710
711
712
713
714
715 pm_runtime_get_sync(&pdev->dev);
716 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
717 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
718 !config->hw->intf.base[i])
719 continue;
720 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
721
722 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
723 }
724 mdelay(16);
725
726 if (config->platform.iommu) {
727 iommu_dev = &pdev->dev;
728 if (!iommu_dev->iommu_fwspec)
729 iommu_dev = iommu_dev->parent;
730
731 aspace = msm_gem_address_space_create(iommu_dev,
732 config->platform.iommu, "mdp5");
733 if (IS_ERR(aspace)) {
734 ret = PTR_ERR(aspace);
735 goto fail;
736 }
737
738 kms->aspace = aspace;
739
740 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
741 ARRAY_SIZE(iommu_ports));
742 if (ret) {
743 DRM_DEV_ERROR(&pdev->dev, "failed to attach iommu: %d\n",
744 ret);
745 goto fail;
746 }
747 } else {
748 DRM_DEV_INFO(&pdev->dev,
749 "no iommu, fallback to phys contig buffers for scanout\n");
750 aspace = NULL;
751 }
752
753 pm_runtime_put_sync(&pdev->dev);
754
755 ret = modeset_init(mdp5_kms);
756 if (ret) {
757 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);
758 goto fail;
759 }
760
761 dev->mode_config.min_width = 0;
762 dev->mode_config.min_height = 0;
763 dev->mode_config.max_width = 0xffff;
764 dev->mode_config.max_height = 0xffff;
765
766 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
767 dev->driver->get_scanout_position = mdp5_get_scanoutpos;
768 dev->driver->get_vblank_counter = mdp5_get_vblank_counter;
769 dev->max_vblank_count = 0;
770 dev->vblank_disable_immediate = true;
771
772 return kms;
773 fail:
774 if (kms)
775 mdp5_kms_destroy(kms);
776 return ERR_PTR(ret);
777 }
778
779 static void mdp5_destroy(struct platform_device *pdev)
780 {
781 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
782 int i;
783
784 if (mdp5_kms->ctlm)
785 mdp5_ctlm_destroy(mdp5_kms->ctlm);
786 if (mdp5_kms->smp)
787 mdp5_smp_destroy(mdp5_kms->smp);
788 if (mdp5_kms->cfg)
789 mdp5_cfg_destroy(mdp5_kms->cfg);
790
791 for (i = 0; i < mdp5_kms->num_intfs; i++)
792 kfree(mdp5_kms->intfs[i]);
793
794 if (mdp5_kms->rpm_enabled)
795 pm_runtime_disable(&pdev->dev);
796
797 drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
798 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
799 }
800
801 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
802 const enum mdp5_pipe *pipes, const uint32_t *offsets,
803 uint32_t caps)
804 {
805 struct drm_device *dev = mdp5_kms->dev;
806 int i, ret;
807
808 for (i = 0; i < cnt; i++) {
809 struct mdp5_hw_pipe *hwpipe;
810
811 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
812 if (IS_ERR(hwpipe)) {
813 ret = PTR_ERR(hwpipe);
814 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",
815 pipe2name(pipes[i]), ret);
816 return ret;
817 }
818 hwpipe->idx = mdp5_kms->num_hwpipes;
819 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
820 }
821
822 return 0;
823 }
824
825 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
826 {
827 static const enum mdp5_pipe rgb_planes[] = {
828 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
829 };
830 static const enum mdp5_pipe vig_planes[] = {
831 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
832 };
833 static const enum mdp5_pipe dma_planes[] = {
834 SSPP_DMA0, SSPP_DMA1,
835 };
836 static const enum mdp5_pipe cursor_planes[] = {
837 SSPP_CURSOR0, SSPP_CURSOR1,
838 };
839 const struct mdp5_cfg_hw *hw_cfg;
840 int ret;
841
842 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
843
844
845 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
846 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
847 if (ret)
848 return ret;
849
850
851 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
852 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
853 if (ret)
854 return ret;
855
856
857 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
858 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
859 if (ret)
860 return ret;
861
862
863 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
864 cursor_planes, hw_cfg->pipe_cursor.base,
865 hw_cfg->pipe_cursor.caps);
866 if (ret)
867 return ret;
868
869 return 0;
870 }
871
872 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
873 {
874 struct drm_device *dev = mdp5_kms->dev;
875 const struct mdp5_cfg_hw *hw_cfg;
876 int i, ret;
877
878 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
879
880 for (i = 0; i < hw_cfg->lm.count; i++) {
881 struct mdp5_hw_mixer *mixer;
882
883 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
884 if (IS_ERR(mixer)) {
885 ret = PTR_ERR(mixer);
886 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",
887 i, ret);
888 return ret;
889 }
890
891 mixer->idx = mdp5_kms->num_hwmixers;
892 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
893 }
894
895 return 0;
896 }
897
898 static int interface_init(struct mdp5_kms *mdp5_kms)
899 {
900 struct drm_device *dev = mdp5_kms->dev;
901 const struct mdp5_cfg_hw *hw_cfg;
902 const enum mdp5_intf_type *intf_types;
903 int i;
904
905 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
906 intf_types = hw_cfg->intf.connect;
907
908 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
909 struct mdp5_interface *intf;
910
911 if (intf_types[i] == INTF_DISABLED)
912 continue;
913
914 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
915 if (!intf) {
916 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);
917 return -ENOMEM;
918 }
919
920 intf->num = i;
921 intf->type = intf_types[i];
922 intf->mode = MDP5_INTF_MODE_NONE;
923 intf->idx = mdp5_kms->num_intfs;
924 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
925 }
926
927 return 0;
928 }
929
930 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
931 {
932 struct msm_drm_private *priv = dev->dev_private;
933 struct mdp5_kms *mdp5_kms;
934 struct mdp5_cfg *config;
935 u32 major, minor;
936 int ret;
937
938 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
939 if (!mdp5_kms) {
940 ret = -ENOMEM;
941 goto fail;
942 }
943
944 platform_set_drvdata(pdev, mdp5_kms);
945
946 spin_lock_init(&mdp5_kms->resource_lock);
947
948 mdp5_kms->dev = dev;
949 mdp5_kms->pdev = pdev;
950
951 ret = mdp5_global_obj_init(mdp5_kms);
952 if (ret)
953 goto fail;
954
955 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
956 if (IS_ERR(mdp5_kms->mmio)) {
957 ret = PTR_ERR(mdp5_kms->mmio);
958 goto fail;
959 }
960
961
962 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
963 if (ret)
964 goto fail;
965 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
966 if (ret)
967 goto fail;
968 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
969 if (ret)
970 goto fail;
971 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
972 if (ret)
973 goto fail;
974
975
976 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
977
978
979
980
981
982 clk_set_rate(mdp5_kms->core_clk, 200000000);
983
984 pm_runtime_enable(&pdev->dev);
985 mdp5_kms->rpm_enabled = true;
986
987 read_mdp_hw_revision(mdp5_kms, &major, &minor);
988
989 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
990 if (IS_ERR(mdp5_kms->cfg)) {
991 ret = PTR_ERR(mdp5_kms->cfg);
992 mdp5_kms->cfg = NULL;
993 goto fail;
994 }
995
996 config = mdp5_cfg_get_config(mdp5_kms->cfg);
997 mdp5_kms->caps = config->hw->mdp.caps;
998
999
1000 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
1001
1002
1003
1004
1005
1006
1007 if (mdp5_kms->caps & MDP_CAP_SMP) {
1008 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
1009 if (IS_ERR(mdp5_kms->smp)) {
1010 ret = PTR_ERR(mdp5_kms->smp);
1011 mdp5_kms->smp = NULL;
1012 goto fail;
1013 }
1014 }
1015
1016 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
1017 if (IS_ERR(mdp5_kms->ctlm)) {
1018 ret = PTR_ERR(mdp5_kms->ctlm);
1019 mdp5_kms->ctlm = NULL;
1020 goto fail;
1021 }
1022
1023 ret = hwpipe_init(mdp5_kms);
1024 if (ret)
1025 goto fail;
1026
1027 ret = hwmixer_init(mdp5_kms);
1028 if (ret)
1029 goto fail;
1030
1031 ret = interface_init(mdp5_kms);
1032 if (ret)
1033 goto fail;
1034
1035
1036 priv->kms = &mdp5_kms->base.base;
1037
1038 return 0;
1039 fail:
1040 mdp5_destroy(pdev);
1041 return ret;
1042 }
1043
1044 static int mdp5_bind(struct device *dev, struct device *master, void *data)
1045 {
1046 struct drm_device *ddev = dev_get_drvdata(master);
1047 struct platform_device *pdev = to_platform_device(dev);
1048
1049 DBG("");
1050
1051 return mdp5_init(pdev, ddev);
1052 }
1053
1054 static void mdp5_unbind(struct device *dev, struct device *master,
1055 void *data)
1056 {
1057 struct platform_device *pdev = to_platform_device(dev);
1058
1059 mdp5_destroy(pdev);
1060 }
1061
1062 static const struct component_ops mdp5_ops = {
1063 .bind = mdp5_bind,
1064 .unbind = mdp5_unbind,
1065 };
1066
1067 static int mdp5_setup_interconnect(struct platform_device *pdev)
1068 {
1069 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem");
1070 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem");
1071 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem");
1072
1073 if (IS_ERR(path0))
1074 return PTR_ERR(path0);
1075
1076 if (!path0) {
1077
1078
1079
1080
1081
1082
1083 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
1084 return 0;
1085 }
1086
1087 icc_set_bw(path0, 0, MBps_to_icc(6400));
1088
1089 if (!IS_ERR_OR_NULL(path1))
1090 icc_set_bw(path1, 0, MBps_to_icc(6400));
1091 if (!IS_ERR_OR_NULL(path_rot))
1092 icc_set_bw(path_rot, 0, MBps_to_icc(6400));
1093
1094 return 0;
1095 }
1096
1097 static int mdp5_dev_probe(struct platform_device *pdev)
1098 {
1099 int ret;
1100
1101 DBG("");
1102
1103 ret = mdp5_setup_interconnect(pdev);
1104 if (ret)
1105 return ret;
1106
1107 return component_add(&pdev->dev, &mdp5_ops);
1108 }
1109
1110 static int mdp5_dev_remove(struct platform_device *pdev)
1111 {
1112 DBG("");
1113 component_del(&pdev->dev, &mdp5_ops);
1114 return 0;
1115 }
1116
1117 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
1118 {
1119 struct platform_device *pdev = to_platform_device(dev);
1120 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1121
1122 DBG("");
1123
1124 return mdp5_disable(mdp5_kms);
1125 }
1126
1127 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
1128 {
1129 struct platform_device *pdev = to_platform_device(dev);
1130 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1131
1132 DBG("");
1133
1134 return mdp5_enable(mdp5_kms);
1135 }
1136
1137 static const struct dev_pm_ops mdp5_pm_ops = {
1138 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
1139 };
1140
1141 static const struct of_device_id mdp5_dt_match[] = {
1142 { .compatible = "qcom,mdp5", },
1143
1144 { .compatible = "qcom,mdss_mdp", },
1145 {}
1146 };
1147 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
1148
1149 static struct platform_driver mdp5_driver = {
1150 .probe = mdp5_dev_probe,
1151 .remove = mdp5_dev_remove,
1152 .driver = {
1153 .name = "msm_mdp",
1154 .of_match_table = mdp5_dt_match,
1155 .pm = &mdp5_pm_ops,
1156 },
1157 };
1158
1159 void __init msm_mdp_register(void)
1160 {
1161 DBG("");
1162 platform_driver_register(&mdp5_driver);
1163 }
1164
1165 void __exit msm_mdp_unregister(void)
1166 {
1167 DBG("");
1168 platform_driver_unregister(&mdp5_driver);
1169 }