root/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h

INCLUDED FROM

DEFINITIONS

1. MDSS_HW_VERSION_STEP
2. MDSS_HW_VERSION_MINOR
3. MDSS_HW_VERSION_MAJOR
4. MDP5_HW_VERSION_STEP
5. MDP5_HW_VERSION_MINOR
6. MDP5_HW_VERSION_MAJOR
7. MDP5_DISP_INTF_SEL_INTF0
8. MDP5_DISP_INTF_SEL_INTF1
9. MDP5_DISP_INTF_SEL_INTF2
10. MDP5_DISP_INTF_SEL_INTF3
11. REG_MDP5_SMP_ALLOC_W
12. REG_MDP5_SMP_ALLOC_W_REG
13. MDP5_SMP_ALLOC_W_REG_CLIENT0
14. MDP5_SMP_ALLOC_W_REG_CLIENT1
15. MDP5_SMP_ALLOC_W_REG_CLIENT2
16. REG_MDP5_SMP_ALLOC_R
17. REG_MDP5_SMP_ALLOC_R_REG
18. MDP5_SMP_ALLOC_R_REG_CLIENT0
19. MDP5_SMP_ALLOC_R_REG_CLIENT1
20. MDP5_SMP_ALLOC_R_REG_CLIENT2
21. __offset_IGC
22. REG_MDP5_IGC
23. REG_MDP5_IGC_LUT
24. REG_MDP5_IGC_LUT_REG
25. MDP5_IGC_LUT_REG_VAL
26. __offset_CTL
27. REG_MDP5_CTL
28. __offset_LAYER
29. REG_MDP5_CTL_LAYER
30. REG_MDP5_CTL_LAYER_REG
31. MDP5_CTL_LAYER_REG_VIG0
32. MDP5_CTL_LAYER_REG_VIG1
33. MDP5_CTL_LAYER_REG_VIG2
34. MDP5_CTL_LAYER_REG_RGB0
35. MDP5_CTL_LAYER_REG_RGB1
36. MDP5_CTL_LAYER_REG_RGB2
37. MDP5_CTL_LAYER_REG_DMA0
38. MDP5_CTL_LAYER_REG_DMA1
39. MDP5_CTL_LAYER_REG_VIG3
40. MDP5_CTL_LAYER_REG_RGB3
41. REG_MDP5_CTL_OP
42. MDP5_CTL_OP_MODE
43. MDP5_CTL_OP_INTF_NUM
44. MDP5_CTL_OP_PACK_3D
45. REG_MDP5_CTL_FLUSH
46. REG_MDP5_CTL_START
47. REG_MDP5_CTL_PACK_3D
48. __offset_LAYER_EXT
49. REG_MDP5_CTL_LAYER_EXT
50. REG_MDP5_CTL_LAYER_EXT_REG
51. MDP5_CTL_LAYER_EXT_REG_CURSOR0
52. MDP5_CTL_LAYER_EXT_REG_CURSOR1
53. __offset_PIPE
54. REG_MDP5_PIPE
55. REG_MDP5_PIPE_OP_MODE
56. MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT
57. MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT
58. REG_MDP5_PIPE_HIST_CTL_BASE
59. REG_MDP5_PIPE_HIST_LUT_BASE
60. REG_MDP5_PIPE_HIST_LUT_SWAP
61. REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0
62. MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11
63. MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12
64. REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1
65. MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13
66. MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21
67. REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2
68. MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22
69. MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23
70. REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3
71. MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31
72. MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32
73. REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4
74. MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33
75. REG_MDP5_PIPE_CSC_1_PRE_CLAMP
76. REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG
77. MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH
78. MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW
79. REG_MDP5_PIPE_CSC_1_POST_CLAMP
80. REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG
81. MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH
82. MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW
83. REG_MDP5_PIPE_CSC_1_PRE_BIAS
84. REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG
85. MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE
86. REG_MDP5_PIPE_CSC_1_POST_BIAS
87. REG_MDP5_PIPE_CSC_1_POST_BIAS_REG
88. MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE
89. REG_MDP5_PIPE_SRC_SIZE
90. MDP5_PIPE_SRC_SIZE_HEIGHT
91. MDP5_PIPE_SRC_SIZE_WIDTH
92. REG_MDP5_PIPE_SRC_IMG_SIZE
93. MDP5_PIPE_SRC_IMG_SIZE_HEIGHT
94. MDP5_PIPE_SRC_IMG_SIZE_WIDTH
95. REG_MDP5_PIPE_SRC_XY
96. MDP5_PIPE_SRC_XY_Y
97. MDP5_PIPE_SRC_XY_X
98. REG_MDP5_PIPE_OUT_SIZE
99. MDP5_PIPE_OUT_SIZE_HEIGHT
100. MDP5_PIPE_OUT_SIZE_WIDTH
101. REG_MDP5_PIPE_OUT_XY
102. MDP5_PIPE_OUT_XY_Y
103. MDP5_PIPE_OUT_XY_X
104. REG_MDP5_PIPE_SRC0_ADDR
105. REG_MDP5_PIPE_SRC1_ADDR
106. REG_MDP5_PIPE_SRC2_ADDR
107. REG_MDP5_PIPE_SRC3_ADDR
108. REG_MDP5_PIPE_SRC_STRIDE_A
109. MDP5_PIPE_SRC_STRIDE_A_P0
110. MDP5_PIPE_SRC_STRIDE_A_P1
111. REG_MDP5_PIPE_SRC_STRIDE_B
112. MDP5_PIPE_SRC_STRIDE_B_P2
113. MDP5_PIPE_SRC_STRIDE_B_P3
114. REG_MDP5_PIPE_STILE_FRAME_SIZE
115. REG_MDP5_PIPE_SRC_FORMAT
116. MDP5_PIPE_SRC_FORMAT_G_BPC
117. MDP5_PIPE_SRC_FORMAT_B_BPC
118. MDP5_PIPE_SRC_FORMAT_R_BPC
119. MDP5_PIPE_SRC_FORMAT_A_BPC
120. MDP5_PIPE_SRC_FORMAT_CPP
121. MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT
122. MDP5_PIPE_SRC_FORMAT_FETCH_TYPE
123. MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP
124. REG_MDP5_PIPE_SRC_UNPACK
125. MDP5_PIPE_SRC_UNPACK_ELEM0
126. MDP5_PIPE_SRC_UNPACK_ELEM1
127. MDP5_PIPE_SRC_UNPACK_ELEM2
128. MDP5_PIPE_SRC_UNPACK_ELEM3
129. REG_MDP5_PIPE_SRC_OP_MODE
130. MDP5_PIPE_SRC_OP_MODE_BWC
131. REG_MDP5_PIPE_SRC_CONSTANT_COLOR
132. REG_MDP5_PIPE_FETCH_CONFIG
133. REG_MDP5_PIPE_VC1_RANGE
134. REG_MDP5_PIPE_REQPRIO_FIFO_WM_0
135. REG_MDP5_PIPE_REQPRIO_FIFO_WM_1
136. REG_MDP5_PIPE_REQPRIO_FIFO_WM_2
137. REG_MDP5_PIPE_SRC_ADDR_SW_STATUS
138. REG_MDP5_PIPE_CURRENT_SRC0_ADDR
139. REG_MDP5_PIPE_CURRENT_SRC1_ADDR
140. REG_MDP5_PIPE_CURRENT_SRC2_ADDR
141. REG_MDP5_PIPE_CURRENT_SRC3_ADDR
142. REG_MDP5_PIPE_DECIMATION
143. MDP5_PIPE_DECIMATION_VERT
144. MDP5_PIPE_DECIMATION_HORZ
145. __offset_SW_PIX_EXT
146. REG_MDP5_PIPE_SW_PIX_EXT
147. REG_MDP5_PIPE_SW_PIX_EXT_LR
148. MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT
149. MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF
150. MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT
151. MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF
152. REG_MDP5_PIPE_SW_PIX_EXT_TB
153. MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT
154. MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF
155. MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT
156. MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF
157. REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS
158. MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT
159. MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM
160. REG_MDP5_PIPE_SCALE_CONFIG
161. MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0
162. MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0
163. MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2
164. MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2
165. MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3
166. MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3
167. REG_MDP5_PIPE_SCALE_PHASE_STEP_X
168. REG_MDP5_PIPE_SCALE_PHASE_STEP_Y
169. REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X
170. REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y
171. REG_MDP5_PIPE_SCALE_INIT_PHASE_X
172. REG_MDP5_PIPE_SCALE_INIT_PHASE_Y
173. __offset_LM
174. REG_MDP5_LM
175. REG_MDP5_LM_BLEND_COLOR_OUT
176. REG_MDP5_LM_OUT_SIZE
177. MDP5_LM_OUT_SIZE_HEIGHT
178. MDP5_LM_OUT_SIZE_WIDTH
179. REG_MDP5_LM_BORDER_COLOR_0
180. REG_MDP5_LM_BORDER_COLOR_1
181. __offset_BLEND
182. REG_MDP5_LM_BLEND
183. REG_MDP5_LM_BLEND_OP_MODE
184. MDP5_LM_BLEND_OP_MODE_FG_ALPHA
185. MDP5_LM_BLEND_OP_MODE_BG_ALPHA
186. REG_MDP5_LM_BLEND_FG_ALPHA
187. REG_MDP5_LM_BLEND_BG_ALPHA
188. REG_MDP5_LM_BLEND_FG_TRANSP_LOW0
189. REG_MDP5_LM_BLEND_FG_TRANSP_LOW1
190. REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0
191. REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1
192. REG_MDP5_LM_BLEND_BG_TRANSP_LOW0
193. REG_MDP5_LM_BLEND_BG_TRANSP_LOW1
194. REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0
195. REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1
196. REG_MDP5_LM_CURSOR_IMG_SIZE
197. MDP5_LM_CURSOR_IMG_SIZE_SRC_W
198. MDP5_LM_CURSOR_IMG_SIZE_SRC_H
199. REG_MDP5_LM_CURSOR_SIZE
200. MDP5_LM_CURSOR_SIZE_ROI_W
201. MDP5_LM_CURSOR_SIZE_ROI_H
202. REG_MDP5_LM_CURSOR_XY
203. MDP5_LM_CURSOR_XY_SRC_X
204. MDP5_LM_CURSOR_XY_SRC_Y
205. REG_MDP5_LM_CURSOR_STRIDE
206. MDP5_LM_CURSOR_STRIDE_STRIDE
207. REG_MDP5_LM_CURSOR_FORMAT
208. MDP5_LM_CURSOR_FORMAT_FORMAT
209. REG_MDP5_LM_CURSOR_BASE_ADDR
210. REG_MDP5_LM_CURSOR_START_XY
211. MDP5_LM_CURSOR_START_XY_X_START
212. MDP5_LM_CURSOR_START_XY_Y_START
213. REG_MDP5_LM_CURSOR_BLEND_CONFIG
214. MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL
215. REG_MDP5_LM_CURSOR_BLEND_PARAM
216. REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0
217. REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1
218. REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0
219. REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1
220. REG_MDP5_LM_GC_LUT_BASE
221. __offset_DSPP
222. REG_MDP5_DSPP
223. REG_MDP5_DSPP_OP_MODE
224. MDP5_DSPP_OP_MODE_IGC_TBL_IDX
225. REG_MDP5_DSPP_PCC_BASE
226. REG_MDP5_DSPP_DITHER_DEPTH
227. REG_MDP5_DSPP_HIST_CTL_BASE
228. REG_MDP5_DSPP_HIST_LUT_BASE
229. REG_MDP5_DSPP_HIST_LUT_SWAP
230. REG_MDP5_DSPP_PA_BASE
231. REG_MDP5_DSPP_GAMUT_BASE
232. REG_MDP5_DSPP_GC_BASE
233. __offset_PP
234. REG_MDP5_PP
235. REG_MDP5_PP_TEAR_CHECK_EN
236. REG_MDP5_PP_SYNC_CONFIG_VSYNC
237. MDP5_PP_SYNC_CONFIG_VSYNC_COUNT
238. REG_MDP5_PP_SYNC_CONFIG_HEIGHT
239. REG_MDP5_PP_SYNC_WRCOUNT
240. MDP5_PP_SYNC_WRCOUNT_LINE_COUNT
241. MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT
242. REG_MDP5_PP_VSYNC_INIT_VAL
243. REG_MDP5_PP_INT_COUNT_VAL
244. MDP5_PP_INT_COUNT_VAL_LINE_COUNT
245. MDP5_PP_INT_COUNT_VAL_FRAME_COUNT
246. REG_MDP5_PP_SYNC_THRESH
247. MDP5_PP_SYNC_THRESH_START
248. MDP5_PP_SYNC_THRESH_CONTINUE
249. REG_MDP5_PP_START_POS
250. REG_MDP5_PP_RD_PTR_IRQ
251. REG_MDP5_PP_WR_PTR_IRQ
252. REG_MDP5_PP_OUT_LINE_COUNT
253. REG_MDP5_PP_PP_LINE_COUNT
254. REG_MDP5_PP_AUTOREFRESH_CONFIG
255. REG_MDP5_PP_FBC_MODE
256. REG_MDP5_PP_FBC_BUDGET_CTL
257. REG_MDP5_PP_FBC_LOSSY_MODE
258. __offset_WB
259. REG_MDP5_WB
260. REG_MDP5_WB_DST_FORMAT
261. MDP5_WB_DST_FORMAT_DSTC0_OUT
262. MDP5_WB_DST_FORMAT_DSTC1_OUT
263. MDP5_WB_DST_FORMAT_DSTC2_OUT
264. MDP5_WB_DST_FORMAT_DSTC3_OUT
265. MDP5_WB_DST_FORMAT_DST_BPP
266. MDP5_WB_DST_FORMAT_PACK_COUNT
267. MDP5_WB_DST_FORMAT_WRITE_PLANES
268. MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP
269. MDP5_WB_DST_FORMAT_DST_CHROMA_SITE
270. MDP5_WB_DST_FORMAT_FRAME_FORMAT
271. REG_MDP5_WB_DST_OP_MODE
272. MDP5_WB_DST_OP_MODE_BWC_ENC_OP
273. MDP5_WB_DST_OP_MODE_BLOCK_SIZE
274. MDP5_WB_DST_OP_MODE_ROT_MODE
275. MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT
276. MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT
277. MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT
278. MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD
279. MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD
280. REG_MDP5_WB_DST_PACK_PATTERN
281. MDP5_WB_DST_PACK_PATTERN_ELEMENT0
282. MDP5_WB_DST_PACK_PATTERN_ELEMENT1
283. MDP5_WB_DST_PACK_PATTERN_ELEMENT2
284. MDP5_WB_DST_PACK_PATTERN_ELEMENT3
285. REG_MDP5_WB_DST0_ADDR
286. REG_MDP5_WB_DST1_ADDR
287. REG_MDP5_WB_DST2_ADDR
288. REG_MDP5_WB_DST3_ADDR
289. REG_MDP5_WB_DST_YSTRIDE0
290. MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE
291. MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE
292. REG_MDP5_WB_DST_YSTRIDE1
293. MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE
294. MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE
295. REG_MDP5_WB_DST_DITHER_BITDEPTH
296. REG_MDP5_WB_DITHER_MATRIX_ROW0
297. REG_MDP5_WB_DITHER_MATRIX_ROW1
298. REG_MDP5_WB_DITHER_MATRIX_ROW2
299. REG_MDP5_WB_DITHER_MATRIX_ROW3
300. REG_MDP5_WB_DST_WRITE_CONFIG
301. REG_MDP5_WB_ROTATION_DNSCALER
302. REG_MDP5_WB_N16_INIT_PHASE_X_0_3
303. REG_MDP5_WB_N16_INIT_PHASE_X_1_2
304. REG_MDP5_WB_N16_INIT_PHASE_Y_0_3
305. REG_MDP5_WB_N16_INIT_PHASE_Y_1_2
306. REG_MDP5_WB_OUT_SIZE
307. MDP5_WB_OUT_SIZE_DST_W
308. MDP5_WB_OUT_SIZE_DST_H
309. REG_MDP5_WB_ALPHA_X_VALUE
310. REG_MDP5_WB_CSC_MATRIX_COEFF_0
311. MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11
312. MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12
313. REG_MDP5_WB_CSC_MATRIX_COEFF_1
314. MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13
315. MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21
316. REG_MDP5_WB_CSC_MATRIX_COEFF_2
317. MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22
318. MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23
319. REG_MDP5_WB_CSC_MATRIX_COEFF_3
320. MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31
321. MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32
322. REG_MDP5_WB_CSC_MATRIX_COEFF_4
323. MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33
324. REG_MDP5_WB_CSC_COMP_PRECLAMP
325. REG_MDP5_WB_CSC_COMP_PRECLAMP_REG
326. MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH
327. MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW
328. REG_MDP5_WB_CSC_COMP_POSTCLAMP
329. REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG
330. MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH
331. MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW
332. REG_MDP5_WB_CSC_COMP_PREBIAS
333. REG_MDP5_WB_CSC_COMP_PREBIAS_REG
334. MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE
335. REG_MDP5_WB_CSC_COMP_POSTBIAS
336. REG_MDP5_WB_CSC_COMP_POSTBIAS_REG
337. MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE
338. __offset_INTF
339. REG_MDP5_INTF
340. REG_MDP5_INTF_TIMING_ENGINE_EN
341. REG_MDP5_INTF_CONFIG
342. REG_MDP5_INTF_HSYNC_CTL
343. MDP5_INTF_HSYNC_CTL_PULSEW
344. MDP5_INTF_HSYNC_CTL_PERIOD
345. REG_MDP5_INTF_VSYNC_PERIOD_F0
346. REG_MDP5_INTF_VSYNC_PERIOD_F1
347. REG_MDP5_INTF_VSYNC_LEN_F0
348. REG_MDP5_INTF_VSYNC_LEN_F1
349. REG_MDP5_INTF_DISPLAY_VSTART_F0
350. REG_MDP5_INTF_DISPLAY_VSTART_F1
351. REG_MDP5_INTF_DISPLAY_VEND_F0
352. REG_MDP5_INTF_DISPLAY_VEND_F1
353. REG_MDP5_INTF_ACTIVE_VSTART_F0
354. MDP5_INTF_ACTIVE_VSTART_F0_VAL
355. REG_MDP5_INTF_ACTIVE_VSTART_F1
356. MDP5_INTF_ACTIVE_VSTART_F1_VAL
357. REG_MDP5_INTF_ACTIVE_VEND_F0
358. REG_MDP5_INTF_ACTIVE_VEND_F1
359. REG_MDP5_INTF_DISPLAY_HCTL
360. MDP5_INTF_DISPLAY_HCTL_START
361. MDP5_INTF_DISPLAY_HCTL_END
362. REG_MDP5_INTF_ACTIVE_HCTL
363. MDP5_INTF_ACTIVE_HCTL_START
364. MDP5_INTF_ACTIVE_HCTL_END
365. REG_MDP5_INTF_BORDER_COLOR
366. REG_MDP5_INTF_UNDERFLOW_COLOR
367. REG_MDP5_INTF_HSYNC_SKEW
368. REG_MDP5_INTF_POLARITY_CTL
369. REG_MDP5_INTF_TEST_CTL
370. REG_MDP5_INTF_TP_COLOR0
371. REG_MDP5_INTF_TP_COLOR1
372. REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN
373. REG_MDP5_INTF_PANEL_FORMAT
374. REG_MDP5_INTF_FRAME_LINE_COUNT_EN
375. REG_MDP5_INTF_FRAME_COUNT
376. REG_MDP5_INTF_LINE_COUNT
377. REG_MDP5_INTF_DEFLICKER_CONFIG
378. REG_MDP5_INTF_DEFLICKER_STRNG_COEFF
379. REG_MDP5_INTF_DEFLICKER_WEAK_COEFF
380. REG_MDP5_INTF_TPG_ENABLE
381. REG_MDP5_INTF_TPG_MAIN_CONTROL
382. REG_MDP5_INTF_TPG_VIDEO_CONFIG
383. REG_MDP5_INTF_TPG_COMPONENT_LIMITS
384. REG_MDP5_INTF_TPG_RECTANGLE
385. REG_MDP5_INTF_TPG_INITIAL_VALUE
386. REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME
387. REG_MDP5_INTF_TPG_RGB_MAPPING
388. __offset_AD
389. REG_MDP5_AD
390. REG_MDP5_AD_BYPASS
391. REG_MDP5_AD_CTRL_0
392. REG_MDP5_AD_CTRL_1
393. REG_MDP5_AD_FRAME_SIZE
394. REG_MDP5_AD_CON_CTRL_0
395. REG_MDP5_AD_CON_CTRL_1
396. REG_MDP5_AD_STR_MAN
397. REG_MDP5_AD_VAR
398. REG_MDP5_AD_DITH
399. REG_MDP5_AD_DITH_CTRL
400. REG_MDP5_AD_AMP_LIM
401. REG_MDP5_AD_SLOPE
402. REG_MDP5_AD_BW_LVL
403. REG_MDP5_AD_LOGO_POS
404. REG_MDP5_AD_LUT_FI
405. REG_MDP5_AD_LUT_CC
406. REG_MDP5_AD_STR_LIM
407. REG_MDP5_AD_CALIB_AB
408. REG_MDP5_AD_CALIB_CD
409. REG_MDP5_AD_MODE_SEL
410. REG_MDP5_AD_TFILT_CTRL
411. REG_MDP5_AD_BL_MINMAX
412. REG_MDP5_AD_BL
413. REG_MDP5_AD_BL_MAX
414. REG_MDP5_AD_AL
415. REG_MDP5_AD_AL_MIN
416. REG_MDP5_AD_AL_FILT
417. REG_MDP5_AD_CFG_BUF
418. REG_MDP5_AD_LUT_AL
419. REG_MDP5_AD_TARG_STR
420. REG_MDP5_AD_START_CALC
421. REG_MDP5_AD_STR_OUT
422. REG_MDP5_AD_BL_OUT
423. REG_MDP5_AD_CALC_DONE

   1 #ifndef MDP5_XML
   2 #define MDP5_XML
   3 
   4 /* Autogenerated file, DO NOT EDIT manually!
   5 
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9 
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/envytools/rnndb/msm.xml                 (    676 bytes, from 2018-07-03 19:37:13)
  12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2018-07-03 19:37:13)
  13 - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2018-07-03 19:37:13)
  14 - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2018-07-03 19:37:13)
  15 - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2018-07-03 19:37:13)
  16 - /home/robclark/src/envytools/rnndb/dsi/dsi.xml             (  37239 bytes, from 2018-07-03 19:37:13)
  17 - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2018-07-03 19:37:13)
  18 - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2018-07-03 19:37:13)
  19 - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2018-07-03 19:37:13)
  20 - /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml           (  41799 bytes, from 2018-07-03 19:37:13)
  21 - /home/robclark/src/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2018-07-03 19:37:13)
  22 
  23 Copyright (C) 2013-2018 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26 
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34 
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38 
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47 
  48 
  49 enum mdp5_intf_type {
  50         INTF_DISABLED = 0,
  51         INTF_DSI = 1,
  52         INTF_HDMI = 3,
  53         INTF_LCDC = 5,
  54         INTF_eDP = 9,
  55         INTF_VIRTUAL = 100,
  56         INTF_WB = 101,
  57 };
  58 
  59 enum mdp5_intfnum {
  60         NO_INTF = 0,
  61         INTF0 = 1,
  62         INTF1 = 2,
  63         INTF2 = 3,
  64         INTF3 = 4,
  65 };
  66 
  67 enum mdp5_pipe {
  68         SSPP_NONE = 0,
  69         SSPP_VIG0 = 1,
  70         SSPP_VIG1 = 2,
  71         SSPP_VIG2 = 3,
  72         SSPP_RGB0 = 4,
  73         SSPP_RGB1 = 5,
  74         SSPP_RGB2 = 6,
  75         SSPP_DMA0 = 7,
  76         SSPP_DMA1 = 8,
  77         SSPP_VIG3 = 9,
  78         SSPP_RGB3 = 10,
  79         SSPP_CURSOR0 = 11,
  80         SSPP_CURSOR1 = 12,
  81 };
  82 
  83 enum mdp5_ctl_mode {
  84         MODE_NONE = 0,
  85         MODE_WB_0_BLOCK = 1,
  86         MODE_WB_1_BLOCK = 2,
  87         MODE_WB_0_LINE = 3,
  88         MODE_WB_1_LINE = 4,
  89         MODE_WB_2_LINE = 5,
  90 };
  91 
  92 enum mdp5_pack_3d {
  93         PACK_3D_FRAME_INT = 0,
  94         PACK_3D_H_ROW_INT = 1,
  95         PACK_3D_V_ROW_INT = 2,
  96         PACK_3D_COL_INT = 3,
  97 };
  98 
  99 enum mdp5_scale_filter {
 100         SCALE_FILTER_NEAREST = 0,
 101         SCALE_FILTER_BIL = 1,
 102         SCALE_FILTER_PCMN = 2,
 103         SCALE_FILTER_CA = 3,
 104 };
 105 
 106 enum mdp5_pipe_bwc {
 107         BWC_LOSSLESS = 0,
 108         BWC_Q_HIGH = 1,
 109         BWC_Q_MED = 2,
 110 };
 111 
 112 enum mdp5_cursor_format {
 113         CURSOR_FMT_ARGB8888 = 0,
 114         CURSOR_FMT_ARGB1555 = 2,
 115         CURSOR_FMT_ARGB4444 = 4,
 116 };
 117 
 118 enum mdp5_cursor_alpha {
 119         CURSOR_ALPHA_CONST = 0,
 120         CURSOR_ALPHA_PER_PIXEL = 2,
 121 };
 122 
 123 enum mdp5_igc_type {
 124         IGC_VIG = 0,
 125         IGC_RGB = 1,
 126         IGC_DMA = 2,
 127         IGC_DSPP = 3,
 128 };
 129 
 130 enum mdp5_data_format {
 131         DATA_FORMAT_RGB = 0,
 132         DATA_FORMAT_YUV = 1,
 133 };
 134 
 135 enum mdp5_block_size {
 136         BLOCK_SIZE_64 = 0,
 137         BLOCK_SIZE_128 = 1,
 138 };
 139 
 140 enum mdp5_rotate_mode {
 141         ROTATE_0 = 0,
 142         ROTATE_90 = 1,
 143 };
 144 
 145 enum mdp5_chroma_downsample_method {
 146         DS_MTHD_NO_PIXEL_DROP = 0,
 147         DS_MTHD_PIXEL_DROP = 1,
 148 };
 149 
 150 #define MDP5_IRQ_WB_0_DONE                                      0x00000001
 151 #define MDP5_IRQ_WB_1_DONE                                      0x00000002
 152 #define MDP5_IRQ_WB_2_DONE                                      0x00000010
 153 #define MDP5_IRQ_PING_PONG_0_DONE                               0x00000100
 154 #define MDP5_IRQ_PING_PONG_1_DONE                               0x00000200
 155 #define MDP5_IRQ_PING_PONG_2_DONE                               0x00000400
 156 #define MDP5_IRQ_PING_PONG_3_DONE                               0x00000800
 157 #define MDP5_IRQ_PING_PONG_0_RD_PTR                             0x00001000
 158 #define MDP5_IRQ_PING_PONG_1_RD_PTR                             0x00002000
 159 #define MDP5_IRQ_PING_PONG_2_RD_PTR                             0x00004000
 160 #define MDP5_IRQ_PING_PONG_3_RD_PTR                             0x00008000
 161 #define MDP5_IRQ_PING_PONG_0_WR_PTR                             0x00010000
 162 #define MDP5_IRQ_PING_PONG_1_WR_PTR                             0x00020000
 163 #define MDP5_IRQ_PING_PONG_2_WR_PTR                             0x00040000
 164 #define MDP5_IRQ_PING_PONG_3_WR_PTR                             0x00080000
 165 #define MDP5_IRQ_PING_PONG_0_AUTO_REF                           0x00100000
 166 #define MDP5_IRQ_PING_PONG_1_AUTO_REF                           0x00200000
 167 #define MDP5_IRQ_PING_PONG_2_AUTO_REF                           0x00400000
 168 #define MDP5_IRQ_PING_PONG_3_AUTO_REF                           0x00800000
 169 #define MDP5_IRQ_INTF0_UNDER_RUN                                0x01000000
 170 #define MDP5_IRQ_INTF0_VSYNC                                    0x02000000
 171 #define MDP5_IRQ_INTF1_UNDER_RUN                                0x04000000
 172 #define MDP5_IRQ_INTF1_VSYNC                                    0x08000000
 173 #define MDP5_IRQ_INTF2_UNDER_RUN                                0x10000000
 174 #define MDP5_IRQ_INTF2_VSYNC                                    0x20000000
 175 #define MDP5_IRQ_INTF3_UNDER_RUN                                0x40000000
 176 #define MDP5_IRQ_INTF3_VSYNC                                    0x80000000
 177 #define REG_MDSS_HW_VERSION                                     0x00000000
 178 #define MDSS_HW_VERSION_STEP__MASK                              0x0000ffff
 179 #define MDSS_HW_VERSION_STEP__SHIFT                             0
 180 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
 181 {
 182         return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
 183 }
 184 #define MDSS_HW_VERSION_MINOR__MASK                             0x0fff0000
 185 #define MDSS_HW_VERSION_MINOR__SHIFT                            16
 186 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
 187 {
 188         return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
 189 }
 190 #define MDSS_HW_VERSION_MAJOR__MASK                             0xf0000000
 191 #define MDSS_HW_VERSION_MAJOR__SHIFT                            28
 192 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
 193 {
 194         return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
 195 }
 196 
 197 #define REG_MDSS_HW_INTR_STATUS                                 0x00000010
 198 #define MDSS_HW_INTR_STATUS_INTR_MDP                            0x00000001
 199 #define MDSS_HW_INTR_STATUS_INTR_DSI0                           0x00000010
 200 #define MDSS_HW_INTR_STATUS_INTR_DSI1                           0x00000020
 201 #define MDSS_HW_INTR_STATUS_INTR_HDMI                           0x00000100
 202 #define MDSS_HW_INTR_STATUS_INTR_EDP                            0x00001000
 203 
 204 #define REG_MDP5_HW_VERSION                                     0x00000000
 205 #define MDP5_HW_VERSION_STEP__MASK                              0x0000ffff
 206 #define MDP5_HW_VERSION_STEP__SHIFT                             0
 207 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
 208 {
 209         return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
 210 }
 211 #define MDP5_HW_VERSION_MINOR__MASK                             0x0fff0000
 212 #define MDP5_HW_VERSION_MINOR__SHIFT                            16
 213 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
 214 {
 215         return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
 216 }
 217 #define MDP5_HW_VERSION_MAJOR__MASK                             0xf0000000
 218 #define MDP5_HW_VERSION_MAJOR__SHIFT                            28
 219 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
 220 {
 221         return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
 222 }
 223 
 224 #define REG_MDP5_DISP_INTF_SEL                                  0x00000004
 225 #define MDP5_DISP_INTF_SEL_INTF0__MASK                          0x000000ff
 226 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT                         0
 227 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
 228 {
 229         return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
 230 }
 231 #define MDP5_DISP_INTF_SEL_INTF1__MASK                          0x0000ff00
 232 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT                         8
 233 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
 234 {
 235         return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
 236 }
 237 #define MDP5_DISP_INTF_SEL_INTF2__MASK                          0x00ff0000
 238 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT                         16
 239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
 240 {
 241         return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
 242 }
 243 #define MDP5_DISP_INTF_SEL_INTF3__MASK                          0xff000000
 244 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT                         24
 245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
 246 {
 247         return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
 248 }
 249 
 250 #define REG_MDP5_INTR_EN                                        0x00000010
 251 
 252 #define REG_MDP5_INTR_STATUS                                    0x00000014
 253 
 254 #define REG_MDP5_INTR_CLEAR                                     0x00000018
 255 
 256 #define REG_MDP5_HIST_INTR_EN                                   0x0000001c
 257 
 258 #define REG_MDP5_HIST_INTR_STATUS                               0x00000020
 259 
 260 #define REG_MDP5_HIST_INTR_CLEAR                                0x00000024
 261 
 262 #define REG_MDP5_SPARE_0                                        0x00000028
 263 #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN                  0x00000001
 264 
 265 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
 266 
 267 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
 268 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK                      0x000000ff
 269 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT                     0
 270 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
 271 {
 272         return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
 273 }
 274 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK                      0x0000ff00
 275 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT                     8
 276 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
 277 {
 278         return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
 279 }
 280 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK                      0x00ff0000
 281 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT                     16
 282 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
 283 {
 284         return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
 285 }
 286 
 287 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
 288 
 289 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
 290 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK                      0x000000ff
 291 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT                     0
 292 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
 293 {
 294         return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
 295 }
 296 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK                      0x0000ff00
 297 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT                     8
 298 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
 299 {
 300         return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
 301 }
 302 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK                      0x00ff0000
 303 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT                     16
 304 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
 305 {
 306         return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
 307 }
 308 
 309 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
 310 {
 311         switch (idx) {
 312                 case IGC_VIG: return 0x00000200;
 313                 case IGC_RGB: return 0x00000210;
 314                 case IGC_DMA: return 0x00000220;
 315                 case IGC_DSPP: return 0x00000300;
 316                 default: return INVALID_IDX(idx);
 317         }
 318 }
 319 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
 320 
 321 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
 322 
 323 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
 324 #define MDP5_IGC_LUT_REG_VAL__MASK                              0x00000fff
 325 #define MDP5_IGC_LUT_REG_VAL__SHIFT                             0
 326 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
 327 {
 328         return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
 329 }
 330 #define MDP5_IGC_LUT_REG_INDEX_UPDATE                           0x02000000
 331 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0                         0x10000000
 332 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1                         0x20000000
 333 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2                         0x40000000
 334 
 335 #define REG_MDP5_SPLIT_DPL_EN                                   0x000002f4
 336 
 337 #define REG_MDP5_SPLIT_DPL_UPPER                                0x000002f8
 338 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL                        0x00000002
 339 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN               0x00000004
 340 #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX                   0x00000010
 341 #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX                   0x00000100
 342 
 343 #define REG_MDP5_SPLIT_DPL_LOWER                                0x000003f0
 344 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL                        0x00000002
 345 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN               0x00000004
 346 #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC                      0x00000010
 347 #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC                      0x00000100
 348 
 349 static inline uint32_t __offset_CTL(uint32_t idx)
 350 {
 351         switch (idx) {
 352                 case 0: return (mdp5_cfg->ctl.base[0]);
 353                 case 1: return (mdp5_cfg->ctl.base[1]);
 354                 case 2: return (mdp5_cfg->ctl.base[2]);
 355                 case 3: return (mdp5_cfg->ctl.base[3]);
 356                 case 4: return (mdp5_cfg->ctl.base[4]);
 357                 default: return INVALID_IDX(idx);
 358         }
 359 }
 360 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
 361 
 362 static inline uint32_t __offset_LAYER(uint32_t idx)
 363 {
 364         switch (idx) {
 365                 case 0: return 0x00000000;
 366                 case 1: return 0x00000004;
 367                 case 2: return 0x00000008;
 368                 case 3: return 0x0000000c;
 369                 case 4: return 0x00000010;
 370                 case 5: return 0x00000024;
 371                 default: return INVALID_IDX(idx);
 372         }
 373 }
 374 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
 375 
 376 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
 377 #define MDP5_CTL_LAYER_REG_VIG0__MASK                           0x00000007
 378 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT                          0
 379 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
 380 {
 381         return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
 382 }
 383 #define MDP5_CTL_LAYER_REG_VIG1__MASK                           0x00000038
 384 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT                          3
 385 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
 386 {
 387         return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
 388 }
 389 #define MDP5_CTL_LAYER_REG_VIG2__MASK                           0x000001c0
 390 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT                          6
 391 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
 392 {
 393         return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
 394 }
 395 #define MDP5_CTL_LAYER_REG_RGB0__MASK                           0x00000e00
 396 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT                          9
 397 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
 398 {
 399         return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
 400 }
 401 #define MDP5_CTL_LAYER_REG_RGB1__MASK                           0x00007000
 402 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT                          12
 403 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
 404 {
 405         return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
 406 }
 407 #define MDP5_CTL_LAYER_REG_RGB2__MASK                           0x00038000
 408 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT                          15
 409 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
 410 {
 411         return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
 412 }
 413 #define MDP5_CTL_LAYER_REG_DMA0__MASK                           0x001c0000
 414 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT                          18
 415 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
 416 {
 417         return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
 418 }
 419 #define MDP5_CTL_LAYER_REG_DMA1__MASK                           0x00e00000
 420 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT                          21
 421 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
 422 {
 423         return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
 424 }
 425 #define MDP5_CTL_LAYER_REG_BORDER_COLOR                         0x01000000
 426 #define MDP5_CTL_LAYER_REG_CURSOR_OUT                           0x02000000
 427 #define MDP5_CTL_LAYER_REG_VIG3__MASK                           0x1c000000
 428 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT                          26
 429 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
 430 {
 431         return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
 432 }
 433 #define MDP5_CTL_LAYER_REG_RGB3__MASK                           0xe0000000
 434 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT                          29
 435 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
 436 {
 437         return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
 438 }
 439 
 440 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
 441 #define MDP5_CTL_OP_MODE__MASK                                  0x0000000f
 442 #define MDP5_CTL_OP_MODE__SHIFT                                 0
 443 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
 444 {
 445         return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
 446 }
 447 #define MDP5_CTL_OP_INTF_NUM__MASK                              0x00000070
 448 #define MDP5_CTL_OP_INTF_NUM__SHIFT                             4
 449 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
 450 {
 451         return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
 452 }
 453 #define MDP5_CTL_OP_CMD_MODE                                    0x00020000
 454 #define MDP5_CTL_OP_PACK_3D_ENABLE                              0x00080000
 455 #define MDP5_CTL_OP_PACK_3D__MASK                               0x00300000
 456 #define MDP5_CTL_OP_PACK_3D__SHIFT                              20
 457 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
 458 {
 459         return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
 460 }
 461 
 462 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
 463 #define MDP5_CTL_FLUSH_VIG0                                     0x00000001
 464 #define MDP5_CTL_FLUSH_VIG1                                     0x00000002
 465 #define MDP5_CTL_FLUSH_VIG2                                     0x00000004
 466 #define MDP5_CTL_FLUSH_RGB0                                     0x00000008
 467 #define MDP5_CTL_FLUSH_RGB1                                     0x00000010
 468 #define MDP5_CTL_FLUSH_RGB2                                     0x00000020
 469 #define MDP5_CTL_FLUSH_LM0                                      0x00000040
 470 #define MDP5_CTL_FLUSH_LM1                                      0x00000080
 471 #define MDP5_CTL_FLUSH_LM2                                      0x00000100
 472 #define MDP5_CTL_FLUSH_LM3                                      0x00000200
 473 #define MDP5_CTL_FLUSH_LM4                                      0x00000400
 474 #define MDP5_CTL_FLUSH_DMA0                                     0x00000800
 475 #define MDP5_CTL_FLUSH_DMA1                                     0x00001000
 476 #define MDP5_CTL_FLUSH_DSPP0                                    0x00002000
 477 #define MDP5_CTL_FLUSH_DSPP1                                    0x00004000
 478 #define MDP5_CTL_FLUSH_DSPP2                                    0x00008000
 479 #define MDP5_CTL_FLUSH_WB                                       0x00010000
 480 #define MDP5_CTL_FLUSH_CTL                                      0x00020000
 481 #define MDP5_CTL_FLUSH_VIG3                                     0x00040000
 482 #define MDP5_CTL_FLUSH_RGB3                                     0x00080000
 483 #define MDP5_CTL_FLUSH_LM5                                      0x00100000
 484 #define MDP5_CTL_FLUSH_DSPP3                                    0x00200000
 485 #define MDP5_CTL_FLUSH_CURSOR_0                                 0x00400000
 486 #define MDP5_CTL_FLUSH_CURSOR_1                                 0x00800000
 487 #define MDP5_CTL_FLUSH_CHROMADOWN_0                             0x04000000
 488 #define MDP5_CTL_FLUSH_TIMING_3                                 0x10000000
 489 #define MDP5_CTL_FLUSH_TIMING_2                                 0x20000000
 490 #define MDP5_CTL_FLUSH_TIMING_1                                 0x40000000
 491 #define MDP5_CTL_FLUSH_TIMING_0                                 0x80000000
 492 
 493 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
 494 
 495 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
 496 
 497 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
 498 {
 499         switch (idx) {
 500                 case 0: return 0x00000040;
 501                 case 1: return 0x00000044;
 502                 case 2: return 0x00000048;
 503                 case 3: return 0x0000004c;
 504                 case 4: return 0x00000050;
 505                 case 5: return 0x00000054;
 506                 default: return INVALID_IDX(idx);
 507         }
 508 }
 509 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
 510 
 511 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
 512 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3                        0x00000001
 513 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3                        0x00000004
 514 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3                        0x00000010
 515 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3                        0x00000040
 516 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3                        0x00000100
 517 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3                        0x00000400
 518 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3                        0x00001000
 519 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3                        0x00004000
 520 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3                        0x00010000
 521 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3                        0x00040000
 522 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK                    0x00f00000
 523 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT                   20
 524 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
 525 {
 526         return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
 527 }
 528 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK                    0x3c000000
 529 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT                   26
 530 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
 531 {
 532         return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
 533 }
 534 
 535 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
 536 {
 537         switch (idx) {
 538                 case SSPP_NONE: return (INVALID_IDX(idx));
 539                 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
 540                 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
 541                 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
 542                 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
 543                 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
 544                 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
 545                 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
 546                 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
 547                 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
 548                 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
 549                 case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
 550                 case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]);
 551                 default: return INVALID_IDX(idx);
 552         }
 553 }
 554 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
 555 
 556 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
 557 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK             0x00080000
 558 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT            19
 559 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
 560 {
 561         return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
 562 }
 563 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK             0x00040000
 564 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT            18
 565 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
 566 {
 567         return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
 568 }
 569 #define MDP5_PIPE_OP_MODE_CSC_1_EN                              0x00020000
 570 
 571 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
 572 
 573 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
 574 
 575 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
 576 
 577 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
 578 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK           0x00001fff
 579 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT          0
 580 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
 581 {
 582         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
 583 }
 584 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK           0x1fff0000
 585 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT          16
 586 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
 587 {
 588         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
 589 }
 590 
 591 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
 592 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK           0x00001fff
 593 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT          0
 594 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
 595 {
 596         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
 597 }
 598 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK           0x1fff0000
 599 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT          16
 600 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
 601 {
 602         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
 603 }
 604 
 605 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
 606 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK           0x00001fff
 607 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT          0
 608 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
 609 {
 610         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
 611 }
 612 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK           0x1fff0000
 613 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT          16
 614 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
 615 {
 616         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
 617 }
 618 
 619 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
 620 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK           0x00001fff
 621 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT          0
 622 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
 623 {
 624         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
 625 }
 626 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK           0x1fff0000
 627 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT          16
 628 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
 629 {
 630         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
 631 }
 632 
 633 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
 634 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK           0x00001fff
 635 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT          0
 636 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
 637 {
 638         return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
 639 }
 640 
 641 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
 642 
 643 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
 644 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK                0x000000ff
 645 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT               0
 646 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
 647 {
 648         return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
 649 }
 650 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK                 0x0000ff00
 651 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT                8
 652 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
 653 {
 654         return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
 655 }
 656 
 657 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
 658 
 659 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
 660 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK               0x000000ff
 661 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT              0
 662 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
 663 {
 664         return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
 665 }
 666 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK                0x0000ff00
 667 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT               8
 668 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
 669 {
 670         return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
 671 }
 672 
 673 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
 674 
 675 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
 676 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK                0x000001ff
 677 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT               0
 678 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
 679 {
 680         return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
 681 }
 682 
 683 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
 684 
 685 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
 686 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK               0x000001ff
 687 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT              0
 688 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
 689 {
 690         return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
 691 }
 692 
 693 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
 694 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK                         0xffff0000
 695 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT                        16
 696 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
 697 {
 698         return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
 699 }
 700 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK                          0x0000ffff
 701 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT                         0
 702 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
 703 {
 704         return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
 705 }
 706 
 707 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
 708 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK                     0xffff0000
 709 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT                    16
 710 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
 711 {
 712         return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
 713 }
 714 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK                      0x0000ffff
 715 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT                     0
 716 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
 717 {
 718         return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
 719 }
 720 
 721 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
 722 #define MDP5_PIPE_SRC_XY_Y__MASK                                0xffff0000
 723 #define MDP5_PIPE_SRC_XY_Y__SHIFT                               16
 724 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
 725 {
 726         return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
 727 }
 728 #define MDP5_PIPE_SRC_XY_X__MASK                                0x0000ffff
 729 #define MDP5_PIPE_SRC_XY_X__SHIFT                               0
 730 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
 731 {
 732         return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
 733 }
 734 
 735 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
 736 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK                         0xffff0000
 737 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT                        16
 738 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
 739 {
 740         return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
 741 }
 742 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK                          0x0000ffff
 743 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT                         0
 744 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
 745 {
 746         return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
 747 }
 748 
 749 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
 750 #define MDP5_PIPE_OUT_XY_Y__MASK                                0xffff0000
 751 #define MDP5_PIPE_OUT_XY_Y__SHIFT                               16
 752 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
 753 {
 754         return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
 755 }
 756 #define MDP5_PIPE_OUT_XY_X__MASK                                0x0000ffff
 757 #define MDP5_PIPE_OUT_XY_X__SHIFT                               0
 758 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
 759 {
 760         return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
 761 }
 762 
 763 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
 764 
 765 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
 766 
 767 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
 768 
 769 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
 770 
 771 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
 772 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK                         0x0000ffff
 773 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT                        0
 774 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
 775 {
 776         return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
 777 }
 778 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK                         0xffff0000
 779 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT                        16
 780 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
 781 {
 782         return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
 783 }
 784 
 785 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
 786 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK                         0x0000ffff
 787 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT                        0
 788 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
 789 {
 790         return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
 791 }
 792 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK                         0xffff0000
 793 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT                        16
 794 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
 795 {
 796         return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
 797 }
 798 
 799 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
 800 
 801 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
 802 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK                        0x00000003
 803 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT                       0
 804 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
 805 {
 806         return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
 807 }
 808 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK                        0x0000000c
 809 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT                       2
 810 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
 811 {
 812         return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
 813 }
 814 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK                        0x00000030
 815 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT                       4
 816 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
 817 {
 818         return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
 819 }
 820 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK                        0x000000c0
 821 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT                       6
 822 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
 823 {
 824         return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
 825 }
 826 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE                       0x00000100
 827 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK                          0x00000600
 828 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT                         9
 829 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
 830 {
 831         return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
 832 }
 833 #define MDP5_PIPE_SRC_FORMAT_ROT90                              0x00000800
 834 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK                 0x00003000
 835 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT                12
 836 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
 837 {
 838         return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
 839 }
 840 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT                       0x00020000
 841 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB                   0x00040000
 842 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK                   0x00180000
 843 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT                  19
 844 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
 845 {
 846         return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
 847 }
 848 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK                  0x01800000
 849 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT                 23
 850 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
 851 {
 852         return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
 853 }
 854 
 855 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
 856 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK                        0x000000ff
 857 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT                       0
 858 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
 859 {
 860         return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
 861 }
 862 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK                        0x0000ff00
 863 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT                       8
 864 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
 865 {
 866         return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
 867 }
 868 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK                        0x00ff0000
 869 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT                       16
 870 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
 871 {
 872         return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
 873 }
 874 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK                        0xff000000
 875 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT                       24
 876 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
 877 {
 878         return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
 879 }
 880 
 881 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
 882 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN                            0x00000001
 883 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK                         0x00000006
 884 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT                        1
 885 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
 886 {
 887         return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
 888 }
 889 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR                           0x00002000
 890 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD                           0x00004000
 891 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN                            0x00010000
 892 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0                         0x00020000
 893 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1                         0x00040000
 894 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE                       0x00400000
 895 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD                   0x00800000
 896 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE               0x80000000
 897 
 898 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
 899 
 900 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
 901 
 902 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
 903 
 904 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
 905 
 906 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
 907 
 908 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
 909 
 910 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
 911 
 912 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
 913 
 914 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
 915 
 916 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
 917 
 918 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
 919 
 920 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
 921 #define MDP5_PIPE_DECIMATION_VERT__MASK                         0x000000ff
 922 #define MDP5_PIPE_DECIMATION_VERT__SHIFT                        0
 923 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
 924 {
 925         return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
 926 }
 927 #define MDP5_PIPE_DECIMATION_HORZ__MASK                         0x0000ff00
 928 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT                        8
 929 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
 930 {
 931         return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
 932 }
 933 
 934 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
 935 {
 936         switch (idx) {
 937                 case COMP_0: return 0x00000100;
 938                 case COMP_1_2: return 0x00000110;
 939                 case COMP_3: return 0x00000120;
 940                 default: return INVALID_IDX(idx);
 941         }
 942 }
 943 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
 944 
 945 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
 946 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK                  0x000000ff
 947 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT                 0
 948 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
 949 {
 950         return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
 951 }
 952 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK                  0x0000ff00
 953 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT                 8
 954 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
 955 {
 956         return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
 957 }
 958 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK                 0x00ff0000
 959 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT                16
 960 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
 961 {
 962         return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
 963 }
 964 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK                 0xff000000
 965 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT                24
 966 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
 967 {
 968         return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
 969 }
 970 
 971 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
 972 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK                   0x000000ff
 973 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT                  0
 974 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
 975 {
 976         return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
 977 }
 978 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK                   0x0000ff00
 979 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT                  8
 980 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
 981 {
 982         return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
 983 }
 984 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK                0x00ff0000
 985 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT               16
 986 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
 987 {
 988         return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
 989 }
 990 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK                0xff000000
 991 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT               24
 992 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
 993 {
 994         return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
 995 }
 996 
 997 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
 998 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK        0x0000ffff
 999 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT       0
1000 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1001 {
1002         return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1003 }
1004 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK        0xffff0000
1005 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT       16
1006 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1007 {
1008         return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1009 }
1010 
1011 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
1012 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN                        0x00000001
1013 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN                        0x00000002
1014 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK       0x00000300
1015 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT      8
1016 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1017 {
1018         return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1019 }
1020 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK       0x00000c00
1021 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT      10
1022 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1023 {
1024         return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1025 }
1026 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK     0x00003000
1027 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT    12
1028 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1029 {
1030         return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1031 }
1032 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK     0x0000c000
1033 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT    14
1034 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1035 {
1036         return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1037 }
1038 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK       0x00030000
1039 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT      16
1040 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1041 {
1042         return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1043 }
1044 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK       0x000c0000
1045 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT      18
1046 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1047 {
1048         return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1049 }
1050 
1051 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1052 
1053 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1054 
1055 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1056 
1057 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1058 
1059 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1060 
1061 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1062 
1063 static inline uint32_t __offset_LM(uint32_t idx)
1064 {
1065         switch (idx) {
1066                 case 0: return (mdp5_cfg->lm.base[0]);
1067                 case 1: return (mdp5_cfg->lm.base[1]);
1068                 case 2: return (mdp5_cfg->lm.base[2]);
1069                 case 3: return (mdp5_cfg->lm.base[3]);
1070                 case 4: return (mdp5_cfg->lm.base[4]);
1071                 case 5: return (mdp5_cfg->lm.base[5]);
1072                 default: return INVALID_IDX(idx);
1073         }
1074 }
1075 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1076 
1077 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1078 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA                 0x00000002
1079 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA                 0x00000004
1080 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA                 0x00000008
1081 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA                 0x00000010
1082 #define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA                 0x00000020
1083 #define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA                 0x00000040
1084 #define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA                 0x00000080
1085 #define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT                0x80000000
1086 
1087 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1088 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK                           0xffff0000
1089 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT                          16
1090 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1091 {
1092         return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1093 }
1094 #define MDP5_LM_OUT_SIZE_WIDTH__MASK                            0x0000ffff
1095 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT                           0
1096 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1097 {
1098         return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1099 }
1100 
1101 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1102 
1103 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1104 
1105 static inline uint32_t __offset_BLEND(uint32_t idx)
1106 {
1107         switch (idx) {
1108                 case 0: return 0x00000020;
1109                 case 1: return 0x00000050;
1110                 case 2: return 0x00000080;
1111                 case 3: return 0x000000b0;
1112                 case 4: return 0x00000230;
1113                 case 5: return 0x00000260;
1114                 case 6: return 0x00000290;
1115                 default: return INVALID_IDX(idx);
1116         }
1117 }
1118 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1119 
1120 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1121 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK                    0x00000003
1122 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT                   0
1123 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1124 {
1125         return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1126 }
1127 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA                      0x00000004
1128 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA                      0x00000008
1129 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA                  0x00000010
1130 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN                      0x00000020
1131 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK                    0x00000300
1132 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT                   8
1133 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1134 {
1135         return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1136 }
1137 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA                      0x00000400
1138 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA                      0x00000800
1139 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA                  0x00001000
1140 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN                      0x00002000
1141 
1142 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1143 
1144 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1145 
1146 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1147 
1148 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1149 
1150 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1151 
1152 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1153 
1154 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1155 
1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1157 
1158 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1159 
1160 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1161 
1162 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1163 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK                     0x0000ffff
1164 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT                    0
1165 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1166 {
1167         return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1168 }
1169 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK                     0xffff0000
1170 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT                    16
1171 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1172 {
1173         return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1174 }
1175 
1176 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1177 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK                         0x0000ffff
1178 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT                        0
1179 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1180 {
1181         return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1182 }
1183 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK                         0xffff0000
1184 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT                        16
1185 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1186 {
1187         return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1188 }
1189 
1190 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1191 #define MDP5_LM_CURSOR_XY_SRC_X__MASK                           0x0000ffff
1192 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT                          0
1193 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1194 {
1195         return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1196 }
1197 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK                           0xffff0000
1198 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT                          16
1199 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1200 {
1201         return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1202 }
1203 
1204 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1205 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK                      0x0000ffff
1206 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT                     0
1207 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1208 {
1209         return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1210 }
1211 
1212 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1213 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK                      0x00000007
1214 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT                     0
1215 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1216 {
1217         return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1218 }
1219 
1220 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1221 
1222 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1223 #define MDP5_LM_CURSOR_START_XY_X_START__MASK                   0x0000ffff
1224 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT                  0
1225 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1226 {
1227         return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1228 }
1229 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK                   0xffff0000
1230 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT                  16
1231 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1232 {
1233         return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1234 }
1235 
1236 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1237 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN                    0x00000001
1238 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK       0x00000006
1239 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT      1
1240 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1241 {
1242         return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1243 }
1244 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN             0x00000008
1245 
1246 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1247 
1248 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1249 
1250 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1251 
1252 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1253 
1254 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1255 
1256 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1257 
1258 static inline uint32_t __offset_DSPP(uint32_t idx)
1259 {
1260         switch (idx) {
1261                 case 0: return (mdp5_cfg->dspp.base[0]);
1262                 case 1: return (mdp5_cfg->dspp.base[1]);
1263                 case 2: return (mdp5_cfg->dspp.base[2]);
1264                 case 3: return (mdp5_cfg->dspp.base[3]);
1265                 default: return INVALID_IDX(idx);
1266         }
1267 }
1268 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1269 
1270 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1271 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN                            0x00000001
1272 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK                     0x0000000e
1273 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT                    1
1274 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1275 {
1276         return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1277 }
1278 #define MDP5_DSPP_OP_MODE_PCC_EN                                0x00000010
1279 #define MDP5_DSPP_OP_MODE_DITHER_EN                             0x00000100
1280 #define MDP5_DSPP_OP_MODE_HIST_EN                               0x00010000
1281 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR                            0x00020000
1282 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN                           0x00080000
1283 #define MDP5_DSPP_OP_MODE_PA_EN                                 0x00100000
1284 #define MDP5_DSPP_OP_MODE_GAMUT_EN                              0x00800000
1285 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER                           0x01000000
1286 
1287 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1288 
1289 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1290 
1291 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1292 
1293 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1294 
1295 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1296 
1297 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1298 
1299 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1300 
1301 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1302 
1303 static inline uint32_t __offset_PP(uint32_t idx)
1304 {
1305         switch (idx) {
1306                 case 0: return (mdp5_cfg->pp.base[0]);
1307                 case 1: return (mdp5_cfg->pp.base[1]);
1308                 case 2: return (mdp5_cfg->pp.base[2]);
1309                 case 3: return (mdp5_cfg->pp.base[3]);
1310                 default: return INVALID_IDX(idx);
1311         }
1312 }
1313 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1314 
1315 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1316 
1317 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1318 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK                   0x0007ffff
1319 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT                  0
1320 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1321 {
1322         return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1323 }
1324 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN                    0x00080000
1325 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN                         0x00100000
1326 
1327 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1328 
1329 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1330 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK                   0x0000ffff
1331 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT                  0
1332 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1333 {
1334         return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1335 }
1336 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK                  0xffff0000
1337 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT                 16
1338 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1339 {
1340         return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1341 }
1342 
1343 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1344 
1345 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1346 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK                  0x0000ffff
1347 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT                 0
1348 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1349 {
1350         return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1351 }
1352 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK                 0xffff0000
1353 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT                16
1354 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1355 {
1356         return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1357 }
1358 
1359 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1360 #define MDP5_PP_SYNC_THRESH_START__MASK                         0x0000ffff
1361 #define MDP5_PP_SYNC_THRESH_START__SHIFT                        0
1362 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1363 {
1364         return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1365 }
1366 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK                      0xffff0000
1367 #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT                     16
1368 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1369 {
1370         return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1371 }
1372 
1373 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1374 
1375 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1376 
1377 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1378 
1379 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1380 
1381 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1382 
1383 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1384 
1385 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1386 
1387 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1388 
1389 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1390 
1391 static inline uint32_t __offset_WB(uint32_t idx)
1392 {
1393         switch (idx) {
1394 #if 0  /* TEMPORARY until patch that adds wb.base[] is merged */
1395                 case 0: return (mdp5_cfg->wb.base[0]);
1396                 case 1: return (mdp5_cfg->wb.base[1]);
1397                 case 2: return (mdp5_cfg->wb.base[2]);
1398                 case 3: return (mdp5_cfg->wb.base[3]);
1399                 case 4: return (mdp5_cfg->wb.base[4]);
1400 #endif
1401                 default: return INVALID_IDX(idx);
1402         }
1403 }
1404 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1405 
1406 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1407 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK                      0x00000003
1408 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT                     0
1409 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1410 {
1411         return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1412 }
1413 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK                      0x0000000c
1414 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT                     2
1415 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1416 {
1417         return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1418 }
1419 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK                      0x00000030
1420 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT                     4
1421 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1422 {
1423         return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1424 }
1425 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK                      0x000000c0
1426 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT                     6
1427 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1428 {
1429         return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1430 }
1431 #define MDP5_WB_DST_FORMAT_DSTC3_EN                             0x00000100
1432 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK                        0x00000600
1433 #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT                       9
1434 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1435 {
1436         return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1437 }
1438 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK                     0x00003000
1439 #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT                    12
1440 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1441 {
1442         return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1443 }
1444 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X                          0x00004000
1445 #define MDP5_WB_DST_FORMAT_PACK_TIGHT                           0x00020000
1446 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB                       0x00040000
1447 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK                   0x00180000
1448 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT                  19
1449 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1450 {
1451         return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1452 }
1453 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN                        0x00400000
1454 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK                0x03800000
1455 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT               23
1456 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1457 {
1458         return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1459 }
1460 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK                0x3c000000
1461 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT               26
1462 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1463 {
1464         return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1465 }
1466 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK                   0xc0000000
1467 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT                  30
1468 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1469 {
1470         return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1471 }
1472 
1473 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1474 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN                          0x00000001
1475 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK                    0x00000006
1476 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT                   1
1477 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1478 {
1479         return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1480 }
1481 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK                    0x00000010
1482 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT                   4
1483 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1484 {
1485         return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1486 }
1487 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK                      0x00000020
1488 #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT                     5
1489 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1490 {
1491         return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1492 }
1493 #define MDP5_WB_DST_OP_MODE_ROT_EN                              0x00000040
1494 #define MDP5_WB_DST_OP_MODE_CSC_EN                              0x00000100
1495 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK           0x00000200
1496 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT          9
1497 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1498 {
1499         return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1500 }
1501 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK           0x00000400
1502 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT          10
1503 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1504 {
1505         return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1506 }
1507 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN                0x00000800
1508 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK      0x00001000
1509 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT     12
1510 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1511 {
1512         return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1513 }
1514 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK      0x00002000
1515 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT     13
1516 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1517 {
1518         return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1519 }
1520 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK      0x00004000
1521 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT     14
1522 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1523 {
1524         return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1525 }
1526 
1527 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1528 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK                 0x00000003
1529 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT                0
1530 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1531 {
1532         return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1533 }
1534 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK                 0x00000300
1535 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT                8
1536 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1537 {
1538         return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1539 }
1540 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK                 0x00030000
1541 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT                16
1542 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1543 {
1544         return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1545 }
1546 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK                 0x03000000
1547 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT                24
1548 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1549 {
1550         return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1551 }
1552 
1553 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1554 
1555 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1556 
1557 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1558 
1559 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1560 
1561 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1562 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK                 0x0000ffff
1563 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT                0
1564 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1565 {
1566         return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1567 }
1568 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK                 0xffff0000
1569 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT                16
1570 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1571 {
1572         return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1573 }
1574 
1575 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1576 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK                 0x0000ffff
1577 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT                0
1578 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1579 {
1580         return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1581 }
1582 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK                 0xffff0000
1583 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT                16
1584 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1585 {
1586         return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1587 }
1588 
1589 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1590 
1591 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1592 
1593 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1594 
1595 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1596 
1597 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1598 
1599 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1600 
1601 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1602 
1603 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1604 
1605 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1606 
1607 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1608 
1609 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1610 
1611 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1612 #define MDP5_WB_OUT_SIZE_DST_W__MASK                            0x0000ffff
1613 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT                           0
1614 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1615 {
1616         return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1617 }
1618 #define MDP5_WB_OUT_SIZE_DST_H__MASK                            0xffff0000
1619 #define MDP5_WB_OUT_SIZE_DST_H__SHIFT                           16
1620 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1621 {
1622         return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1623 }
1624 
1625 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1626 
1627 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1628 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK               0x00001fff
1629 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT              0
1630 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1631 {
1632         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1633 }
1634 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK               0x1fff0000
1635 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT              16
1636 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1637 {
1638         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1639 }
1640 
1641 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1642 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK               0x00001fff
1643 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT              0
1644 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1645 {
1646         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1647 }
1648 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK               0x1fff0000
1649 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT              16
1650 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1651 {
1652         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1653 }
1654 
1655 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1656 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK               0x00001fff
1657 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT              0
1658 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1659 {
1660         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1661 }
1662 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK               0x1fff0000
1663 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT              16
1664 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1665 {
1666         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1667 }
1668 
1669 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1670 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK               0x00001fff
1671 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT              0
1672 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1673 {
1674         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1675 }
1676 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK               0x1fff0000
1677 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT              16
1678 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1679 {
1680         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1681 }
1682 
1683 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1684 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK               0x00001fff
1685 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT              0
1686 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1687 {
1688         return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1689 }
1690 
1691 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1692 
1693 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1694 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK                0x000000ff
1695 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT               0
1696 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1697 {
1698         return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1699 }
1700 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK                 0x0000ff00
1701 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT                8
1702 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1703 {
1704         return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1705 }
1706 
1707 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1708 
1709 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1710 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK               0x000000ff
1711 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT              0
1712 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1713 {
1714         return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1715 }
1716 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK                0x0000ff00
1717 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT               8
1718 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1719 {
1720         return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1721 }
1722 
1723 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1724 
1725 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1726 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK                0x000001ff
1727 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT               0
1728 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1729 {
1730         return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1731 }
1732 
1733 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1734 
1735 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1736 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK               0x000001ff
1737 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT              0
1738 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1739 {
1740         return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1741 }
1742 
1743 static inline uint32_t __offset_INTF(uint32_t idx)
1744 {
1745         switch (idx) {
1746                 case 0: return (mdp5_cfg->intf.base[0]);
1747                 case 1: return (mdp5_cfg->intf.base[1]);
1748                 case 2: return (mdp5_cfg->intf.base[2]);
1749                 case 3: return (mdp5_cfg->intf.base[3]);
1750                 case 4: return (mdp5_cfg->intf.base[4]);
1751                 default: return INVALID_IDX(idx);
1752         }
1753 }
1754 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1755 
1756 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1757 
1758 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1759 
1760 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1761 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK                        0x0000ffff
1762 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT                       0
1763 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1764 {
1765         return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1766 }
1767 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK                        0xffff0000
1768 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT                       16
1769 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1770 {
1771         return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1772 }
1773 
1774 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1775 
1776 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1777 
1778 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1779 
1780 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1781 
1782 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1783 
1784 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1785 
1786 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1787 
1788 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1789 
1790 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1791 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK                    0x7fffffff
1792 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT                   0
1793 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1794 {
1795         return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1796 }
1797 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE              0x80000000
1798 
1799 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1800 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK                    0x7fffffff
1801 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT                   0
1802 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1803 {
1804         return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1805 }
1806 
1807 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1808 
1809 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1810 
1811 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1812 #define MDP5_INTF_DISPLAY_HCTL_START__MASK                      0x0000ffff
1813 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT                     0
1814 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1815 {
1816         return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1817 }
1818 #define MDP5_INTF_DISPLAY_HCTL_END__MASK                        0xffff0000
1819 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT                       16
1820 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1821 {
1822         return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1823 }
1824 
1825 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1826 #define MDP5_INTF_ACTIVE_HCTL_START__MASK                       0x00007fff
1827 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT                      0
1828 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1829 {
1830         return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1831 }
1832 #define MDP5_INTF_ACTIVE_HCTL_END__MASK                         0x7fff0000
1833 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT                        16
1834 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1835 {
1836         return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1837 }
1838 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE                   0x80000000
1839 
1840 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1841 
1842 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1843 
1844 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1845 
1846 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1847 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW                        0x00000001
1848 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW                        0x00000002
1849 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW                      0x00000004
1850 
1851 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1852 
1853 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1854 
1855 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1856 
1857 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1858 
1859 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1860 
1861 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1862 
1863 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1864 
1865 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1866 
1867 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1868 
1869 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1870 
1871 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1872 
1873 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1874 
1875 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1876 
1877 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1878 
1879 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1880 
1881 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1882 
1883 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1884 
1885 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1886 
1887 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1888 
1889 static inline uint32_t __offset_AD(uint32_t idx)
1890 {
1891         switch (idx) {
1892                 case 0: return (mdp5_cfg->ad.base[0]);
1893                 case 1: return (mdp5_cfg->ad.base[1]);
1894                 default: return INVALID_IDX(idx);
1895         }
1896 }
1897 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1898 
1899 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1900 
1901 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1902 
1903 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1904 
1905 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1906 
1907 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1908 
1909 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1910 
1911 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1912 
1913 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1914 
1915 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1916 
1917 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1918 
1919 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1920 
1921 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1922 
1923 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1924 
1925 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1926 
1927 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1928 
1929 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1930 
1931 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1932 
1933 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1934 
1935 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1936 
1937 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1938 
1939 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1940 
1941 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1942 
1943 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1944 
1945 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1946 
1947 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1948 
1949 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1950 
1951 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1952 
1953 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1954 
1955 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1956 
1957 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1958 
1959 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1960 
1961 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1962 
1963 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1964 
1965 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1966 
1967 
1968 #endif /* MDP5_XML */