root/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

DEFINITIONS

1. get_kms
2. request_pending
3. crtc_flush
4. complete_flip
5. unref_cursor_worker
6. mdp4_crtc_destroy
7. setup_mixer
8. blend_setup
9. mdp4_crtc_mode_set_nofb
10. mdp4_crtc_atomic_disable
11. mdp4_crtc_atomic_enable
12. mdp4_crtc_atomic_check
13. mdp4_crtc_atomic_begin
14. mdp4_crtc_atomic_flush
15. update_cursor
16. mdp4_crtc_cursor_set
17. mdp4_crtc_cursor_move
18. mdp4_crtc_vblank_irq
19. mdp4_crtc_err_irq
20. mdp4_crtc_wait_for_flush_done
21. mdp4_crtc_vblank
22. mdp4_crtc_set_config
23. mdp4_crtc_set_intf
24. mdp4_crtc_wait_for_commit_done
25. mdp4_crtc_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6 
   7 #include <drm/drm_crtc.h>
   8 #include <drm/drm_flip_work.h>
   9 #include <drm/drm_mode.h>
  10 #include <drm/drm_probe_helper.h>
  11 #include <drm/drm_vblank.h>
  12 
  13 #include "mdp4_kms.h"
  14 
  15 struct mdp4_crtc {
  16         struct drm_crtc base;
  17         char name[8];
  18         int id;
  19         int ovlp;
  20         enum mdp4_dma dma;
  21         bool enabled;
  22 
  23         /* which mixer/encoder we route output to: */
  24         int mixer;
  25 
  26         struct {
  27                 spinlock_t lock;
  28                 bool stale;
  29                 uint32_t width, height;
  30                 uint32_t x, y;
  31 
  32                 /* next cursor to scan-out: */
  33                 uint32_t next_iova;
  34                 struct drm_gem_object *next_bo;
  35 
  36                 /* current cursor being scanned out: */
  37                 struct drm_gem_object *scanout_bo;
  38         } cursor;
  39 
  40 
  41         /* if there is a pending flip, these will be non-null: */
  42         struct drm_pending_vblank_event *event;
  43 
  44         /* Bits have been flushed at the last commit,
  45          * used to decide if a vsync has happened since last commit.
  46          */
  47         u32 flushed_mask;
  48 
  49 #define PENDING_CURSOR 0x1
  50 #define PENDING_FLIP   0x2
  51         atomic_t pending;
  52 
  53         /* for unref'ing cursor bo's after scanout completes: */
  54         struct drm_flip_work unref_cursor_work;
  55 
  56         struct mdp_irq vblank;
  57         struct mdp_irq err;
  58 };
  59 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
  60 
  61 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
  62 {
  63         struct msm_drm_private *priv = crtc->dev->dev_private;
  64         return to_mdp4_kms(to_mdp_kms(priv->kms));
  65 }
  66 
  67 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  68 {
  69         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  70 
  71         atomic_or(pending, &mdp4_crtc->pending);
  72         mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
  73 }
  74 
  75 static void crtc_flush(struct drm_crtc *crtc)
  76 {
  77         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  78         struct mdp4_kms *mdp4_kms = get_kms(crtc);
  79         struct drm_plane *plane;
  80         uint32_t flush = 0;
  81 
  82         drm_atomic_crtc_for_each_plane(plane, crtc) {
  83                 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
  84                 flush |= pipe2flush(pipe_id);
  85         }
  86 
  87         flush |= ovlp2flush(mdp4_crtc->ovlp);
  88 
  89         DBG("%s: flush=%08x", mdp4_crtc->name, flush);
  90 
  91         mdp4_crtc->flushed_mask = flush;
  92 
  93         mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
  94 }
  95 
  96 /* if file!=NULL, this is preclose potential cancel-flip path */
  97 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
  98 {
  99         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 100         struct drm_device *dev = crtc->dev;
 101         struct drm_pending_vblank_event *event;
 102         unsigned long flags;
 103 
 104         spin_lock_irqsave(&dev->event_lock, flags);
 105         event = mdp4_crtc->event;
 106         if (event) {
 107                 mdp4_crtc->event = NULL;
 108                 DBG("%s: send event: %p", mdp4_crtc->name, event);
 109                 drm_crtc_send_vblank_event(crtc, event);
 110         }
 111         spin_unlock_irqrestore(&dev->event_lock, flags);
 112 }
 113 
 114 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 115 {
 116         struct mdp4_crtc *mdp4_crtc =
 117                 container_of(work, struct mdp4_crtc, unref_cursor_work);
 118         struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
 119         struct msm_kms *kms = &mdp4_kms->base.base;
 120 
 121         msm_gem_unpin_iova(val, kms->aspace);
 122         drm_gem_object_put_unlocked(val);
 123 }
 124 
 125 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
 126 {
 127         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 128 
 129         drm_crtc_cleanup(crtc);
 130         drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
 131 
 132         kfree(mdp4_crtc);
 133 }
 134 
 135 /* statically (for now) map planes to mixer stage (z-order): */
 136 static const int idxs[] = {
 137                 [VG1]  = 1,
 138                 [VG2]  = 2,
 139                 [RGB1] = 0,
 140                 [RGB2] = 0,
 141                 [RGB3] = 0,
 142                 [VG3]  = 3,
 143                 [VG4]  = 4,
 144 
 145 };
 146 
 147 /* setup mixer config, for which we need to consider all crtc's and
 148  * the planes attached to them
 149  *
 150  * TODO may possibly need some extra locking here
 151  */
 152 static void setup_mixer(struct mdp4_kms *mdp4_kms)
 153 {
 154         struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
 155         struct drm_crtc *crtc;
 156         uint32_t mixer_cfg = 0;
 157         static const enum mdp_mixer_stage_id stages[] = {
 158                         STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
 159         };
 160 
 161         list_for_each_entry(crtc, &config->crtc_list, head) {
 162                 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 163                 struct drm_plane *plane;
 164 
 165                 drm_atomic_crtc_for_each_plane(plane, crtc) {
 166                         enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
 167                         int idx = idxs[pipe_id];
 168                         mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
 169                                         pipe_id, stages[idx]);
 170                 }
 171         }
 172 
 173         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
 174 }
 175 
 176 static void blend_setup(struct drm_crtc *crtc)
 177 {
 178         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 179         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 180         struct drm_plane *plane;
 181         int i, ovlp = mdp4_crtc->ovlp;
 182         bool alpha[4]= { false, false, false, false };
 183 
 184         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
 185         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
 186         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
 187         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
 188 
 189         drm_atomic_crtc_for_each_plane(plane, crtc) {
 190                 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
 191                 int idx = idxs[pipe_id];
 192                 if (idx > 0) {
 193                         const struct mdp_format *format =
 194                                         to_mdp_format(msm_framebuffer_format(plane->state->fb));
 195                         alpha[idx-1] = format->alpha_enable;
 196                 }
 197         }
 198 
 199         for (i = 0; i < 4; i++) {
 200                 uint32_t op;
 201 
 202                 if (alpha[i]) {
 203                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
 204                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
 205                                         MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
 206                 } else {
 207                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
 208                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
 209                 }
 210 
 211                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
 212                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
 213                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
 214                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
 215                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
 216                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
 217                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
 218                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
 219         }
 220 
 221         setup_mixer(mdp4_kms);
 222 }
 223 
 224 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 225 {
 226         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 227         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 228         enum mdp4_dma dma = mdp4_crtc->dma;
 229         int ovlp = mdp4_crtc->ovlp;
 230         struct drm_display_mode *mode;
 231 
 232         if (WARN_ON(!crtc->state))
 233                 return;
 234 
 235         mode = &crtc->state->adjusted_mode;
 236 
 237         DBG("%s: set mode: " DRM_MODE_FMT,
 238                         mdp4_crtc->name, DRM_MODE_ARG(mode));
 239 
 240         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
 241                         MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
 242                         MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
 243 
 244         /* take data from pipe: */
 245         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
 246         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
 247         mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
 248                         MDP4_DMA_DST_SIZE_WIDTH(0) |
 249                         MDP4_DMA_DST_SIZE_HEIGHT(0));
 250 
 251         mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
 252         mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
 253                         MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
 254                         MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
 255         mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
 256 
 257         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
 258 
 259         if (dma == DMA_E) {
 260                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
 261                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
 262                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
 263         }
 264 }
 265 
 266 static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
 267                                      struct drm_crtc_state *old_state)
 268 {
 269         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 270         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 271 
 272         DBG("%s", mdp4_crtc->name);
 273 
 274         if (WARN_ON(!mdp4_crtc->enabled))
 275                 return;
 276 
 277         /* Disable/save vblank irq handling before power is disabled */
 278         drm_crtc_vblank_off(crtc);
 279 
 280         mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
 281         mdp4_disable(mdp4_kms);
 282 
 283         mdp4_crtc->enabled = false;
 284 }
 285 
 286 static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
 287                                     struct drm_crtc_state *old_state)
 288 {
 289         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 290         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 291 
 292         DBG("%s", mdp4_crtc->name);
 293 
 294         if (WARN_ON(mdp4_crtc->enabled))
 295                 return;
 296 
 297         mdp4_enable(mdp4_kms);
 298 
 299         /* Restore vblank irq handling after power is enabled */
 300         drm_crtc_vblank_on(crtc);
 301 
 302         mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
 303 
 304         crtc_flush(crtc);
 305 
 306         mdp4_crtc->enabled = true;
 307 }
 308 
 309 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
 310                 struct drm_crtc_state *state)
 311 {
 312         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 313         DBG("%s: check", mdp4_crtc->name);
 314         // TODO anything else to check?
 315         return 0;
 316 }
 317 
 318 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
 319                                    struct drm_crtc_state *old_crtc_state)
 320 {
 321         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 322         DBG("%s: begin", mdp4_crtc->name);
 323 }
 324 
 325 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
 326                                    struct drm_crtc_state *old_crtc_state)
 327 {
 328         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 329         struct drm_device *dev = crtc->dev;
 330         unsigned long flags;
 331 
 332         DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
 333 
 334         WARN_ON(mdp4_crtc->event);
 335 
 336         spin_lock_irqsave(&dev->event_lock, flags);
 337         mdp4_crtc->event = crtc->state->event;
 338         crtc->state->event = NULL;
 339         spin_unlock_irqrestore(&dev->event_lock, flags);
 340 
 341         blend_setup(crtc);
 342         crtc_flush(crtc);
 343         request_pending(crtc, PENDING_FLIP);
 344 }
 345 
 346 #define CURSOR_WIDTH 64
 347 #define CURSOR_HEIGHT 64
 348 
 349 /* called from IRQ to update cursor related registers (if needed).  The
 350  * cursor registers, other than x/y position, appear not to be double
 351  * buffered, and changing them other than from vblank seems to trigger
 352  * underflow.
 353  */
 354 static void update_cursor(struct drm_crtc *crtc)
 355 {
 356         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 357         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 358         struct msm_kms *kms = &mdp4_kms->base.base;
 359         enum mdp4_dma dma = mdp4_crtc->dma;
 360         unsigned long flags;
 361 
 362         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 363         if (mdp4_crtc->cursor.stale) {
 364                 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
 365                 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
 366                 uint64_t iova = mdp4_crtc->cursor.next_iova;
 367 
 368                 if (next_bo) {
 369                         /* take a obj ref + iova ref when we start scanning out: */
 370                         drm_gem_object_get(next_bo);
 371                         msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova);
 372 
 373                         /* enable cursor: */
 374                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
 375                                         MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
 376                                         MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
 377                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
 378                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
 379                                         MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
 380                                         MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
 381                 } else {
 382                         /* disable cursor: */
 383                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
 384                                         mdp4_kms->blank_cursor_iova);
 385                 }
 386 
 387                 /* and drop the iova ref + obj rev when done scanning out: */
 388                 if (prev_bo)
 389                         drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
 390 
 391                 mdp4_crtc->cursor.scanout_bo = next_bo;
 392                 mdp4_crtc->cursor.stale = false;
 393         }
 394 
 395         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
 396                         MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
 397                         MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
 398 
 399         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 400 }
 401 
 402 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
 403                 struct drm_file *file_priv, uint32_t handle,
 404                 uint32_t width, uint32_t height)
 405 {
 406         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 407         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 408         struct msm_kms *kms = &mdp4_kms->base.base;
 409         struct drm_device *dev = crtc->dev;
 410         struct drm_gem_object *cursor_bo, *old_bo;
 411         unsigned long flags;
 412         uint64_t iova;
 413         int ret;
 414 
 415         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 416                 DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
 417                 return -EINVAL;
 418         }
 419 
 420         if (handle) {
 421                 cursor_bo = drm_gem_object_lookup(file_priv, handle);
 422                 if (!cursor_bo)
 423                         return -ENOENT;
 424         } else {
 425                 cursor_bo = NULL;
 426         }
 427 
 428         if (cursor_bo) {
 429                 ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova);
 430                 if (ret)
 431                         goto fail;
 432         } else {
 433                 iova = 0;
 434         }
 435 
 436         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 437         old_bo = mdp4_crtc->cursor.next_bo;
 438         mdp4_crtc->cursor.next_bo   = cursor_bo;
 439         mdp4_crtc->cursor.next_iova = iova;
 440         mdp4_crtc->cursor.width     = width;
 441         mdp4_crtc->cursor.height    = height;
 442         mdp4_crtc->cursor.stale     = true;
 443         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 444 
 445         if (old_bo) {
 446                 /* drop our previous reference: */
 447                 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
 448         }
 449 
 450         request_pending(crtc, PENDING_CURSOR);
 451 
 452         return 0;
 453 
 454 fail:
 455         drm_gem_object_put_unlocked(cursor_bo);
 456         return ret;
 457 }
 458 
 459 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 460 {
 461         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 462         unsigned long flags;
 463 
 464         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 465         mdp4_crtc->cursor.x = x;
 466         mdp4_crtc->cursor.y = y;
 467         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 468 
 469         crtc_flush(crtc);
 470         request_pending(crtc, PENDING_CURSOR);
 471 
 472         return 0;
 473 }
 474 
 475 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
 476         .set_config = drm_atomic_helper_set_config,
 477         .destroy = mdp4_crtc_destroy,
 478         .page_flip = drm_atomic_helper_page_flip,
 479         .cursor_set = mdp4_crtc_cursor_set,
 480         .cursor_move = mdp4_crtc_cursor_move,
 481         .reset = drm_atomic_helper_crtc_reset,
 482         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 483         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 484 };
 485 
 486 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
 487         .mode_set_nofb = mdp4_crtc_mode_set_nofb,
 488         .atomic_check = mdp4_crtc_atomic_check,
 489         .atomic_begin = mdp4_crtc_atomic_begin,
 490         .atomic_flush = mdp4_crtc_atomic_flush,
 491         .atomic_enable = mdp4_crtc_atomic_enable,
 492         .atomic_disable = mdp4_crtc_atomic_disable,
 493 };
 494 
 495 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 496 {
 497         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
 498         struct drm_crtc *crtc = &mdp4_crtc->base;
 499         struct msm_drm_private *priv = crtc->dev->dev_private;
 500         unsigned pending;
 501 
 502         mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
 503 
 504         pending = atomic_xchg(&mdp4_crtc->pending, 0);
 505 
 506         if (pending & PENDING_FLIP) {
 507                 complete_flip(crtc, NULL);
 508         }
 509 
 510         if (pending & PENDING_CURSOR) {
 511                 update_cursor(crtc);
 512                 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
 513         }
 514 }
 515 
 516 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 517 {
 518         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
 519         struct drm_crtc *crtc = &mdp4_crtc->base;
 520         DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
 521         crtc_flush(crtc);
 522 }
 523 
 524 static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 528         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 529         int ret;
 530 
 531         ret = drm_crtc_vblank_get(crtc);
 532         if (ret)
 533                 return;
 534 
 535         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
 536                 !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
 537                         mdp4_crtc->flushed_mask),
 538                 msecs_to_jiffies(50));
 539         if (ret <= 0)
 540                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
 541 
 542         mdp4_crtc->flushed_mask = 0;
 543 
 544         drm_crtc_vblank_put(crtc);
 545 }
 546 
 547 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
 548 {
 549         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 550         return mdp4_crtc->vblank.irqmask;
 551 }
 552 
 553 /* set dma config, ie. the format the encoder wants. */
 554 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
 555 {
 556         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 557         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 558 
 559         mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
 560 }
 561 
 562 /* set interface for routing crtc->encoder: */
 563 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
 564 {
 565         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 566         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 567         uint32_t intf_sel;
 568 
 569         intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
 570 
 571         switch (mdp4_crtc->dma) {
 572         case DMA_P:
 573                 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
 574                 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
 575                 break;
 576         case DMA_S:
 577                 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
 578                 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
 579                 break;
 580         case DMA_E:
 581                 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
 582                 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
 583                 break;
 584         }
 585 
 586         if (intf == INTF_DSI_VIDEO) {
 587                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
 588                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
 589         } else if (intf == INTF_DSI_CMD) {
 590                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
 591                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
 592         }
 593 
 594         mdp4_crtc->mixer = mixer;
 595 
 596         blend_setup(crtc);
 597 
 598         DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
 599 
 600         mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
 601 }
 602 
 603 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
 604 {
 605         /* wait_for_flush_done is the only case for now.
 606          * Later we will have command mode CRTC to wait for
 607          * other event.
 608          */
 609         mdp4_crtc_wait_for_flush_done(crtc);
 610 }
 611 
 612 static const char *dma_names[] = {
 613                 "DMA_P", "DMA_S", "DMA_E",
 614 };
 615 
 616 /* initialize crtc */
 617 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
 618                 struct drm_plane *plane, int id, int ovlp_id,
 619                 enum mdp4_dma dma_id)
 620 {
 621         struct drm_crtc *crtc = NULL;
 622         struct mdp4_crtc *mdp4_crtc;
 623 
 624         mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
 625         if (!mdp4_crtc)
 626                 return ERR_PTR(-ENOMEM);
 627 
 628         crtc = &mdp4_crtc->base;
 629 
 630         mdp4_crtc->id = id;
 631 
 632         mdp4_crtc->ovlp = ovlp_id;
 633         mdp4_crtc->dma = dma_id;
 634 
 635         mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
 636         mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
 637 
 638         mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
 639         mdp4_crtc->err.irq = mdp4_crtc_err_irq;
 640 
 641         snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
 642                         dma_names[dma_id], ovlp_id);
 643 
 644         spin_lock_init(&mdp4_crtc->cursor.lock);
 645 
 646         drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
 647                         "unref cursor", unref_cursor_worker);
 648 
 649         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
 650                                   NULL);
 651         drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
 652 
 653         return crtc;
 654 }