drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
pll_28nm_poll_for_ready
dsi_pll_28nm_clk_set_rate
dsi_pll_28nm_clk_is_enabled
dsi_pll_28nm_clk_recalc_rate
clk_bytediv_recalc_rate
get_vco_mul_factor
clk_bytediv_round_rate
clk_bytediv_set_rate
dsi_pll_28nm_enable_seq
dsi_pll_28nm_disable_seq
dsi_pll_28nm_save_state
dsi_pll_28nm_restore_state
dsi_pll_28nm_get_provider
dsi_pll_28nm_destroy
pll_28nm_register
msm_dsi_pll_28nm_8960_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
   4  */
   5 
   6 #include <linux/clk-provider.h>
   7 
   8 #include "dsi_pll.h"
   9 #include "dsi.xml.h"
  10 
  11 /*
  12  * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):
  13  *
  14  *
  15  *                        +------+
  16  *  dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock)
  17  *  F * byte_clk    |     +------+
  18  *                  | bit clock divider (F / 8)
  19  *                  |
  20  *                  |     +------+
  21  *                  o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG
  22  *                  |     +------+                 | (sets parent rate)
  23  *                  | byte clock divider (F)       |
  24  *                  |                              |
  25  *                  |                              o---> To esc RCG
  26  *                  |                                (doesn't set parent rate)
  27  *                  |
  28  *                  |     +------+
  29  *                  o-----| DIV3 |----dsi0pll------o---> To dsi RCG
  30  *                        +------+                 | (sets parent rate)
  31  *                  dsi clock divider (F * magic)  |
  32  *                                                 |
  33  *                                                 o---> To pixel rcg
  34  *                                                  (doesn't set parent rate)
  35  */
  36 
  37 #define POLL_MAX_READS          8000
  38 #define POLL_TIMEOUT_US         1
  39 
  40 #define NUM_PROVIDED_CLKS       2
  41 
  42 #define VCO_REF_CLK_RATE        27000000
  43 #define VCO_MIN_RATE            600000000
  44 #define VCO_MAX_RATE            1200000000
  45 
  46 #define DSI_BYTE_PLL_CLK        0
  47 #define DSI_PIXEL_PLL_CLK       1
  48 
  49 #define VCO_PREF_DIV_RATIO      27
  50 
  51 struct pll_28nm_cached_state {
  52         unsigned long vco_rate;
  53         u8 postdiv3;
  54         u8 postdiv2;
  55         u8 postdiv1;
  56 };
  57 
  58 struct clk_bytediv {
  59         struct clk_hw hw;
  60         void __iomem *reg;
  61 };
  62 
  63 struct dsi_pll_28nm {
  64         struct msm_dsi_pll base;
  65 
  66         int id;
  67         struct platform_device *pdev;
  68         void __iomem *mmio;
  69 
  70         /* custom byte clock divider */
  71         struct clk_bytediv *bytediv;
  72 
  73         /* private clocks: */
  74         struct clk *clks[NUM_DSI_CLOCKS_MAX];
  75         u32 num_clks;
  76 
  77         /* clock-provider: */
  78         struct clk *provided_clks[NUM_PROVIDED_CLKS];
  79         struct clk_onecell_data clk_data;
  80 
  81         struct pll_28nm_cached_state cached_state;
  82 };
  83 
  84 #define to_pll_28nm(x)  container_of(x, struct dsi_pll_28nm, base)
  85 
  86 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
  87                                     int nb_tries, int timeout_us)
  88 {
  89         bool pll_locked = false;
  90         u32 val;
  91 
  92         while (nb_tries--) {
  93                 val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
  94                 pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
  95 
  96                 if (pll_locked)
  97                         break;
  98 
  99                 udelay(timeout_us);
 100         }
 101         DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
 102 
 103         return pll_locked;
 104 }
 105 
 106 /*
 107  * Clock Callbacks
 108  */
 109 static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 110                                      unsigned long parent_rate)
 111 {
 112         struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
 113         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 114         void __iomem *base = pll_28nm->mmio;
 115         u32 val, temp, fb_divider;
 116 
 117         DBG("rate=%lu, parent's=%lu", rate, parent_rate);
 118 
 119         temp = rate / 10;
 120         val = VCO_REF_CLK_RATE / 10;
 121         fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
 122         fb_divider = fb_divider / 2 - 1;
 123         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
 124                         fb_divider & 0xff);
 125 
 126         val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
 127 
 128         val |= (fb_divider >> 8) & 0x07;
 129 
 130         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
 131                         val);
 132 
 133         val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
 134 
 135         val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f;
 136 
 137         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
 138                         val);
 139 
 140         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
 141                         0xf);
 142 
 143         val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
 144         val |= 0x7 << 4;
 145         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
 146                         val);
 147 
 148         return 0;
 149 }
 150 
 151 static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
 152 {
 153         struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
 154         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 155 
 156         return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
 157                                         POLL_TIMEOUT_US);
 158 }
 159 
 160 static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
 161                                                   unsigned long parent_rate)
 162 {
 163         struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
 164         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 165         void __iomem *base = pll_28nm->mmio;
 166         unsigned long vco_rate;
 167         u32 status, fb_divider, temp, ref_divider;
 168 
 169         VERB("parent_rate=%lu", parent_rate);
 170 
 171         status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
 172 
 173         if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) {
 174                 fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
 175                 fb_divider &= 0xff;
 176                 temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
 177                 fb_divider = (temp << 8) | fb_divider;
 178                 fb_divider += 1;
 179 
 180                 ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
 181                 ref_divider &= 0x3f;
 182                 ref_divider += 1;
 183 
 184                 /* multiply by 2 */
 185                 vco_rate = (parent_rate / ref_divider) * fb_divider * 2;
 186         } else {
 187                 vco_rate = 0;
 188         }
 189 
 190         DBG("returning vco rate = %lu", vco_rate);
 191 
 192         return vco_rate;
 193 }
 194 
 195 static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
 196         .round_rate = msm_dsi_pll_helper_clk_round_rate,
 197         .set_rate = dsi_pll_28nm_clk_set_rate,
 198         .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
 199         .prepare = msm_dsi_pll_helper_clk_prepare,
 200         .unprepare = msm_dsi_pll_helper_clk_unprepare,
 201         .is_enabled = dsi_pll_28nm_clk_is_enabled,
 202 };
 203 
 204 /*
 205  * Custom byte clock divier clk_ops
 206  *
 207  * This clock is the entry point to configuring the PLL. The user (dsi host)
 208  * will set this clock's rate to the desired byte clock rate. The VCO lock
 209  * frequency is a multiple of the byte clock rate. The multiplication factor
 210  * (shown as F in the diagram above) is a function of the byte clock rate.
 211  *
 212  * This custom divider clock ensures that its parent (VCO) is set to the
 213  * desired rate, and that the byte clock postdivider (POSTDIV2) is configured
 214  * accordingly
 215  */
 216 #define to_clk_bytediv(_hw) container_of(_hw, struct clk_bytediv, hw)
 217 
 218 static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw,
 219                 unsigned long parent_rate)
 220 {
 221         struct clk_bytediv *bytediv = to_clk_bytediv(hw);
 222         unsigned int div;
 223 
 224         div = pll_read(bytediv->reg) & 0xff;
 225 
 226         return parent_rate / (div + 1);
 227 }
 228 
 229 /* find multiplication factor(wrt byte clock) at which the VCO should be set */
 230 static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate)
 231 {
 232         unsigned long bit_mhz;
 233 
 234         /* convert to bit clock in Mhz */
 235         bit_mhz = (byte_clk_rate * 8) / 1000000;
 236 
 237         if (bit_mhz < 125)
 238                 return 64;
 239         else if (bit_mhz < 250)
 240                 return 32;
 241         else if (bit_mhz < 600)
 242                 return 16;
 243         else
 244                 return 8;
 245 }
 246 
 247 static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate,
 248                                    unsigned long *prate)
 249 {
 250         unsigned long best_parent;
 251         unsigned int factor;
 252 
 253         factor = get_vco_mul_factor(rate);
 254 
 255         best_parent = rate * factor;
 256         *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
 257 
 258         return *prate / factor;
 259 }
 260 
 261 static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate,
 262                                 unsigned long parent_rate)
 263 {
 264         struct clk_bytediv *bytediv = to_clk_bytediv(hw);
 265         u32 val;
 266         unsigned int factor;
 267 
 268         factor = get_vco_mul_factor(rate);
 269 
 270         val = pll_read(bytediv->reg);
 271         val |= (factor - 1) & 0xff;
 272         pll_write(bytediv->reg, val);
 273 
 274         return 0;
 275 }
 276 
 277 /* Our special byte clock divider ops */
 278 static const struct clk_ops clk_bytediv_ops = {
 279         .round_rate = clk_bytediv_round_rate,
 280         .set_rate = clk_bytediv_set_rate,
 281         .recalc_rate = clk_bytediv_recalc_rate,
 282 };
 283 
 284 /*
 285  * PLL Callbacks
 286  */
 287 static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll)
 288 {
 289         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 290         struct device *dev = &pll_28nm->pdev->dev;
 291         void __iomem *base = pll_28nm->mmio;
 292         bool locked;
 293         unsigned int bit_div, byte_div;
 294         int max_reads = 1000, timeout_us = 100;
 295         u32 val;
 296 
 297         DBG("id=%d", pll_28nm->id);
 298 
 299         /*
 300          * before enabling the PLL, configure the bit clock divider since we
 301          * don't expose it as a clock to the outside world
 302          * 1: read back the byte clock divider that should already be set
 303          * 2: divide by 8 to get bit clock divider
 304          * 3: write it to POSTDIV1
 305          */
 306         val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
 307         byte_div = val + 1;
 308         bit_div = byte_div / 8;
 309 
 310         val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
 311         val &= ~0xf;
 312         val |= (bit_div - 1);
 313         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
 314 
 315         /* enable the PLL */
 316         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
 317                         DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
 318 
 319         locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
 320 
 321         if (unlikely(!locked))
 322                 DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
 323         else
 324                 DBG("DSI PLL lock success");
 325 
 326         return locked ? 0 : -EINVAL;
 327 }
 328 
 329 static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
 330 {
 331         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 332 
 333         DBG("id=%d", pll_28nm->id);
 334         pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
 335 }
 336 
 337 static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
 338 {
 339         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 340         struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
 341         void __iomem *base = pll_28nm->mmio;
 342 
 343         cached_state->postdiv3 =
 344                         pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
 345         cached_state->postdiv2 =
 346                         pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
 347         cached_state->postdiv1 =
 348                         pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
 349 
 350         cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
 351 }
 352 
 353 static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
 354 {
 355         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 356         struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
 357         void __iomem *base = pll_28nm->mmio;
 358         int ret;
 359 
 360         ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
 361                                         cached_state->vco_rate, 0);
 362         if (ret) {
 363                 DRM_DEV_ERROR(&pll_28nm->pdev->dev,
 364                         "restore vco rate failed. ret=%d\n", ret);
 365                 return ret;
 366         }
 367 
 368         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
 369                         cached_state->postdiv3);
 370         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
 371                         cached_state->postdiv2);
 372         pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
 373                         cached_state->postdiv1);
 374 
 375         return 0;
 376 }
 377 
 378 static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
 379                                 struct clk **byte_clk_provider,
 380                                 struct clk **pixel_clk_provider)
 381 {
 382         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 383 
 384         if (byte_clk_provider)
 385                 *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
 386         if (pixel_clk_provider)
 387                 *pixel_clk_provider =
 388                                 pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
 389 
 390         return 0;
 391 }
 392 
 393 static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
 394 {
 395         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
 396 
 397         msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
 398                                         pll_28nm->clks, pll_28nm->num_clks);
 399 }
 400 
 401 static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
 402 {
 403         char *clk_name, *parent_name, *vco_name;
 404         struct clk_init_data vco_init = {
 405                 .parent_names = (const char *[]){ "pxo" },
 406                 .num_parents = 1,
 407                 .flags = CLK_IGNORE_UNUSED,
 408                 .ops = &clk_ops_dsi_pll_28nm_vco,
 409         };
 410         struct device *dev = &pll_28nm->pdev->dev;
 411         struct clk **clks = pll_28nm->clks;
 412         struct clk **provided_clks = pll_28nm->provided_clks;
 413         struct clk_bytediv *bytediv;
 414         struct clk_init_data bytediv_init = { };
 415         int ret, num = 0;
 416 
 417         DBG("%d", pll_28nm->id);
 418 
 419         bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL);
 420         if (!bytediv)
 421                 return -ENOMEM;
 422 
 423         vco_name = devm_kzalloc(dev, 32, GFP_KERNEL);
 424         if (!vco_name)
 425                 return -ENOMEM;
 426 
 427         parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
 428         if (!parent_name)
 429                 return -ENOMEM;
 430 
 431         clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
 432         if (!clk_name)
 433                 return -ENOMEM;
 434 
 435         pll_28nm->bytediv = bytediv;
 436 
 437         snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
 438         vco_init.name = vco_name;
 439 
 440         pll_28nm->base.clk_hw.init = &vco_init;
 441 
 442         clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
 443 
 444         /* prepare and register bytediv */
 445         bytediv->hw.init = &bytediv_init;
 446         bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
 447 
 448         snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id);
 449         snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
 450 
 451         bytediv_init.name = clk_name;
 452         bytediv_init.ops = &clk_bytediv_ops;
 453         bytediv_init.flags = CLK_SET_RATE_PARENT;
 454         bytediv_init.parent_names = (const char * const *) &parent_name;
 455         bytediv_init.num_parents = 1;
 456 
 457         /* DIV2 */
 458         clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
 459                         clk_register(dev, &bytediv->hw);
 460 
 461         snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
 462         /* DIV3 */
 463         clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
 464                         clk_register_divider(dev, clk_name,
 465                                 parent_name, 0, pll_28nm->mmio +
 466                                 REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
 467                                 0, 8, 0, NULL);
 468 
 469         pll_28nm->num_clks = num;
 470 
 471         pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
 472         pll_28nm->clk_data.clks = provided_clks;
 473 
 474         ret = of_clk_add_provider(dev->of_node,
 475                         of_clk_src_onecell_get, &pll_28nm->clk_data);
 476         if (ret) {
 477                 DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
 478                 return ret;
 479         }
 480 
 481         return 0;
 482 }
 483 
 484 struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
 485                                                int id)
 486 {
 487         struct dsi_pll_28nm *pll_28nm;
 488         struct msm_dsi_pll *pll;
 489         int ret;
 490 
 491         if (!pdev)
 492                 return ERR_PTR(-ENODEV);
 493 
 494         pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);
 495         if (!pll_28nm)
 496                 return ERR_PTR(-ENOMEM);
 497 
 498         pll_28nm->pdev = pdev;
 499         pll_28nm->id = id + 1;
 500 
 501         pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
 502         if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
 503                 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
 504                 return ERR_PTR(-ENOMEM);
 505         }
 506 
 507         pll = &pll_28nm->base;
 508         pll->min_rate = VCO_MIN_RATE;
 509         pll->max_rate = VCO_MAX_RATE;
 510         pll->get_provider = dsi_pll_28nm_get_provider;
 511         pll->destroy = dsi_pll_28nm_destroy;
 512         pll->disable_seq = dsi_pll_28nm_disable_seq;
 513         pll->save_state = dsi_pll_28nm_save_state;
 514         pll->restore_state = dsi_pll_28nm_restore_state;
 515 
 516         pll->en_seq_cnt = 1;
 517         pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
 518 
 519         ret = pll_28nm_register(pll_28nm);
 520         if (ret) {
 521                 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
 522                 return ERR_PTR(ret);
 523         }
 524 
 525         return pll;
 526 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c

DEFINITIONS
