root/drivers/gpu/drm/msm/dsi/dsi.xml.h

INCLUDED FROM

DEFINITIONS

1. DSI_6G_HW_VERSION_MAJOR
2. DSI_6G_HW_VERSION_MINOR
3. DSI_6G_HW_VERSION_STEP
4. DSI_VID_CFG0_VIRT_CHANNEL
5. DSI_VID_CFG0_DST_FORMAT
6. DSI_VID_CFG0_TRAFFIC_MODE
7. DSI_VID_CFG1_RGB_SWAP
8. DSI_ACTIVE_H_START
9. DSI_ACTIVE_H_END
10. DSI_ACTIVE_V_START
11. DSI_ACTIVE_V_END
12. DSI_TOTAL_H_TOTAL
13. DSI_TOTAL_V_TOTAL
14. DSI_ACTIVE_HSYNC_START
15. DSI_ACTIVE_HSYNC_END
16. DSI_ACTIVE_VSYNC_HPOS_START
17. DSI_ACTIVE_VSYNC_HPOS_END
18. DSI_ACTIVE_VSYNC_VPOS_START
19. DSI_ACTIVE_VSYNC_VPOS_END
20. DSI_CMD_CFG0_DST_FORMAT
21. DSI_CMD_CFG0_INTERLEAVE_MAX
22. DSI_CMD_CFG0_RGB_SWAP
23. DSI_CMD_CFG1_WR_MEM_START
24. DSI_CMD_CFG1_WR_MEM_CONTINUE
25. DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE
26. DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL
27. DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT
28. DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL
29. DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL
30. REG_DSI_RDBK
31. REG_DSI_RDBK_DATA
32. DSI_TRIG_CTRL_DMA_TRIGGER
33. DSI_TRIG_CTRL_MDP_TRIGGER
34. DSI_TRIG_CTRL_STREAM
35. DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE
36. DSI_CLKOUT_TIMING_CTRL_T_CLK_POST
37. DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL
38. DSI_RDBK_DATA_CTRL_COUNT
39. DSI_VERSION_MAJOR
40. REG_DSI_28nm_8960_PHY_LN
41. REG_DSI_28nm_8960_PHY_LN_CFG_0
42. REG_DSI_28nm_8960_PHY_LN_CFG_1
43. REG_DSI_28nm_8960_PHY_LN_CFG_2
44. REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH
45. REG_DSI_28nm_8960_PHY_LN_TEST_STR_0
46. REG_DSI_28nm_8960_PHY_LN_TEST_STR_1
47. DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO
48. DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL
49. DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE
50. DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT
51. DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO
52. DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE
53. DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL
54. DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST
55. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO
56. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE
57. DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET
58. DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD
59. REG_DSI_28nm_PHY_LN
60. REG_DSI_28nm_PHY_LN_CFG_0
61. REG_DSI_28nm_PHY_LN_CFG_1
62. REG_DSI_28nm_PHY_LN_CFG_2
63. REG_DSI_28nm_PHY_LN_CFG_3
64. REG_DSI_28nm_PHY_LN_CFG_4
65. REG_DSI_28nm_PHY_LN_TEST_DATAPATH
66. REG_DSI_28nm_PHY_LN_DEBUG_SEL
67. REG_DSI_28nm_PHY_LN_TEST_STR_0
68. REG_DSI_28nm_PHY_LN_TEST_STR_1
69. DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO
70. DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL
71. DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE
72. DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT
73. DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO
74. DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE
75. DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL
76. DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST
77. DSI_28nm_PHY_TIMING_CTRL_9_TA_GO
78. DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE
79. DSI_28nm_PHY_TIMING_CTRL_10_TA_GET
80. DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD
81. DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV
82. DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET
83. DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN
84. DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0
85. DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8
86. REG_DSI_20nm_PHY_LN
87. REG_DSI_20nm_PHY_LN_CFG_0
88. REG_DSI_20nm_PHY_LN_CFG_1
89. REG_DSI_20nm_PHY_LN_CFG_2
90. REG_DSI_20nm_PHY_LN_CFG_3
91. REG_DSI_20nm_PHY_LN_CFG_4
92. REG_DSI_20nm_PHY_LN_TEST_DATAPATH
93. REG_DSI_20nm_PHY_LN_DEBUG_SEL
94. REG_DSI_20nm_PHY_LN_TEST_STR_0
95. REG_DSI_20nm_PHY_LN_TEST_STR_1
96. DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO
97. DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL
98. DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE
99. DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT
100. DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO
101. DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE
102. DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL
103. DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST
104. DSI_20nm_PHY_TIMING_CTRL_9_TA_GO
105. DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE
106. DSI_20nm_PHY_TIMING_CTRL_10_TA_GET
107. DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD
108. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0
109. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4
110. DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL
111. REG_DSI_14nm_PHY_LN
112. REG_DSI_14nm_PHY_LN_CFG0
113. DSI_14nm_PHY_LN_CFG0_PREPARE_DLY
114. REG_DSI_14nm_PHY_LN_CFG1
115. REG_DSI_14nm_PHY_LN_CFG2
116. REG_DSI_14nm_PHY_LN_CFG3
117. REG_DSI_14nm_PHY_LN_TEST_DATAPATH
118. REG_DSI_14nm_PHY_LN_TEST_STR
119. REG_DSI_14nm_PHY_LN_TIMING_CTRL_4
120. DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT
121. REG_DSI_14nm_PHY_LN_TIMING_CTRL_5
122. DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO
123. REG_DSI_14nm_PHY_LN_TIMING_CTRL_6
124. DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE
125. REG_DSI_14nm_PHY_LN_TIMING_CTRL_7
126. DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL
127. REG_DSI_14nm_PHY_LN_TIMING_CTRL_8
128. DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST
129. REG_DSI_14nm_PHY_LN_TIMING_CTRL_9
130. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO
131. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE
132. REG_DSI_14nm_PHY_LN_TIMING_CTRL_10
133. DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET
134. REG_DSI_14nm_PHY_LN_TIMING_CTRL_11
135. DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD
136. REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0
137. REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1
138. REG_DSI_14nm_PHY_LN_VREG_CNTRL
139. REG_DSI_10nm_PHY_LN
140. REG_DSI_10nm_PHY_LN_CFG0
141. REG_DSI_10nm_PHY_LN_CFG1
142. REG_DSI_10nm_PHY_LN_CFG2
143. REG_DSI_10nm_PHY_LN_CFG3
144. REG_DSI_10nm_PHY_LN_TEST_DATAPATH
145. REG_DSI_10nm_PHY_LN_PIN_SWAP
146. REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL
147. REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL
148. REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL
149. REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL
150. REG_DSI_10nm_PHY_LN_LPRX_CTRL
151. REG_DSI_10nm_PHY_LN_TX_DCTRL

   1 #ifndef DSI_XML
   2 #define DSI_XML
   3 
   4 /* Autogenerated file, DO NOT EDIT manually!
   5 
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9 
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/envytools/rnndb/msm.xml                 (    676 bytes, from 2018-07-03 19:37:13)
  12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2018-07-03 19:37:13)
  13 - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2018-07-03 19:37:13)
  14 - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2018-07-03 19:37:13)
  15 - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2018-07-03 19:37:13)
  16 - /home/robclark/src/envytools/rnndb/dsi/dsi.xml             (  37239 bytes, from 2018-07-03 19:37:13)
  17 - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2018-07-03 19:37:13)
  18 - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2018-07-03 19:37:13)
  19 - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2018-07-03 19:37:13)
  20 - /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml           (  41799 bytes, from 2018-07-03 19:37:13)
  21 - /home/robclark/src/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2018-07-03 19:37:13)
  22 
  23 Copyright (C) 2013-2018 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26 
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34 
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38 
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47 
  48 
  49 enum dsi_traffic_mode {
  50         NON_BURST_SYNCH_PULSE = 0,
  51         NON_BURST_SYNCH_EVENT = 1,
  52         BURST_MODE = 2,
  53 };
  54 
  55 enum dsi_vid_dst_format {
  56         VID_DST_FORMAT_RGB565 = 0,
  57         VID_DST_FORMAT_RGB666 = 1,
  58         VID_DST_FORMAT_RGB666_LOOSE = 2,
  59         VID_DST_FORMAT_RGB888 = 3,
  60 };
  61 
  62 enum dsi_rgb_swap {
  63         SWAP_RGB = 0,
  64         SWAP_RBG = 1,
  65         SWAP_BGR = 2,
  66         SWAP_BRG = 3,
  67         SWAP_GRB = 4,
  68         SWAP_GBR = 5,
  69 };
  70 
  71 enum dsi_cmd_trigger {
  72         TRIGGER_NONE = 0,
  73         TRIGGER_SEOF = 1,
  74         TRIGGER_TE = 2,
  75         TRIGGER_SW = 4,
  76         TRIGGER_SW_SEOF = 5,
  77         TRIGGER_SW_TE = 6,
  78 };
  79 
  80 enum dsi_cmd_dst_format {
  81         CMD_DST_FORMAT_RGB111 = 0,
  82         CMD_DST_FORMAT_RGB332 = 3,
  83         CMD_DST_FORMAT_RGB444 = 4,
  84         CMD_DST_FORMAT_RGB565 = 6,
  85         CMD_DST_FORMAT_RGB666 = 7,
  86         CMD_DST_FORMAT_RGB888 = 8,
  87 };
  88 
  89 enum dsi_lane_swap {
  90         LANE_SWAP_0123 = 0,
  91         LANE_SWAP_3012 = 1,
  92         LANE_SWAP_2301 = 2,
  93         LANE_SWAP_1230 = 3,
  94         LANE_SWAP_0321 = 4,
  95         LANE_SWAP_1032 = 5,
  96         LANE_SWAP_2103 = 6,
  97         LANE_SWAP_3210 = 7,
  98 };
  99 
 100 #define DSI_IRQ_CMD_DMA_DONE                                    0x00000001
 101 #define DSI_IRQ_MASK_CMD_DMA_DONE                               0x00000002
 102 #define DSI_IRQ_CMD_MDP_DONE                                    0x00000100
 103 #define DSI_IRQ_MASK_CMD_MDP_DONE                               0x00000200
 104 #define DSI_IRQ_VIDEO_DONE                                      0x00010000
 105 #define DSI_IRQ_MASK_VIDEO_DONE                                 0x00020000
 106 #define DSI_IRQ_BTA_DONE                                        0x00100000
 107 #define DSI_IRQ_MASK_BTA_DONE                                   0x00200000
 108 #define DSI_IRQ_ERROR                                           0x01000000
 109 #define DSI_IRQ_MASK_ERROR                                      0x02000000
 110 #define REG_DSI_6G_HW_VERSION                                   0x00000000
 111 #define DSI_6G_HW_VERSION_MAJOR__MASK                           0xf0000000
 112 #define DSI_6G_HW_VERSION_MAJOR__SHIFT                          28
 113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
 114 {
 115         return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
 116 }
 117 #define DSI_6G_HW_VERSION_MINOR__MASK                           0x0fff0000
 118 #define DSI_6G_HW_VERSION_MINOR__SHIFT                          16
 119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
 120 {
 121         return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
 122 }
 123 #define DSI_6G_HW_VERSION_STEP__MASK                            0x0000ffff
 124 #define DSI_6G_HW_VERSION_STEP__SHIFT                           0
 125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
 126 {
 127         return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
 128 }
 129 
 130 #define REG_DSI_CTRL                                            0x00000000
 131 #define DSI_CTRL_ENABLE                                         0x00000001
 132 #define DSI_CTRL_VID_MODE_EN                                    0x00000002
 133 #define DSI_CTRL_CMD_MODE_EN                                    0x00000004
 134 #define DSI_CTRL_LANE0                                          0x00000010
 135 #define DSI_CTRL_LANE1                                          0x00000020
 136 #define DSI_CTRL_LANE2                                          0x00000040
 137 #define DSI_CTRL_LANE3                                          0x00000080
 138 #define DSI_CTRL_CLK_EN                                         0x00000100
 139 #define DSI_CTRL_ECC_CHECK                                      0x00100000
 140 #define DSI_CTRL_CRC_CHECK                                      0x01000000
 141 
 142 #define REG_DSI_STATUS0                                         0x00000004
 143 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY                        0x00000001
 144 #define DSI_STATUS0_CMD_MODE_DMA_BUSY                           0x00000002
 145 #define DSI_STATUS0_CMD_MODE_MDP_BUSY                           0x00000004
 146 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY                      0x00000008
 147 #define DSI_STATUS0_DSI_BUSY                                    0x00000010
 148 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION                    0x80000000
 149 
 150 #define REG_DSI_FIFO_STATUS                                     0x00000008
 151 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW                  0x00000080
 152 
 153 #define REG_DSI_VID_CFG0                                        0x0000000c
 154 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK                         0x00000003
 155 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT                        0
 156 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
 157 {
 158         return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
 159 }
 160 #define DSI_VID_CFG0_DST_FORMAT__MASK                           0x00000030
 161 #define DSI_VID_CFG0_DST_FORMAT__SHIFT                          4
 162 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
 163 {
 164         return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
 165 }
 166 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK                         0x00000300
 167 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT                        8
 168 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
 169 {
 170         return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
 171 }
 172 #define DSI_VID_CFG0_BLLP_POWER_STOP                            0x00001000
 173 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP                        0x00008000
 174 #define DSI_VID_CFG0_HSA_POWER_STOP                             0x00010000
 175 #define DSI_VID_CFG0_HBP_POWER_STOP                             0x00100000
 176 #define DSI_VID_CFG0_HFP_POWER_STOP                             0x01000000
 177 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE                          0x10000000
 178 
 179 #define REG_DSI_VID_CFG1                                        0x0000001c
 180 #define DSI_VID_CFG1_R_SEL                                      0x00000001
 181 #define DSI_VID_CFG1_G_SEL                                      0x00000010
 182 #define DSI_VID_CFG1_B_SEL                                      0x00000100
 183 #define DSI_VID_CFG1_RGB_SWAP__MASK                             0x00007000
 184 #define DSI_VID_CFG1_RGB_SWAP__SHIFT                            12
 185 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
 186 {
 187         return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
 188 }
 189 
 190 #define REG_DSI_ACTIVE_H                                        0x00000020
 191 #define DSI_ACTIVE_H_START__MASK                                0x00000fff
 192 #define DSI_ACTIVE_H_START__SHIFT                               0
 193 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
 194 {
 195         return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
 196 }
 197 #define DSI_ACTIVE_H_END__MASK                                  0x0fff0000
 198 #define DSI_ACTIVE_H_END__SHIFT                                 16
 199 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
 200 {
 201         return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
 202 }
 203 
 204 #define REG_DSI_ACTIVE_V                                        0x00000024
 205 #define DSI_ACTIVE_V_START__MASK                                0x00000fff
 206 #define DSI_ACTIVE_V_START__SHIFT                               0
 207 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
 208 {
 209         return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
 210 }
 211 #define DSI_ACTIVE_V_END__MASK                                  0x0fff0000
 212 #define DSI_ACTIVE_V_END__SHIFT                                 16
 213 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
 214 {
 215         return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
 216 }
 217 
 218 #define REG_DSI_TOTAL                                           0x00000028
 219 #define DSI_TOTAL_H_TOTAL__MASK                                 0x00000fff
 220 #define DSI_TOTAL_H_TOTAL__SHIFT                                0
 221 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
 222 {
 223         return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
 224 }
 225 #define DSI_TOTAL_V_TOTAL__MASK                                 0x0fff0000
 226 #define DSI_TOTAL_V_TOTAL__SHIFT                                16
 227 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
 228 {
 229         return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
 230 }
 231 
 232 #define REG_DSI_ACTIVE_HSYNC                                    0x0000002c
 233 #define DSI_ACTIVE_HSYNC_START__MASK                            0x00000fff
 234 #define DSI_ACTIVE_HSYNC_START__SHIFT                           0
 235 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
 236 {
 237         return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
 238 }
 239 #define DSI_ACTIVE_HSYNC_END__MASK                              0x0fff0000
 240 #define DSI_ACTIVE_HSYNC_END__SHIFT                             16
 241 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
 242 {
 243         return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
 244 }
 245 
 246 #define REG_DSI_ACTIVE_VSYNC_HPOS                               0x00000030
 247 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK                       0x00000fff
 248 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT                      0
 249 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
 250 {
 251         return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
 252 }
 253 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK                         0x0fff0000
 254 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT                        16
 255 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
 256 {
 257         return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
 258 }
 259 
 260 #define REG_DSI_ACTIVE_VSYNC_VPOS                               0x00000034
 261 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK                       0x00000fff
 262 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT                      0
 263 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
 264 {
 265         return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
 266 }
 267 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK                         0x0fff0000
 268 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT                        16
 269 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
 270 {
 271         return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
 272 }
 273 
 274 #define REG_DSI_CMD_DMA_CTRL                                    0x00000038
 275 #define DSI_CMD_DMA_CTRL_BROADCAST_EN                           0x80000000
 276 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER                      0x10000000
 277 #define DSI_CMD_DMA_CTRL_LOW_POWER                              0x04000000
 278 
 279 #define REG_DSI_CMD_CFG0                                        0x0000003c
 280 #define DSI_CMD_CFG0_DST_FORMAT__MASK                           0x0000000f
 281 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT                          0
 282 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
 283 {
 284         return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
 285 }
 286 #define DSI_CMD_CFG0_R_SEL                                      0x00000010
 287 #define DSI_CMD_CFG0_G_SEL                                      0x00000100
 288 #define DSI_CMD_CFG0_B_SEL                                      0x00001000
 289 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK                       0x00f00000
 290 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT                      20
 291 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
 292 {
 293         return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
 294 }
 295 #define DSI_CMD_CFG0_RGB_SWAP__MASK                             0x00070000
 296 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT                            16
 297 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
 298 {
 299         return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
 300 }
 301 
 302 #define REG_DSI_CMD_CFG1                                        0x00000040
 303 #define DSI_CMD_CFG1_WR_MEM_START__MASK                         0x000000ff
 304 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT                        0
 305 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
 306 {
 307         return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
 308 }
 309 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK                      0x0000ff00
 310 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT                     8
 311 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
 312 {
 313         return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
 314 }
 315 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND                         0x00010000
 316 
 317 #define REG_DSI_DMA_BASE                                        0x00000044
 318 
 319 #define REG_DSI_DMA_LEN                                         0x00000048
 320 
 321 #define REG_DSI_CMD_MDP_STREAM_CTRL                             0x00000054
 322 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK                 0x0000003f
 323 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT                0
 324 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
 325 {
 326         return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
 327 }
 328 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK           0x00000300
 329 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT          8
 330 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
 331 {
 332         return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
 333 }
 334 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK                0xffff0000
 335 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT               16
 336 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
 337 {
 338         return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
 339 }
 340 
 341 #define REG_DSI_CMD_MDP_STREAM_TOTAL                            0x00000058
 342 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK                  0x00000fff
 343 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT                 0
 344 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
 345 {
 346         return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
 347 }
 348 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK                  0x0fff0000
 349 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT                 16
 350 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
 351 {
 352         return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
 353 }
 354 
 355 #define REG_DSI_ACK_ERR_STATUS                                  0x00000064
 356 
 357 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
 358 
 359 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
 360 
 361 #define REG_DSI_TRIG_CTRL                                       0x00000080
 362 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK                         0x00000007
 363 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT                        0
 364 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
 365 {
 366         return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
 367 }
 368 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK                         0x00000070
 369 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT                        4
 370 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
 371 {
 372         return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
 373 }
 374 #define DSI_TRIG_CTRL_STREAM__MASK                              0x00000300
 375 #define DSI_TRIG_CTRL_STREAM__SHIFT                             8
 376 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
 377 {
 378         return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
 379 }
 380 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME                    0x00001000
 381 #define DSI_TRIG_CTRL_TE                                        0x80000000
 382 
 383 #define REG_DSI_TRIG_DMA                                        0x0000008c
 384 
 385 #define REG_DSI_DLN0_PHY_ERR                                    0x000000b0
 386 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC                           0x00000001
 387 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC                      0x00000010
 388 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL                       0x00000100
 389 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0                0x00001000
 390 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1                0x00010000
 391 
 392 #define REG_DSI_TIMEOUT_STATUS                                  0x000000bc
 393 
 394 #define REG_DSI_CLKOUT_TIMING_CTRL                              0x000000c0
 395 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK                  0x0000003f
 396 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT                 0
 397 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
 398 {
 399         return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
 400 }
 401 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK                 0x00003f00
 402 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT                8
 403 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
 404 {
 405         return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
 406 }
 407 
 408 #define REG_DSI_EOT_PACKET_CTRL                                 0x000000c8
 409 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND                       0x00000001
 410 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE                       0x00000010
 411 
 412 #define REG_DSI_LANE_CTRL                                       0x000000a8
 413 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST                    0x10000000
 414 
 415 #define REG_DSI_LANE_SWAP_CTRL                                  0x000000ac
 416 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK                   0x00000007
 417 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT                  0
 418 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
 419 {
 420         return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
 421 }
 422 
 423 #define REG_DSI_ERR_INT_MASK0                                   0x00000108
 424 
 425 #define REG_DSI_INTR_CTRL                                       0x0000010c
 426 
 427 #define REG_DSI_RESET                                           0x00000114
 428 
 429 #define REG_DSI_CLK_CTRL                                        0x00000118
 430 #define DSI_CLK_CTRL_AHBS_HCLK_ON                               0x00000001
 431 #define DSI_CLK_CTRL_AHBM_SCLK_ON                               0x00000002
 432 #define DSI_CLK_CTRL_PCLK_ON                                    0x00000004
 433 #define DSI_CLK_CTRL_DSICLK_ON                                  0x00000008
 434 #define DSI_CLK_CTRL_BYTECLK_ON                                 0x00000010
 435 #define DSI_CLK_CTRL_ESCCLK_ON                                  0x00000020
 436 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK                     0x00000200
 437 
 438 #define REG_DSI_CLK_STATUS                                      0x0000011c
 439 #define DSI_CLK_STATUS_PLL_UNLOCKED                             0x00010000
 440 
 441 #define REG_DSI_PHY_RESET                                       0x00000128
 442 #define DSI_PHY_RESET_RESET                                     0x00000001
 443 
 444 #define REG_DSI_T_CLK_PRE_EXTEND                                0x0000017c
 445 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK                   0x00000001
 446 
 447 #define REG_DSI_RDBK_DATA_CTRL                                  0x000001d0
 448 #define DSI_RDBK_DATA_CTRL_COUNT__MASK                          0x00ff0000
 449 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT                         16
 450 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
 451 {
 452         return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
 453 }
 454 #define DSI_RDBK_DATA_CTRL_CLR                                  0x00000001
 455 
 456 #define REG_DSI_VERSION                                         0x000001f0
 457 #define DSI_VERSION_MAJOR__MASK                                 0xff000000
 458 #define DSI_VERSION_MAJOR__SHIFT                                24
 459 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
 460 {
 461         return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
 462 }
 463 
 464 #define REG_DSI_PHY_PLL_CTRL_0                                  0x00000200
 465 #define DSI_PHY_PLL_CTRL_0_ENABLE                               0x00000001
 466 
 467 #define REG_DSI_PHY_PLL_CTRL_1                                  0x00000204
 468 
 469 #define REG_DSI_PHY_PLL_CTRL_2                                  0x00000208
 470 
 471 #define REG_DSI_PHY_PLL_CTRL_3                                  0x0000020c
 472 
 473 #define REG_DSI_PHY_PLL_CTRL_4                                  0x00000210
 474 
 475 #define REG_DSI_PHY_PLL_CTRL_5                                  0x00000214
 476 
 477 #define REG_DSI_PHY_PLL_CTRL_6                                  0x00000218
 478 
 479 #define REG_DSI_PHY_PLL_CTRL_7                                  0x0000021c
 480 
 481 #define REG_DSI_PHY_PLL_CTRL_8                                  0x00000220
 482 
 483 #define REG_DSI_PHY_PLL_CTRL_9                                  0x00000224
 484 
 485 #define REG_DSI_PHY_PLL_CTRL_10                                 0x00000228
 486 
 487 #define REG_DSI_PHY_PLL_CTRL_11                                 0x0000022c
 488 
 489 #define REG_DSI_PHY_PLL_CTRL_12                                 0x00000230
 490 
 491 #define REG_DSI_PHY_PLL_CTRL_13                                 0x00000234
 492 
 493 #define REG_DSI_PHY_PLL_CTRL_14                                 0x00000238
 494 
 495 #define REG_DSI_PHY_PLL_CTRL_15                                 0x0000023c
 496 
 497 #define REG_DSI_PHY_PLL_CTRL_16                                 0x00000240
 498 
 499 #define REG_DSI_PHY_PLL_CTRL_17                                 0x00000244
 500 
 501 #define REG_DSI_PHY_PLL_CTRL_18                                 0x00000248
 502 
 503 #define REG_DSI_PHY_PLL_CTRL_19                                 0x0000024c
 504 
 505 #define REG_DSI_PHY_PLL_CTRL_20                                 0x00000250
 506 
 507 #define REG_DSI_PHY_PLL_STATUS                                  0x00000280
 508 #define DSI_PHY_PLL_STATUS_PLL_BUSY                             0x00000001
 509 
 510 #define REG_DSI_8x60_PHY_TPA_CTRL_1                             0x00000258
 511 
 512 #define REG_DSI_8x60_PHY_TPA_CTRL_2                             0x0000025c
 513 
 514 #define REG_DSI_8x60_PHY_TIMING_CTRL_0                          0x00000260
 515 
 516 #define REG_DSI_8x60_PHY_TIMING_CTRL_1                          0x00000264
 517 
 518 #define REG_DSI_8x60_PHY_TIMING_CTRL_2                          0x00000268
 519 
 520 #define REG_DSI_8x60_PHY_TIMING_CTRL_3                          0x0000026c
 521 
 522 #define REG_DSI_8x60_PHY_TIMING_CTRL_4                          0x00000270
 523 
 524 #define REG_DSI_8x60_PHY_TIMING_CTRL_5                          0x00000274
 525 
 526 #define REG_DSI_8x60_PHY_TIMING_CTRL_6                          0x00000278
 527 
 528 #define REG_DSI_8x60_PHY_TIMING_CTRL_7                          0x0000027c
 529 
 530 #define REG_DSI_8x60_PHY_TIMING_CTRL_8                          0x00000280
 531 
 532 #define REG_DSI_8x60_PHY_TIMING_CTRL_9                          0x00000284
 533 
 534 #define REG_DSI_8x60_PHY_TIMING_CTRL_10                         0x00000288
 535 
 536 #define REG_DSI_8x60_PHY_TIMING_CTRL_11                         0x0000028c
 537 
 538 #define REG_DSI_8x60_PHY_CTRL_0                                 0x00000290
 539 
 540 #define REG_DSI_8x60_PHY_CTRL_1                                 0x00000294
 541 
 542 #define REG_DSI_8x60_PHY_CTRL_2                                 0x00000298
 543 
 544 #define REG_DSI_8x60_PHY_CTRL_3                                 0x0000029c
 545 
 546 #define REG_DSI_8x60_PHY_STRENGTH_0                             0x000002a0
 547 
 548 #define REG_DSI_8x60_PHY_STRENGTH_1                             0x000002a4
 549 
 550 #define REG_DSI_8x60_PHY_STRENGTH_2                             0x000002a8
 551 
 552 #define REG_DSI_8x60_PHY_STRENGTH_3                             0x000002ac
 553 
 554 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0                       0x000002cc
 555 
 556 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1                       0x000002d0
 557 
 558 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2                       0x000002d4
 559 
 560 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3                       0x000002d8
 561 
 562 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4                       0x000002dc
 563 
 564 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER                         0x000000f0
 565 
 566 #define REG_DSI_8x60_PHY_CAL_CTRL                               0x000000f4
 567 
 568 #define REG_DSI_8x60_PHY_CAL_STATUS                             0x000000fc
 569 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY                        0x10000000
 570 
 571 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
 572 
 573 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
 574 
 575 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
 576 
 577 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
 578 
 579 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
 580 
 581 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
 582 
 583 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
 584 
 585 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0                        0x00000100
 586 
 587 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1                        0x00000104
 588 
 589 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2                        0x00000108
 590 
 591 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH                0x0000010c
 592 
 593 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0                    0x00000114
 594 
 595 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1                    0x00000118
 596 
 597 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0                     0x00000140
 598 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK          0x000000ff
 599 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT         0
 600 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
 601 {
 602         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
 603 }
 604 
 605 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1                     0x00000144
 606 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK         0x000000ff
 607 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT        0
 608 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
 609 {
 610         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
 611 }
 612 
 613 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2                     0x00000148
 614 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK       0x000000ff
 615 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT      0
 616 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
 617 {
 618         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
 619 }
 620 
 621 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3                     0x0000014c
 622 
 623 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4                     0x00000150
 624 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK           0x000000ff
 625 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT          0
 626 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
 627 {
 628         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
 629 }
 630 
 631 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5                     0x00000154
 632 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK           0x000000ff
 633 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT          0
 634 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
 635 {
 636         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
 637 }
 638 
 639 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6                     0x00000158
 640 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK        0x000000ff
 641 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT       0
 642 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
 643 {
 644         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
 645 }
 646 
 647 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7                     0x0000015c
 648 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK          0x000000ff
 649 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT         0
 650 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
 651 {
 652         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
 653 }
 654 
 655 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8                     0x00000160
 656 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK           0x000000ff
 657 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT          0
 658 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
 659 {
 660         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
 661 }
 662 
 663 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9                     0x00000164
 664 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK             0x00000007
 665 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT            0
 666 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
 667 {
 668         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
 669 }
 670 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK           0x00000070
 671 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT          4
 672 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
 673 {
 674         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
 675 }
 676 
 677 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10                    0x00000168
 678 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK           0x00000007
 679 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT          0
 680 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
 681 {
 682         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
 683 }
 684 
 685 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11                    0x0000016c
 686 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK        0x000000ff
 687 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT       0
 688 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 689 {
 690         return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
 691 }
 692 
 693 #define REG_DSI_28nm_8960_PHY_CTRL_0                            0x00000170
 694 
 695 #define REG_DSI_28nm_8960_PHY_CTRL_1                            0x00000174
 696 
 697 #define REG_DSI_28nm_8960_PHY_CTRL_2                            0x00000178
 698 
 699 #define REG_DSI_28nm_8960_PHY_CTRL_3                            0x0000017c
 700 
 701 #define REG_DSI_28nm_8960_PHY_STRENGTH_0                        0x00000180
 702 
 703 #define REG_DSI_28nm_8960_PHY_STRENGTH_1                        0x00000184
 704 
 705 #define REG_DSI_28nm_8960_PHY_STRENGTH_2                        0x00000188
 706 
 707 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0                       0x0000018c
 708 
 709 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1                       0x00000190
 710 
 711 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2                       0x00000194
 712 
 713 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3                       0x00000198
 714 
 715 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4                       0x0000019c
 716 
 717 #define REG_DSI_28nm_8960_PHY_LDO_CTRL                          0x000001b0
 718 
 719 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0             0x00000000
 720 
 721 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1             0x00000004
 722 
 723 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2             0x00000008
 724 
 725 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3             0x0000000c
 726 
 727 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4             0x00000010
 728 
 729 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5             0x00000014
 730 
 731 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG        0x00000018
 732 
 733 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER               0x00000028
 734 
 735 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0                 0x0000002c
 736 
 737 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1                 0x00000030
 738 
 739 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2                 0x00000034
 740 
 741 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0                 0x00000038
 742 
 743 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1                 0x0000003c
 744 
 745 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2                 0x00000040
 746 
 747 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3                 0x00000044
 748 
 749 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4                 0x00000048
 750 
 751 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS                   0x00000050
 752 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY              0x00000010
 753 
 754 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0                        0x00000000
 755 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE                     0x00000001
 756 
 757 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1                        0x00000004
 758 
 759 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2                        0x00000008
 760 
 761 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3                        0x0000000c
 762 
 763 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4                        0x00000010
 764 
 765 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5                        0x00000014
 766 
 767 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6                        0x00000018
 768 
 769 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7                        0x0000001c
 770 
 771 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8                        0x00000020
 772 
 773 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9                        0x00000024
 774 
 775 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10                       0x00000028
 776 
 777 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11                       0x0000002c
 778 
 779 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12                       0x00000030
 780 
 781 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13                       0x00000034
 782 
 783 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14                       0x00000038
 784 
 785 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15                       0x0000003c
 786 
 787 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16                       0x00000040
 788 
 789 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17                       0x00000044
 790 
 791 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18                       0x00000048
 792 
 793 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19                       0x0000004c
 794 
 795 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20                       0x00000050
 796 
 797 #define REG_DSI_28nm_8960_PHY_PLL_RDY                           0x00000080
 798 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY                       0x00000001
 799 
 800 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
 801 
 802 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
 803 
 804 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
 805 
 806 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
 807 
 808 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
 809 
 810 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
 811 
 812 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
 813 
 814 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
 815 
 816 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
 817 
 818 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
 819 
 820 #define REG_DSI_28nm_PHY_LNCK_CFG_0                             0x00000100
 821 
 822 #define REG_DSI_28nm_PHY_LNCK_CFG_1                             0x00000104
 823 
 824 #define REG_DSI_28nm_PHY_LNCK_CFG_2                             0x00000108
 825 
 826 #define REG_DSI_28nm_PHY_LNCK_CFG_3                             0x0000010c
 827 
 828 #define REG_DSI_28nm_PHY_LNCK_CFG_4                             0x00000110
 829 
 830 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH                     0x00000114
 831 
 832 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL                         0x00000118
 833 
 834 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0                         0x0000011c
 835 
 836 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1                         0x00000120
 837 
 838 #define REG_DSI_28nm_PHY_TIMING_CTRL_0                          0x00000140
 839 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK               0x000000ff
 840 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT              0
 841 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
 842 {
 843         return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
 844 }
 845 
 846 #define REG_DSI_28nm_PHY_TIMING_CTRL_1                          0x00000144
 847 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK              0x000000ff
 848 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT             0
 849 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
 850 {
 851         return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
 852 }
 853 
 854 #define REG_DSI_28nm_PHY_TIMING_CTRL_2                          0x00000148
 855 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK            0x000000ff
 856 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT           0
 857 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
 858 {
 859         return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
 860 }
 861 
 862 #define REG_DSI_28nm_PHY_TIMING_CTRL_3                          0x0000014c
 863 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8                   0x00000001
 864 
 865 #define REG_DSI_28nm_PHY_TIMING_CTRL_4                          0x00000150
 866 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK                0x000000ff
 867 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT               0
 868 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
 869 {
 870         return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
 871 }
 872 
 873 #define REG_DSI_28nm_PHY_TIMING_CTRL_5                          0x00000154
 874 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK                0x000000ff
 875 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT               0
 876 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
 877 {
 878         return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
 879 }
 880 
 881 #define REG_DSI_28nm_PHY_TIMING_CTRL_6                          0x00000158
 882 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK             0x000000ff
 883 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT            0
 884 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
 885 {
 886         return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
 887 }
 888 
 889 #define REG_DSI_28nm_PHY_TIMING_CTRL_7                          0x0000015c
 890 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK               0x000000ff
 891 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT              0
 892 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
 893 {
 894         return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
 895 }
 896 
 897 #define REG_DSI_28nm_PHY_TIMING_CTRL_8                          0x00000160
 898 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK                0x000000ff
 899 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT               0
 900 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
 901 {
 902         return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
 903 }
 904 
 905 #define REG_DSI_28nm_PHY_TIMING_CTRL_9                          0x00000164
 906 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK                  0x00000007
 907 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT                 0
 908 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
 909 {
 910         return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
 911 }
 912 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK                0x00000070
 913 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT               4
 914 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
 915 {
 916         return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
 917 }
 918 
 919 #define REG_DSI_28nm_PHY_TIMING_CTRL_10                         0x00000168
 920 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK                0x00000007
 921 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT               0
 922 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
 923 {
 924         return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
 925 }
 926 
 927 #define REG_DSI_28nm_PHY_TIMING_CTRL_11                         0x0000016c
 928 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK             0x000000ff
 929 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT            0
 930 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 931 {
 932         return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
 933 }
 934 
 935 #define REG_DSI_28nm_PHY_CTRL_0                                 0x00000170
 936 
 937 #define REG_DSI_28nm_PHY_CTRL_1                                 0x00000174
 938 
 939 #define REG_DSI_28nm_PHY_CTRL_2                                 0x00000178
 940 
 941 #define REG_DSI_28nm_PHY_CTRL_3                                 0x0000017c
 942 
 943 #define REG_DSI_28nm_PHY_CTRL_4                                 0x00000180
 944 
 945 #define REG_DSI_28nm_PHY_STRENGTH_0                             0x00000184
 946 
 947 #define REG_DSI_28nm_PHY_STRENGTH_1                             0x00000188
 948 
 949 #define REG_DSI_28nm_PHY_BIST_CTRL_0                            0x000001b4
 950 
 951 #define REG_DSI_28nm_PHY_BIST_CTRL_1                            0x000001b8
 952 
 953 #define REG_DSI_28nm_PHY_BIST_CTRL_2                            0x000001bc
 954 
 955 #define REG_DSI_28nm_PHY_BIST_CTRL_3                            0x000001c0
 956 
 957 #define REG_DSI_28nm_PHY_BIST_CTRL_4                            0x000001c4
 958 
 959 #define REG_DSI_28nm_PHY_BIST_CTRL_5                            0x000001c8
 960 
 961 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL                         0x000001d4
 962 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL               0x00000001
 963 
 964 #define REG_DSI_28nm_PHY_LDO_CNTRL                              0x000001dc
 965 
 966 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0                       0x00000000
 967 
 968 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1                       0x00000004
 969 
 970 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2                       0x00000008
 971 
 972 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3                       0x0000000c
 973 
 974 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4                       0x00000010
 975 
 976 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5                       0x00000014
 977 
 978 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG                  0x00000018
 979 
 980 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG                         0x00000000
 981 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR                        0x00000001
 982 
 983 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG                       0x00000004
 984 
 985 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG                        0x00000008
 986 
 987 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG                         0x0000000c
 988 
 989 #define REG_DSI_28nm_PHY_PLL_VREG_CFG                           0x00000010
 990 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B             0x00000002
 991 
 992 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG                         0x00000014
 993 
 994 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG                           0x00000018
 995 
 996 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG                           0x0000001c
 997 
 998 #define REG_DSI_28nm_PHY_PLL_GLB_CFG                            0x00000020
 999 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B                    0x00000001
1000 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B                0x00000002
1001 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B             0x00000004
1002 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE                     0x00000008
1003 
1004 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG                       0x00000024
1005 
1006 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG                       0x00000028
1007 
1008 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG                           0x0000002c
1009 
1010 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG                          0x00000030
1011 
1012 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG                          0x00000034
1013 
1014 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0                           0x00000038
1015 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK                 0x0000003f
1016 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT                0
1017 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
1018 {
1019         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
1020 }
1021 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP                           0x00000040
1022 
1023 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1                           0x0000003c
1024 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK               0x0000003f
1025 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT              0
1026 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
1027 {
1028         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
1029 }
1030 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK               0x00000040
1031 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT              6
1032 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
1033 {
1034         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
1035 }
1036 
1037 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2                           0x00000040
1038 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK           0x000000ff
1039 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT          0
1040 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
1041 {
1042         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
1043 }
1044 
1045 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3                           0x00000044
1046 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK          0x000000ff
1047 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT         0
1048 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
1049 {
1050         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
1051 }
1052 
1053 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4                           0x00000048
1054 
1055 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0                           0x0000004c
1056 
1057 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1                           0x00000050
1058 
1059 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2                           0x00000054
1060 
1061 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3                           0x00000058
1062 
1063 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0                         0x0000005c
1064 
1065 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1                         0x00000060
1066 
1067 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2                         0x00000064
1068 
1069 #define REG_DSI_28nm_PHY_PLL_TEST_CFG                           0x00000068
1070 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET                  0x00000001
1071 
1072 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0                           0x0000006c
1073 
1074 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1                           0x00000070
1075 
1076 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2                           0x00000074
1077 
1078 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3                           0x00000078
1079 
1080 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4                           0x0000007c
1081 
1082 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5                           0x00000080
1083 
1084 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6                           0x00000084
1085 
1086 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7                           0x00000088
1087 
1088 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8                           0x0000008c
1089 
1090 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9                           0x00000090
1091 
1092 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10                          0x00000094
1093 
1094 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11                          0x00000098
1095 
1096 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG                          0x0000009c
1097 
1098 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL                      0x000000a0
1099 
1100 #define REG_DSI_28nm_PHY_PLL_CTRL_42                            0x000000a4
1101 
1102 #define REG_DSI_28nm_PHY_PLL_CTRL_43                            0x000000a8
1103 
1104 #define REG_DSI_28nm_PHY_PLL_CTRL_44                            0x000000ac
1105 
1106 #define REG_DSI_28nm_PHY_PLL_CTRL_45                            0x000000b0
1107 
1108 #define REG_DSI_28nm_PHY_PLL_CTRL_46                            0x000000b4
1109 
1110 #define REG_DSI_28nm_PHY_PLL_CTRL_47                            0x000000b8
1111 
1112 #define REG_DSI_28nm_PHY_PLL_CTRL_48                            0x000000bc
1113 
1114 #define REG_DSI_28nm_PHY_PLL_STATUS                             0x000000c0
1115 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY                         0x00000001
1116 
1117 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0                         0x000000c4
1118 
1119 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1                         0x000000c8
1120 
1121 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2                         0x000000cc
1122 
1123 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3                         0x000000d0
1124 
1125 #define REG_DSI_28nm_PHY_PLL_CTRL_54                            0x000000d4
1126 
1127 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1128 
1129 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1130 
1131 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
1132 
1133 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
1134 
1135 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
1136 
1137 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
1138 
1139 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
1140 
1141 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
1142 
1143 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
1144 
1145 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
1146 
1147 #define REG_DSI_20nm_PHY_LNCK_CFG_0                             0x00000100
1148 
1149 #define REG_DSI_20nm_PHY_LNCK_CFG_1                             0x00000104
1150 
1151 #define REG_DSI_20nm_PHY_LNCK_CFG_2                             0x00000108
1152 
1153 #define REG_DSI_20nm_PHY_LNCK_CFG_3                             0x0000010c
1154 
1155 #define REG_DSI_20nm_PHY_LNCK_CFG_4                             0x00000110
1156 
1157 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH                     0x00000114
1158 
1159 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL                         0x00000118
1160 
1161 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0                         0x0000011c
1162 
1163 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1                         0x00000120
1164 
1165 #define REG_DSI_20nm_PHY_TIMING_CTRL_0                          0x00000140
1166 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK               0x000000ff
1167 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT              0
1168 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1169 {
1170         return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1171 }
1172 
1173 #define REG_DSI_20nm_PHY_TIMING_CTRL_1                          0x00000144
1174 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK              0x000000ff
1175 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT             0
1176 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1177 {
1178         return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1179 }
1180 
1181 #define REG_DSI_20nm_PHY_TIMING_CTRL_2                          0x00000148
1182 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK            0x000000ff
1183 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT           0
1184 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1185 {
1186         return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1187 }
1188 
1189 #define REG_DSI_20nm_PHY_TIMING_CTRL_3                          0x0000014c
1190 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8                   0x00000001
1191 
1192 #define REG_DSI_20nm_PHY_TIMING_CTRL_4                          0x00000150
1193 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK                0x000000ff
1194 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT               0
1195 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1196 {
1197         return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1198 }
1199 
1200 #define REG_DSI_20nm_PHY_TIMING_CTRL_5                          0x00000154
1201 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK                0x000000ff
1202 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT               0
1203 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1204 {
1205         return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1206 }
1207 
1208 #define REG_DSI_20nm_PHY_TIMING_CTRL_6                          0x00000158
1209 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK             0x000000ff
1210 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT            0
1211 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1212 {
1213         return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1214 }
1215 
1216 #define REG_DSI_20nm_PHY_TIMING_CTRL_7                          0x0000015c
1217 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK               0x000000ff
1218 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT              0
1219 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1220 {
1221         return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1222 }
1223 
1224 #define REG_DSI_20nm_PHY_TIMING_CTRL_8                          0x00000160
1225 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK                0x000000ff
1226 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT               0
1227 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1228 {
1229         return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1230 }
1231 
1232 #define REG_DSI_20nm_PHY_TIMING_CTRL_9                          0x00000164
1233 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK                  0x00000007
1234 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT                 0
1235 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1236 {
1237         return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1238 }
1239 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK                0x00000070
1240 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT               4
1241 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1242 {
1243         return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1244 }
1245 
1246 #define REG_DSI_20nm_PHY_TIMING_CTRL_10                         0x00000168
1247 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK                0x00000007
1248 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT               0
1249 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1250 {
1251         return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1252 }
1253 
1254 #define REG_DSI_20nm_PHY_TIMING_CTRL_11                         0x0000016c
1255 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK             0x000000ff
1256 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT            0
1257 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1258 {
1259         return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1260 }
1261 
1262 #define REG_DSI_20nm_PHY_CTRL_0                                 0x00000170
1263 
1264 #define REG_DSI_20nm_PHY_CTRL_1                                 0x00000174
1265 
1266 #define REG_DSI_20nm_PHY_CTRL_2                                 0x00000178
1267 
1268 #define REG_DSI_20nm_PHY_CTRL_3                                 0x0000017c
1269 
1270 #define REG_DSI_20nm_PHY_CTRL_4                                 0x00000180
1271 
1272 #define REG_DSI_20nm_PHY_STRENGTH_0                             0x00000184
1273 
1274 #define REG_DSI_20nm_PHY_STRENGTH_1                             0x00000188
1275 
1276 #define REG_DSI_20nm_PHY_BIST_CTRL_0                            0x000001b4
1277 
1278 #define REG_DSI_20nm_PHY_BIST_CTRL_1                            0x000001b8
1279 
1280 #define REG_DSI_20nm_PHY_BIST_CTRL_2                            0x000001bc
1281 
1282 #define REG_DSI_20nm_PHY_BIST_CTRL_3                            0x000001c0
1283 
1284 #define REG_DSI_20nm_PHY_BIST_CTRL_4                            0x000001c4
1285 
1286 #define REG_DSI_20nm_PHY_BIST_CTRL_5                            0x000001c8
1287 
1288 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL                         0x000001d4
1289 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL               0x00000001
1290 
1291 #define REG_DSI_20nm_PHY_LDO_CNTRL                              0x000001dc
1292 
1293 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0                       0x00000000
1294 
1295 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1                       0x00000004
1296 
1297 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2                       0x00000008
1298 
1299 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3                       0x0000000c
1300 
1301 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4                       0x00000010
1302 
1303 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5                       0x00000014
1304 
1305 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG                  0x00000018
1306 
1307 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0                       0x00000000
1308 
1309 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1                       0x00000004
1310 
1311 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2                       0x00000008
1312 
1313 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3                       0x0000000c
1314 
1315 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0                           0x00000010
1316 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK            0x000000f0
1317 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT           4
1318 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
1319 {
1320         return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
1321 }
1322 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK            0x000000f0
1323 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT           4
1324 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
1325 {
1326         return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
1327 }
1328 
1329 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1                           0x00000014
1330 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL                    0x00000001
1331 
1332 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL                     0x00000018
1333 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL           0x00000004
1334 
1335 #define REG_DSI_14nm_PHY_CMN_CTRL_0                             0x0000001c
1336 
1337 #define REG_DSI_14nm_PHY_CMN_CTRL_1                             0x00000020
1338 
1339 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER                         0x00000024
1340 
1341 #define REG_DSI_14nm_PHY_CMN_SW_CFG0                            0x00000028
1342 
1343 #define REG_DSI_14nm_PHY_CMN_SW_CFG1                            0x0000002c
1344 
1345 #define REG_DSI_14nm_PHY_CMN_SW_CFG2                            0x00000030
1346 
1347 #define REG_DSI_14nm_PHY_CMN_HW_CFG0                            0x00000034
1348 
1349 #define REG_DSI_14nm_PHY_CMN_HW_CFG1                            0x00000038
1350 
1351 #define REG_DSI_14nm_PHY_CMN_HW_CFG2                            0x0000003c
1352 
1353 #define REG_DSI_14nm_PHY_CMN_HW_CFG3                            0x00000040
1354 
1355 #define REG_DSI_14nm_PHY_CMN_HW_CFG4                            0x00000044
1356 
1357 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL                          0x00000048
1358 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START                    0x00000001
1359 
1360 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL                          0x0000004c
1361 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK              0x0000003f
1362 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT             0
1363 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
1364 {
1365         return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
1366 }
1367 
1368 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1369 
1370 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1371 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK                  0x000000c0
1372 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT                 6
1373 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
1374 {
1375         return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
1376 }
1377 
1378 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1379 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN                     0x00000001
1380 
1381 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1382 
1383 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1384 
1385 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1386 
1387 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1388 
1389 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1390 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK             0x000000ff
1391 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT            0
1392 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1393 {
1394         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
1395 }
1396 
1397 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1398 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK             0x000000ff
1399 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT            0
1400 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1401 {
1402         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
1403 }
1404 
1405 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1406 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK          0x000000ff
1407 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT         0
1408 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1409 {
1410         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
1411 }
1412 
1413 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1414 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK            0x000000ff
1415 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT           0
1416 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1417 {
1418         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
1419 }
1420 
1421 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1422 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK             0x000000ff
1423 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT            0
1424 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
1425 {
1426         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
1427 }
1428 
1429 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1430 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK               0x00000007
1431 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT              0
1432 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
1433 {
1434         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
1435 }
1436 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK             0x00000070
1437 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT            4
1438 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
1439 {
1440         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
1441 }
1442 
1443 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
1444 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK             0x00000007
1445 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT            0
1446 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
1447 {
1448         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
1449 }
1450 
1451 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
1452 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK          0x000000ff
1453 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT         0
1454 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1455 {
1456         return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
1457 }
1458 
1459 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
1460 
1461 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
1462 
1463 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
1464 
1465 #define REG_DSI_14nm_PHY_PLL_IE_TRIM                            0x00000000
1466 
1467 #define REG_DSI_14nm_PHY_PLL_IP_TRIM                            0x00000004
1468 
1469 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM                         0x00000010
1470 
1471 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN                        0x0000001c
1472 
1473 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET                    0x00000028
1474 
1475 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL                      0x0000002c
1476 
1477 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2                     0x00000030
1478 
1479 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3                     0x00000034
1480 
1481 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4                     0x00000038
1482 
1483 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5                     0x0000003c
1484 
1485 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1                      0x00000040
1486 
1487 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2                      0x00000044
1488 
1489 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1                        0x00000048
1490 
1491 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2                        0x0000004c
1492 
1493 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1                          0x0000005c
1494 
1495 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE                          0x00000058
1496 
1497 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1                       0x0000006c
1498 
1499 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2                       0x00000070
1500 
1501 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1                         0x00000074
1502 
1503 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2                         0x00000078
1504 
1505 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1                       0x0000007c
1506 
1507 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2                       0x00000080
1508 
1509 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3                       0x00000084
1510 
1511 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN                     0x00000088
1512 
1513 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE                       0x0000008c
1514 
1515 #define REG_DSI_14nm_PHY_PLL_DEC_START                          0x00000090
1516 
1517 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER                      0x00000094
1518 
1519 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1                       0x00000098
1520 
1521 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2                       0x0000009c
1522 
1523 #define REG_DSI_14nm_PHY_PLL_SSC_PER1                           0x000000a0
1524 
1525 #define REG_DSI_14nm_PHY_PLL_SSC_PER2                           0x000000a4
1526 
1527 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1                     0x000000a8
1528 
1529 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2                     0x000000ac
1530 
1531 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1                    0x000000b4
1532 
1533 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2                    0x000000b8
1534 
1535 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3                    0x000000bc
1536 
1537 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN                           0x000000c0
1538 
1539 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL                         0x000000c4
1540 
1541 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS              0x000000cc
1542 
1543 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1                          0x000000e8
1544 
1545 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR                         0x000000f0
1546 
1547 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET                        0x000000f4
1548 
1549 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET                        0x000000f8
1550 
1551 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET                        0x000000fc
1552 
1553 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1                           0x00000100
1554 
1555 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV                   0x00000104
1556 
1557 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP                        0x00000108
1558 
1559 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0                       0x00000000
1560 
1561 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1                       0x00000004
1562 
1563 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2                       0x00000008
1564 
1565 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3                       0x0000000c
1566 
1567 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0                           0x00000010
1568 
1569 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1                           0x00000014
1570 
1571 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL                          0x00000018
1572 
1573 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL                          0x0000001c
1574 
1575 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL                          0x00000020
1576 
1577 #define REG_DSI_10nm_PHY_CMN_CTRL_0                             0x00000024
1578 
1579 #define REG_DSI_10nm_PHY_CMN_CTRL_1                             0x00000028
1580 
1581 #define REG_DSI_10nm_PHY_CMN_CTRL_2                             0x0000002c
1582 
1583 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0                          0x00000030
1584 
1585 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1                          0x00000034
1586 
1587 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL                          0x00000038
1588 
1589 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0                         0x00000098
1590 
1591 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1                         0x0000009c
1592 
1593 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2                         0x000000a0
1594 
1595 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3                         0x000000a4
1596 
1597 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4                         0x000000a8
1598 
1599 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0                      0x000000ac
1600 
1601 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1                      0x000000b0
1602 
1603 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2                      0x000000b4
1604 
1605 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3                      0x000000b8
1606 
1607 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4                      0x000000bc
1608 
1609 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5                      0x000000c0
1610 
1611 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6                      0x000000c4
1612 
1613 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7                      0x000000c8
1614 
1615 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8                      0x000000cc
1616 
1617 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9                      0x000000d0
1618 
1619 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10                     0x000000d4
1620 
1621 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11                     0x000000d8
1622 
1623 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS                         0x000000ec
1624 
1625 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0                       0x000000f4
1626 
1627 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1                       0x000000f8
1628 
1629 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1630 
1631 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1632 
1633 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1634 
1635 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1636 
1637 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1638 
1639 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1640 
1641 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1642 
1643 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1644 
1645 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1646 
1647 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1648 
1649 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1650 
1651 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1652 
1653 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1654 
1655 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE                0x00000000
1656 
1657 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO                0x00000004
1658 
1659 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE              0x00000010
1660 
1661 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER                        0x0000001c
1662 
1663 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER                   0x00000020
1664 
1665 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES                       0x00000024
1666 
1667 #define REG_DSI_10nm_PHY_PLL_CMODE                              0x0000002c
1668 
1669 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS               0x00000030
1670 
1671 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE        0x00000054
1672 
1673 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE           0x00000064
1674 
1675 #define REG_DSI_10nm_PHY_PLL_PFILT                              0x0000007c
1676 
1677 #define REG_DSI_10nm_PHY_PLL_IFILT                              0x00000080
1678 
1679 #define REG_DSI_10nm_PHY_PLL_OUTDIV                             0x00000094
1680 
1681 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE                      0x000000a4
1682 
1683 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE                0x000000a8
1684 
1685 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO             0x000000b4
1686 
1687 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1                0x000000cc
1688 
1689 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1               0x000000d0
1690 
1691 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1               0x000000d4
1692 
1693 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1              0x000000d8
1694 
1695 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1                 0x0000010c
1696 
1697 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1                0x00000110
1698 
1699 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1                  0x00000114
1700 
1701 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1                 0x00000118
1702 
1703 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1               0x0000011c
1704 
1705 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1              0x00000120
1706 
1707 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL                        0x0000013c
1708 
1709 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE                    0x00000140
1710 
1711 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1                 0x00000144
1712 
1713 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1               0x0000014c
1714 
1715 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1                0x00000154
1716 
1717 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1          0x0000015c
1718 
1719 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1       0x00000164
1720 
1721 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE                  0x00000180
1722 
1723 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY                     0x00000184
1724 
1725 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS                    0x0000018c
1726 
1727 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE                  0x000001a0
1728 
1729 
1730 #endif /* DSI_XML */