This source file includes following definitions.
- __offset_CLK
- REG_MMSS_CC_CLK
- REG_MMSS_CC_CLK_CC
- MMSS_CC_CLK_CC_MND_MODE
- MMSS_CC_CLK_CC_PMXO_SEL
- REG_MMSS_CC_CLK_MD
- MMSS_CC_CLK_MD_D
- MMSS_CC_CLK_MD_M
- REG_MMSS_CC_CLK_NS
- MMSS_CC_CLK_NS_SRC
- MMSS_CC_CLK_NS_PRE_DIV_FUNC
- MMSS_CC_CLK_NS_VAL
1 #ifndef MMSS_CC_XML
2 #define MMSS_CC_XML
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49 enum mmss_cc_clk {
50 CLK = 0,
51 PCLK = 1,
52 };
53
54 #define REG_MMSS_CC_AHB 0x00000008
55
56 static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
57 {
58 switch (idx) {
59 case CLK: return 0x0000004c;
60 case PCLK: return 0x00000130;
61 default: return INVALID_IDX(idx);
62 }
63 }
64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
65
66 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
67 #define MMSS_CC_CLK_CC_CLK_EN 0x00000001
68 #define MMSS_CC_CLK_CC_ROOT_EN 0x00000004
69 #define MMSS_CC_CLK_CC_MND_EN 0x00000020
70 #define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0
71 #define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6
72 static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
73 {
74 return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
75 }
76 #define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300
77 #define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8
78 static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
79 {
80 return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
81 }
82
83 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
84 #define MMSS_CC_CLK_MD_D__MASK 0x000000ff
85 #define MMSS_CC_CLK_MD_D__SHIFT 0
86 static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
87 {
88 return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
89 }
90 #define MMSS_CC_CLK_MD_M__MASK 0x0000ff00
91 #define MMSS_CC_CLK_MD_M__SHIFT 8
92 static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
93 {
94 return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
95 }
96
97 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
98 #define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f
99 #define MMSS_CC_CLK_NS_SRC__SHIFT 0
100 static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
101 {
102 return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
103 }
104 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000
105 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12
106 static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
107 {
108 return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
109 }
110 #define MMSS_CC_CLK_NS_VAL__MASK 0xff000000
111 #define MMSS_CC_CLK_NS_VAL__SHIFT 24
112 static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
113 {
114 return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
115 }
116
117 #define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094
118
119 #define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4
120
121 #define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264
122
123
124 #endif