root/drivers/gpu/drm/msm/dsi/dsi_cfg.c

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DEFINITIONS

This source file includes following definitions.
  1. msm_dsi_cfg_get

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5 
   6 #include "dsi_cfg.h"
   7 
   8 static const char * const dsi_v2_bus_clk_names[] = {
   9         "core_mmss", "iface", "bus",
  10 };
  11 
  12 static const struct msm_dsi_config apq8064_dsi_cfg = {
  13         .io_offset = 0,
  14         .reg_cfg = {
  15                 .num = 3,
  16                 .regs = {
  17                         {"vdda", 100000, 100},  /* 1.2 V */
  18                         {"avdd", 10000, 100},   /* 3.0 V */
  19                         {"vddio", 100000, 100}, /* 1.8 V */
  20                 },
  21         },
  22         .bus_clk_names = dsi_v2_bus_clk_names,
  23         .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names),
  24         .io_start = { 0x4700000, 0x5800000 },
  25         .num_dsi = 2,
  26 };
  27 
  28 static const char * const dsi_6g_bus_clk_names[] = {
  29         "mdp_core", "iface", "bus", "core_mmss",
  30 };
  31 
  32 static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
  33         .io_offset = DSI_6G_REG_SHIFT,
  34         .reg_cfg = {
  35                 .num = 4,
  36                 .regs = {
  37                         {"gdsc", -1, -1},
  38                         {"vdd", 150000, 100},   /* 3.0 V */
  39                         {"vdda", 100000, 100},  /* 1.2 V */
  40                         {"vddio", 100000, 100}, /* 1.8 V */
  41                 },
  42         },
  43         .bus_clk_names = dsi_6g_bus_clk_names,
  44         .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
  45         .io_start = { 0xfd922800, 0xfd922b00 },
  46         .num_dsi = 2,
  47 };
  48 
  49 static const char * const dsi_8916_bus_clk_names[] = {
  50         "mdp_core", "iface", "bus",
  51 };
  52 
  53 static const struct msm_dsi_config msm8916_dsi_cfg = {
  54         .io_offset = DSI_6G_REG_SHIFT,
  55         .reg_cfg = {
  56                 .num = 3,
  57                 .regs = {
  58                         {"gdsc", -1, -1},
  59                         {"vdda", 100000, 100},  /* 1.2 V */
  60                         {"vddio", 100000, 100}, /* 1.8 V */
  61                 },
  62         },
  63         .bus_clk_names = dsi_8916_bus_clk_names,
  64         .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
  65         .io_start = { 0x1a98000 },
  66         .num_dsi = 1,
  67 };
  68 
  69 static const struct msm_dsi_config msm8994_dsi_cfg = {
  70         .io_offset = DSI_6G_REG_SHIFT,
  71         .reg_cfg = {
  72                 .num = 7,
  73                 .regs = {
  74                         {"gdsc", -1, -1},
  75                         {"vdda", 100000, 100},  /* 1.25 V */
  76                         {"vddio", 100000, 100}, /* 1.8 V */
  77                         {"vcca", 10000, 100},   /* 1.0 V */
  78                         {"vdd", 100000, 100},   /* 1.8 V */
  79                         {"lab_reg", -1, -1},
  80                         {"ibb_reg", -1, -1},
  81                 },
  82         },
  83         .bus_clk_names = dsi_6g_bus_clk_names,
  84         .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
  85         .io_start = { 0xfd998000, 0xfd9a0000 },
  86         .num_dsi = 2,
  87 };
  88 
  89 /*
  90  * TODO: core_mmss_clk fails to enable for some reason, but things work fine
  91  * without it too. Figure out why it doesn't enable and uncomment below
  92  */
  93 static const char * const dsi_8996_bus_clk_names[] = {
  94         "mdp_core", "iface", "bus", /* "core_mmss", */
  95 };
  96 
  97 static const struct msm_dsi_config msm8996_dsi_cfg = {
  98         .io_offset = DSI_6G_REG_SHIFT,
  99         .reg_cfg = {
 100                 .num = 2,
 101                 .regs = {
 102                         {"vdda", 18160, 1 },    /* 1.25 V */
 103                         {"vcca", 17000, 32 },   /* 0.925 V */
 104                         {"vddio", 100000, 100 },/* 1.8 V */
 105                 },
 106         },
 107         .bus_clk_names = dsi_8996_bus_clk_names,
 108         .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names),
 109         .io_start = { 0x994000, 0x996000 },
 110         .num_dsi = 2,
 111 };
 112 
 113 static const char * const dsi_msm8998_bus_clk_names[] = {
 114         "iface", "bus", "core",
 115 };
 116 
 117 static const struct msm_dsi_config msm8998_dsi_cfg = {
 118         .io_offset = DSI_6G_REG_SHIFT,
 119         .reg_cfg = {
 120                 .num = 2,
 121                 .regs = {
 122                         {"vdd", 367000, 16 },   /* 0.9 V */
 123                         {"vdda", 62800, 2 },    /* 1.2 V */
 124                 },
 125         },
 126         .bus_clk_names = dsi_msm8998_bus_clk_names,
 127         .num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names),
 128         .io_start = { 0xc994000, 0xc996000 },
 129         .num_dsi = 2,
 130 };
 131 
 132 static const char * const dsi_sdm845_bus_clk_names[] = {
 133         "iface", "bus",
 134 };
 135 
 136 static const struct msm_dsi_config sdm845_dsi_cfg = {
 137         .io_offset = DSI_6G_REG_SHIFT,
 138         .reg_cfg = {
 139                 .num = 1,
 140                 .regs = {
 141                         {"vdda", 21800, 4 },    /* 1.2 V */
 142                 },
 143         },
 144         .bus_clk_names = dsi_sdm845_bus_clk_names,
 145         .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
 146         .io_start = { 0xae94000, 0xae96000 },
 147         .num_dsi = 2,
 148 };
 149 
 150 const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
 151         .link_clk_enable = dsi_link_clk_enable_v2,
 152         .link_clk_disable = dsi_link_clk_disable_v2,
 153         .clk_init_ver = dsi_clk_init_v2,
 154         .tx_buf_alloc = dsi_tx_buf_alloc_v2,
 155         .tx_buf_get = dsi_tx_buf_get_v2,
 156         .tx_buf_put = NULL,
 157         .dma_base_get = dsi_dma_base_get_v2,
 158         .calc_clk_rate = dsi_calc_clk_rate_v2,
 159 };
 160 
 161 const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
 162         .link_clk_enable = dsi_link_clk_enable_6g,
 163         .link_clk_disable = dsi_link_clk_disable_6g,
 164         .clk_init_ver = NULL,
 165         .tx_buf_alloc = dsi_tx_buf_alloc_6g,
 166         .tx_buf_get = dsi_tx_buf_get_6g,
 167         .tx_buf_put = dsi_tx_buf_put_6g,
 168         .dma_base_get = dsi_dma_base_get_6g,
 169         .calc_clk_rate = dsi_calc_clk_rate_6g,
 170 };
 171 
 172 const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
 173         .link_clk_enable = dsi_link_clk_enable_6g,
 174         .link_clk_disable = dsi_link_clk_disable_6g,
 175         .clk_init_ver = dsi_clk_init_6g_v2,
 176         .tx_buf_alloc = dsi_tx_buf_alloc_6g,
 177         .tx_buf_get = dsi_tx_buf_get_6g,
 178         .tx_buf_put = dsi_tx_buf_put_6g,
 179         .dma_base_get = dsi_dma_base_get_6g,
 180         .calc_clk_rate = dsi_calc_clk_rate_6g,
 181 };
 182 
 183 static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
 184         {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
 185                 &apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
 186         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
 187                 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
 188         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
 189                 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
 190         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
 191                 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
 192         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
 193                 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
 194         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
 195                 &msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
 196         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
 197                 &msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
 198         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
 199                 &msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
 200         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0,
 201                 &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 202         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
 203                 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 204 };
 205 
 206 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
 207 {
 208         const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
 209         int i;
 210 
 211         for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
 212                 if ((dsi_cfg_handlers[i].major == major) &&
 213                         (dsi_cfg_handlers[i].minor == minor)) {
 214                         cfg_hnd = &dsi_cfg_handlers[i];
 215                         break;
 216                 }
 217         }
 218 
 219         return cfg_hnd;
 220 }
 221 

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