root/drivers/gpu/drm/msm/adreno/a6xx_gmu.h

INCLUDED FROM

DEFINITIONS

1. gmu_read
2. gmu_write
3. gmu_rmw
4. gmu_read64

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3 
   4 #ifndef _A6XX_GMU_H_
   5 #define _A6XX_GMU_H_
   6 
   7 #include <linux/iopoll.h>
   8 #include <linux/interrupt.h>
   9 #include "msm_drv.h"
  10 #include "a6xx_hfi.h"
  11 
  12 struct a6xx_gmu_bo {
  13         void *virt;
  14         size_t size;
  15         u64 iova;
  16         struct page **pages;
  17 };
  18 
  19 /*
  20  * These define the different GMU wake up options - these define how both the
  21  * CPU and the GMU bring up the hardware
  22  */
  23 
  24 /* THe GMU has already been booted and the rentention registers are active */
  25 #define GMU_WARM_BOOT 0
  26 
  27 /* the GMU is coming up for the first time or back from a power collapse */
  28 #define GMU_COLD_BOOT 1
  29 
  30 /*
  31  * These define the level of control that the GMU has - the higher the number
  32  * the more things that the GMU hardware controls on its own.
  33  */
  34 
  35 /* The GMU does not do any idle state management */
  36 #define GMU_IDLE_STATE_ACTIVE 0
  37 
  38 /* The GMU manages SPTP power collapse */
  39 #define GMU_IDLE_STATE_SPTP 2
  40 
  41 /* The GMU does automatic IFPC (intra-frame power collapse) */
  42 #define GMU_IDLE_STATE_IFPC 3
  43 
  44 struct a6xx_gmu {
  45         struct device *dev;
  46 
  47         void * __iomem mmio;
  48 
  49         int hfi_irq;
  50         int gmu_irq;
  51 
  52         struct iommu_domain *domain;
  53         u64 uncached_iova_base;
  54 
  55         struct device *gxpd;
  56 
  57         int idle_level;
  58 
  59         struct a6xx_gmu_bo *hfi;
  60         struct a6xx_gmu_bo *debug;
  61 
  62         int nr_clocks;
  63         struct clk_bulk_data *clocks;
  64         struct clk *core_clk;
  65 
  66         int nr_gpu_freqs;
  67         unsigned long gpu_freqs[16];
  68         u32 gx_arc_votes[16];
  69 
  70         int nr_gmu_freqs;
  71         unsigned long gmu_freqs[4];
  72         u32 cx_arc_votes[4];
  73 
  74         unsigned long freq;
  75 
  76         struct a6xx_hfi_queue queues[2];
  77 
  78         bool initialized;
  79         bool hung;
  80 };
  81 
  82 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
  83 {
  84         return msm_readl(gmu->mmio + (offset << 2));
  85 }
  86 
  87 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
  88 {
  89         return msm_writel(value, gmu->mmio + (offset << 2));
  90 }
  91 
  92 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
  93 {
  94         u32 val = gmu_read(gmu, reg);
  95 
  96         val &= ~mask;
  97 
  98         gmu_write(gmu, reg, val | or);
  99 }
 100 
 101 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
 102 {
 103         u64 val;
 104 
 105         val = (u64) msm_readl(gmu->mmio + (lo << 2));
 106         val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
 107 
 108         return val;
 109 }
 110 
 111 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
 112         readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
 113                 interval, timeout)
 114 
 115 /*
 116  * These are the available OOB (out of band requests) to the GMU where "out of
 117  * band" means that the CPU talks to the GMU directly and not through HFI.
 118  * Normally this works by writing a ITCM/DTCM register and then triggering a
 119  * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
 120  * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
 121  *
 122  * These are used to force the GMU/GPU to stay on during a critical sequence or
 123  * for hardware workarounds.
 124  */
 125 
 126 enum a6xx_gmu_oob_state {
 127         GMU_OOB_BOOT_SLUMBER = 0,
 128         GMU_OOB_GPU_SET,
 129         GMU_OOB_DCVS_SET,
 130 };
 131 
 132 /* These are the interrupt / ack bits for each OOB request that are set
 133  * in a6xx_gmu_set_oob and a6xx_clear_oob
 134  */
 135 
 136 /*
 137  * Let the GMU know that a boot or slumber operation has started. The value in
 138  * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
 139  * doing
 140  */
 141 #define GMU_OOB_BOOT_SLUMBER_REQUEST    22
 142 #define GMU_OOB_BOOT_SLUMBER_ACK        30
 143 #define GMU_OOB_BOOT_SLUMBER_CLEAR      30
 144 
 145 /*
 146  * Set a new power level for the GPU when the CPU is doing frequency scaling
 147  */
 148 #define GMU_OOB_DCVS_REQUEST    23
 149 #define GMU_OOB_DCVS_ACK        31
 150 #define GMU_OOB_DCVS_CLEAR      31
 151 
 152 /*
 153  * Let the GMU know to not turn off any GPU registers while the CPU is in a
 154  * critical section
 155  */
 156 #define GMU_OOB_GPU_SET_REQUEST 16
 157 #define GMU_OOB_GPU_SET_ACK     24
 158 #define GMU_OOB_GPU_SET_CLEAR   24
 159 
 160 
 161 void a6xx_hfi_init(struct a6xx_gmu *gmu);
 162 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
 163 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
 164 
 165 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
 166 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
 167 
 168 #endif