root/drivers/gpu/drm/msm/adreno/a6xx_gpu.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3 
   4 #ifndef __A6XX_GPU_H__
   5 #define __A6XX_GPU_H__
   6 
   7 
   8 #include "adreno_gpu.h"
   9 #include "a6xx.xml.h"
  10 
  11 #include "a6xx_gmu.h"
  12 
  13 extern bool hang_debug;
  14 
  15 struct a6xx_gpu {
  16         struct adreno_gpu base;
  17 
  18         struct drm_gem_object *sqe_bo;
  19         uint64_t sqe_iova;
  20 
  21         struct msm_ringbuffer *cur_ring;
  22 
  23         struct a6xx_gmu gmu;
  24 };
  25 
  26 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
  27 
  28 /*
  29  * Given a register and a count, return a value to program into
  30  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
  31  * registers starting at _reg.
  32  */
  33 #define A6XX_PROTECT_RW(_reg, _len) \
  34         ((1 << 31) | \
  35         (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
  36 
  37 /*
  38  * Same as above, but allow reads over the range. For areas of mixed use (such
  39  * as performance counters) this allows us to protect a much larger range with a
  40  * single register
  41  */
  42 #define A6XX_PROTECT_RDONLY(_reg, _len) \
  43         ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
  44 
  45 
  46 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
  47 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
  48 
  49 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
  50 
  51 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
  52 
  53 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
  54 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
  55 
  56 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
  57 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
  58 
  59 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq);
  60 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
  61 
  62 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
  63                 struct drm_printer *p);
  64 
  65 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
  66 int a6xx_gpu_state_put(struct msm_gpu_state *state);
  67 
  68 #endif /* __A6XX_GPU_H__ */