root/drivers/gpu/drm/msm/adreno/a6xx.xml.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. REG_A6XX_CP_SCRATCH
  2. REG_A6XX_CP_SCRATCH_REG
  3. REG_A6XX_CP_PROTECT
  4. REG_A6XX_CP_PROTECT_REG
  5. A6XX_CP_PROTECT_REG_BASE_ADDR
  6. A6XX_CP_PROTECT_REG_MASK_LEN
  7. A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX
  8. A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL
  9. A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN
  10. A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU
  11. A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT
  12. A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE
  13. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0
  14. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1
  15. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2
  16. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3
  17. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4
  18. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5
  19. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6
  20. A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7
  21. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8
  22. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9
  23. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10
  24. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11
  25. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12
  26. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13
  27. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14
  28. A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15
  29. A6XX_UCHE_CLIENT_PF_PERFSEL
  30. A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL
  31. A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL
  32. A6XX_RB_WINDOW_OFFSET2_X
  33. A6XX_RB_WINDOW_OFFSET2_Y
  34. A6XX_SP_WINDOW_OFFSET_X
  35. A6XX_SP_WINDOW_OFFSET_Y
  36. A6XX_SP_TP_WINDOW_OFFSET_X
  37. A6XX_SP_TP_WINDOW_OFFSET_Y
  38. A6XX_GRAS_BIN_CONTROL_BINW
  39. A6XX_GRAS_BIN_CONTROL_BINH
  40. A6XX_RB_BIN_CONTROL2_BINW
  41. A6XX_RB_BIN_CONTROL2_BINH
  42. A6XX_VSC_BIN_SIZE_WIDTH
  43. A6XX_VSC_BIN_SIZE_HEIGHT
  44. A6XX_VSC_BIN_COUNT_NX
  45. A6XX_VSC_BIN_COUNT_NY
  46. REG_A6XX_VSC_PIPE_CONFIG
  47. REG_A6XX_VSC_PIPE_CONFIG_REG
  48. A6XX_VSC_PIPE_CONFIG_REG_X
  49. A6XX_VSC_PIPE_CONFIG_REG_Y
  50. A6XX_VSC_PIPE_CONFIG_REG_W
  51. A6XX_VSC_PIPE_CONFIG_REG_H
  52. A6XX_VSC_PIPE_DATA2_ARRAY_PITCH
  53. A6XX_VSC_PIPE_DATA_ARRAY_PITCH
  54. REG_A6XX_VSC_SIZE
  55. REG_A6XX_VSC_SIZE_REG
  56. A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ
  57. A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT
  58. A6XX_GRAS_CL_VPORT_XOFFSET_0
  59. A6XX_GRAS_CL_VPORT_XSCALE_0
  60. A6XX_GRAS_CL_VPORT_YOFFSET_0
  61. A6XX_GRAS_CL_VPORT_YSCALE_0
  62. A6XX_GRAS_CL_VPORT_ZOFFSET_0
  63. A6XX_GRAS_CL_VPORT_ZSCALE_0
  64. A6XX_GRAS_SU_CNTL_LINEHALFWIDTH
  65. A6XX_GRAS_SU_POINT_MINMAX_MIN
  66. A6XX_GRAS_SU_POINT_MINMAX_MAX
  67. A6XX_GRAS_SU_POINT_SIZE
  68. A6XX_GRAS_SU_POLY_OFFSET_SCALE
  69. A6XX_GRAS_SU_POLY_OFFSET_OFFSET
  70. A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP
  71. A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT
  72. A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES
  73. A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES
  74. A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X
  75. A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y
  76. A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X
  77. A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y
  78. A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X
  79. A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y
  80. A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X
  81. A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y
  82. A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X
  83. A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y
  84. A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X
  85. A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y
  86. A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT
  87. A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH
  88. A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH
  89. A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT
  90. A6XX_GRAS_2D_SRC_TL_X_X
  91. A6XX_GRAS_2D_SRC_BR_X_X
  92. A6XX_GRAS_2D_SRC_TL_Y_Y
  93. A6XX_GRAS_2D_SRC_BR_Y_Y
  94. A6XX_GRAS_2D_DST_TL_X
  95. A6XX_GRAS_2D_DST_TL_Y
  96. A6XX_GRAS_2D_DST_BR_X
  97. A6XX_GRAS_2D_DST_BR_Y
  98. A6XX_GRAS_RESOLVE_CNTL_1_X
  99. A6XX_GRAS_RESOLVE_CNTL_1_Y
  100. A6XX_GRAS_RESOLVE_CNTL_2_X
  101. A6XX_GRAS_RESOLVE_CNTL_2_Y
  102. A6XX_RB_BIN_CONTROL_BINW
  103. A6XX_RB_BIN_CONTROL_BINH
  104. A6XX_RB_RENDER_CNTL_FLAG_MRTS
  105. A6XX_RB_RAS_MSAA_CNTL_SAMPLES
  106. A6XX_RB_DEST_MSAA_CNTL_SAMPLES
  107. A6XX_RB_FS_OUTPUT_CNTL1_MRT
  108. A6XX_RB_RENDER_COMPONENTS_RT0
  109. A6XX_RB_RENDER_COMPONENTS_RT1
  110. A6XX_RB_RENDER_COMPONENTS_RT2
  111. A6XX_RB_RENDER_COMPONENTS_RT3
  112. A6XX_RB_RENDER_COMPONENTS_RT4
  113. A6XX_RB_RENDER_COMPONENTS_RT5
  114. A6XX_RB_RENDER_COMPONENTS_RT6
  115. A6XX_RB_RENDER_COMPONENTS_RT7
  116. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0
  117. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1
  118. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2
  119. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3
  120. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4
  121. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5
  122. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6
  123. A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7
  124. REG_A6XX_RB_MRT
  125. REG_A6XX_RB_MRT_CONTROL
  126. A6XX_RB_MRT_CONTROL_ROP_CODE
  127. A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE
  128. REG_A6XX_RB_MRT_BLEND_CONTROL
  129. A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR
  130. A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE
  131. A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR
  132. A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR
  133. A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE
  134. A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR
  135. REG_A6XX_RB_MRT_BUF_INFO
  136. A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT
  137. A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE
  138. A6XX_RB_MRT_BUF_INFO_COLOR_SWAP
  139. REG_A6XX_RB_MRT_PITCH
  140. A6XX_RB_MRT_PITCH
  141. REG_A6XX_RB_MRT_ARRAY_PITCH
  142. A6XX_RB_MRT_ARRAY_PITCH
  143. REG_A6XX_RB_MRT_BASE_LO
  144. REG_A6XX_RB_MRT_BASE_HI
  145. REG_A6XX_RB_MRT_BASE_GMEM
  146. A6XX_RB_BLEND_RED_F32
  147. A6XX_RB_BLEND_GREEN_F32
  148. A6XX_RB_BLEND_BLUE_F32
  149. A6XX_RB_BLEND_ALPHA_F32
  150. A6XX_RB_ALPHA_CONTROL_ALPHA_REF
  151. A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC
  152. A6XX_RB_BLEND_CNTL_ENABLE_BLEND
  153. A6XX_RB_BLEND_CNTL_SAMPLE_MASK
  154. A6XX_RB_DEPTH_CNTL_ZFUNC
  155. A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT
  156. A6XX_RB_DEPTH_BUFFER_PITCH
  157. A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH
  158. A6XX_RB_STENCIL_CONTROL_FUNC
  159. A6XX_RB_STENCIL_CONTROL_FAIL
  160. A6XX_RB_STENCIL_CONTROL_ZPASS
  161. A6XX_RB_STENCIL_CONTROL_ZFAIL
  162. A6XX_RB_STENCIL_CONTROL_FUNC_BF
  163. A6XX_RB_STENCIL_CONTROL_FAIL_BF
  164. A6XX_RB_STENCIL_CONTROL_ZPASS_BF
  165. A6XX_RB_STENCIL_CONTROL_ZFAIL_BF
  166. A6XX_RB_STENCIL_BUFFER_PITCH
  167. A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH
  168. A6XX_RB_STENCILREF_REF
  169. A6XX_RB_STENCILREF_BFREF
  170. A6XX_RB_STENCILMASK_MASK
  171. A6XX_RB_STENCILMASK_BFMASK
  172. A6XX_RB_STENCILWRMASK_WRMASK
  173. A6XX_RB_STENCILWRMASK_BFWRMASK
  174. A6XX_RB_WINDOW_OFFSET_X
  175. A6XX_RB_WINDOW_OFFSET_Y
  176. A6XX_RB_BLIT_SCISSOR_TL_X
  177. A6XX_RB_BLIT_SCISSOR_TL_Y
  178. A6XX_RB_BLIT_SCISSOR_BR_X
  179. A6XX_RB_BLIT_SCISSOR_BR_Y
  180. A6XX_RB_MSAA_CNTL_SAMPLES
  181. A6XX_RB_BLIT_DST_INFO_TILE_MODE
  182. A6XX_RB_BLIT_DST_INFO_SAMPLES
  183. A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT
  184. A6XX_RB_BLIT_DST_INFO_COLOR_SWAP
  185. A6XX_RB_BLIT_DST_PITCH
  186. A6XX_RB_BLIT_DST_ARRAY_PITCH
  187. A6XX_RB_BLIT_INFO_CLEAR_MASK
  188. REG_A6XX_RB_MRT_FLAG_BUFFER
  189. REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO
  190. REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI
  191. REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH
  192. A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH
  193. A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH
  194. A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT
  195. A6XX_RB_2D_DST_INFO_COLOR_FORMAT
  196. A6XX_RB_2D_DST_INFO_TILE_MODE
  197. A6XX_RB_2D_DST_INFO_COLOR_SWAP
  198. A6XX_RB_2D_DST_SIZE_PITCH
  199. REG_A6XX_VPC_VARYING_INTERP
  200. REG_A6XX_VPC_VARYING_INTERP_MODE
  201. REG_A6XX_VPC_VARYING_PS_REPL
  202. REG_A6XX_VPC_VARYING_PS_REPL_MODE
  203. REG_A6XX_VPC_VAR
  204. REG_A6XX_VPC_VAR_DISABLE
  205. A6XX_VPC_SO_PROG_A_BUF
  206. A6XX_VPC_SO_PROG_A_OFF
  207. A6XX_VPC_SO_PROG_B_BUF
  208. A6XX_VPC_SO_PROG_B_OFF
  209. REG_A6XX_VPC_SO
  210. REG_A6XX_VPC_SO_BUFFER_BASE_LO
  211. REG_A6XX_VPC_SO_BUFFER_BASE_HI
  212. REG_A6XX_VPC_SO_BUFFER_SIZE
  213. REG_A6XX_VPC_SO_NCOMP
  214. REG_A6XX_VPC_SO_BUFFER_OFFSET
  215. REG_A6XX_VPC_SO_FLUSH_BASE_LO
  216. REG_A6XX_VPC_SO_FLUSH_BASE_HI
  217. A6XX_VPC_PACK_STRIDE_IN_VPC
  218. A6XX_VPC_PACK_NUMNONPOSVAR
  219. A6XX_VPC_PACK_PSIZELOC
  220. A6XX_VPC_CNTL_0_NUMNONPOSVAR
  221. A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC
  222. A6XX_VFD_CONTROL_0_VTXCNT
  223. A6XX_VFD_CONTROL_1_REGID4VTX
  224. A6XX_VFD_CONTROL_1_REGID4INST
  225. A6XX_VFD_CONTROL_1_REGID4PRIMID
  226. A6XX_VFD_CONTROL_2_REGID_PATCHID
  227. A6XX_VFD_CONTROL_3_REGID_PATCHID
  228. A6XX_VFD_CONTROL_3_REGID_TESSX
  229. A6XX_VFD_CONTROL_3_REGID_TESSY
  230. REG_A6XX_VFD_FETCH
  231. REG_A6XX_VFD_FETCH_BASE_LO
  232. REG_A6XX_VFD_FETCH_BASE_HI
  233. REG_A6XX_VFD_FETCH_SIZE
  234. REG_A6XX_VFD_FETCH_STRIDE
  235. REG_A6XX_VFD_DECODE
  236. REG_A6XX_VFD_DECODE_INSTR
  237. A6XX_VFD_DECODE_INSTR_IDX
  238. A6XX_VFD_DECODE_INSTR_FORMAT
  239. A6XX_VFD_DECODE_INSTR_SWAP
  240. REG_A6XX_VFD_DECODE_STEP_RATE
  241. REG_A6XX_VFD_DEST_CNTL
  242. REG_A6XX_VFD_DEST_CNTL_INSTR
  243. A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK
  244. A6XX_VFD_DEST_CNTL_INSTR_REGID
  245. A6XX_SP_PRIMITIVE_CNTL_VSOUT
  246. REG_A6XX_SP_VS_OUT
  247. REG_A6XX_SP_VS_OUT_REG
  248. A6XX_SP_VS_OUT_REG_A_REGID
  249. A6XX_SP_VS_OUT_REG_A_COMPMASK
  250. A6XX_SP_VS_OUT_REG_B_REGID
  251. A6XX_SP_VS_OUT_REG_B_COMPMASK
  252. REG_A6XX_SP_VS_VPC_DST
  253. REG_A6XX_SP_VS_VPC_DST_REG
  254. A6XX_SP_VS_VPC_DST_REG_OUTLOC0
  255. A6XX_SP_VS_VPC_DST_REG_OUTLOC1
  256. A6XX_SP_VS_VPC_DST_REG_OUTLOC2
  257. A6XX_SP_VS_VPC_DST_REG_OUTLOC3
  258. A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT
  259. A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT
  260. A6XX_SP_VS_CTRL_REG0_BRANCHSTACK
  261. A6XX_SP_VS_CTRL_REG0_THREADSIZE
  262. A6XX_SP_VS_CONFIG_NTEX
  263. A6XX_SP_VS_CONFIG_NSAMP
  264. A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT
  265. A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT
  266. A6XX_SP_HS_CTRL_REG0_BRANCHSTACK
  267. A6XX_SP_HS_CTRL_REG0_THREADSIZE
  268. A6XX_SP_HS_CONFIG_NTEX
  269. A6XX_SP_HS_CONFIG_NSAMP
  270. A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT
  271. A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT
  272. A6XX_SP_DS_CTRL_REG0_BRANCHSTACK
  273. A6XX_SP_DS_CTRL_REG0_THREADSIZE
  274. A6XX_SP_DS_CONFIG_NTEX
  275. A6XX_SP_DS_CONFIG_NSAMP
  276. A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT
  277. A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT
  278. A6XX_SP_GS_CTRL_REG0_BRANCHSTACK
  279. A6XX_SP_GS_CTRL_REG0_THREADSIZE
  280. A6XX_SP_GS_CONFIG_NTEX
  281. A6XX_SP_GS_CONFIG_NSAMP
  282. A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT
  283. A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT
  284. A6XX_SP_FS_CTRL_REG0_BRANCHSTACK
  285. A6XX_SP_FS_CTRL_REG0_THREADSIZE
  286. A6XX_SP_FS_RENDER_COMPONENTS_RT0
  287. A6XX_SP_FS_RENDER_COMPONENTS_RT1
  288. A6XX_SP_FS_RENDER_COMPONENTS_RT2
  289. A6XX_SP_FS_RENDER_COMPONENTS_RT3
  290. A6XX_SP_FS_RENDER_COMPONENTS_RT4
  291. A6XX_SP_FS_RENDER_COMPONENTS_RT5
  292. A6XX_SP_FS_RENDER_COMPONENTS_RT6
  293. A6XX_SP_FS_RENDER_COMPONENTS_RT7
  294. A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID
  295. A6XX_SP_FS_OUTPUT_CNTL1_MRT
  296. REG_A6XX_SP_FS_MRT
  297. REG_A6XX_SP_FS_MRT_REG
  298. A6XX_SP_FS_MRT_REG_COLOR_FORMAT
  299. REG_A6XX_SP_FS_OUTPUT
  300. REG_A6XX_SP_FS_OUTPUT_REG
  301. A6XX_SP_FS_OUTPUT_REG_REGID
  302. A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT
  303. A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT
  304. A6XX_SP_CS_CTRL_REG0_BRANCHSTACK
  305. A6XX_SP_CS_CTRL_REG0_THREADSIZE
  306. A6XX_SP_FS_CONFIG_NTEX
  307. A6XX_SP_FS_CONFIG_NSAMP
  308. A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES
  309. A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES
  310. A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT
  311. A6XX_SP_PS_2D_SRC_INFO_TILE_MODE
  312. A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP
  313. A6XX_SP_PS_2D_SRC_SIZE_WIDTH
  314. A6XX_SP_PS_2D_SRC_SIZE_HEIGHT
  315. A6XX_SP_PS_2D_SRC_PITCH_PITCH
  316. A6XX_HLSQ_VS_CNTL_CONSTLEN
  317. A6XX_HLSQ_HS_CNTL_CONSTLEN
  318. A6XX_HLSQ_DS_CNTL_CONSTLEN
  319. A6XX_HLSQ_GS_CNTL_CONSTLEN
  320. A6XX_HLSQ_CONTROL_2_REG_FACEREGID
  321. A6XX_HLSQ_CONTROL_2_REG_SAMPLEID
  322. A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK
  323. A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID
  324. A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID
  325. A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID
  326. A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM
  327. A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX
  328. A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY
  329. A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ
  330. A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X
  331. A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X
  332. A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y
  333. A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y
  334. A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z
  335. A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z
  336. A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID
  337. A6XX_HLSQ_CS_CNTL_0_UNK0
  338. A6XX_HLSQ_CS_CNTL_0_UNK1
  339. A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID
  340. A6XX_HLSQ_FS_CNTL_CONSTLEN
  341. A6XX_TEX_SAMP_0_XY_MAG
  342. A6XX_TEX_SAMP_0_XY_MIN
  343. A6XX_TEX_SAMP_0_WRAP_S
  344. A6XX_TEX_SAMP_0_WRAP_T
  345. A6XX_TEX_SAMP_0_WRAP_R
  346. A6XX_TEX_SAMP_0_ANISO
  347. A6XX_TEX_SAMP_0_LOD_BIAS
  348. A6XX_TEX_SAMP_1_COMPARE_FUNC
  349. A6XX_TEX_SAMP_1_MAX_LOD
  350. A6XX_TEX_SAMP_1_MIN_LOD
  351. A6XX_TEX_SAMP_2_BCOLOR_OFFSET
  352. A6XX_TEX_CONST_0_TILE_MODE
  353. A6XX_TEX_CONST_0_SWIZ_X
  354. A6XX_TEX_CONST_0_SWIZ_Y
  355. A6XX_TEX_CONST_0_SWIZ_Z
  356. A6XX_TEX_CONST_0_SWIZ_W
  357. A6XX_TEX_CONST_0_MIPLVLS
  358. A6XX_TEX_CONST_0_SAMPLES
  359. A6XX_TEX_CONST_0_FMT
  360. A6XX_TEX_CONST_0_SWAP
  361. A6XX_TEX_CONST_1_WIDTH
  362. A6XX_TEX_CONST_1_HEIGHT
  363. A6XX_TEX_CONST_2_FETCHSIZE
  364. A6XX_TEX_CONST_2_PITCH
  365. A6XX_TEX_CONST_2_TYPE
  366. A6XX_TEX_CONST_3_ARRAY_PITCH
  367. A6XX_TEX_CONST_4_BASE_LO
  368. A6XX_TEX_CONST_5_BASE_HI
  369. A6XX_TEX_CONST_5_DEPTH
  370. A6XX_TEX_CONST_7_FLAG_LO
  371. A6XX_TEX_CONST_8_FLAG_HI
  372. A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX
  373. A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL
  374. A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN
  375. A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU
  376. A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT
  377. A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE
  378. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0
  379. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1
  380. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2
  381. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3
  382. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4
  383. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5
  384. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6
  385. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7
  386. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8
  387. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9
  388. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10
  389. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11
  390. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12
  391. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13
  392. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14
  393. A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15
   1 #ifndef A6XX_XML
   2 #define A6XX_XML
   3 
   4 /* Autogenerated file, DO NOT EDIT manually!
   5 
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9 
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
  12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
  13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
  14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14201 bytes, from 2018-12-02 17:29:54)
  15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-02 17:29:54)
  16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
  17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
  18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-02 17:29:54)
  19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 140790 bytes, from 2018-12-02 17:29:54)
  20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
  21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
  22 
  23 Copyright (C) 2013-2018 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26 
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34 
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38 
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47 
  48 
  49 enum a6xx_color_fmt {
  50         RB6_A8_UNORM = 2,
  51         RB6_R8_UNORM = 3,
  52         RB6_R8_SNORM = 4,
  53         RB6_R8_UINT = 5,
  54         RB6_R8_SINT = 6,
  55         RB6_R4G4B4A4_UNORM = 8,
  56         RB6_R5G5B5A1_UNORM = 10,
  57         RB6_R5G6B5_UNORM = 14,
  58         RB6_R8G8_UNORM = 15,
  59         RB6_R8G8_SNORM = 16,
  60         RB6_R8G8_UINT = 17,
  61         RB6_R8G8_SINT = 18,
  62         RB6_R16_UNORM = 21,
  63         RB6_R16_SNORM = 22,
  64         RB6_R16_FLOAT = 23,
  65         RB6_R16_UINT = 24,
  66         RB6_R16_SINT = 25,
  67         RB6_R8G8B8A8_UNORM = 48,
  68         RB6_R8G8B8_UNORM = 49,
  69         RB6_R8G8B8A8_SNORM = 50,
  70         RB6_R8G8B8A8_UINT = 51,
  71         RB6_R8G8B8A8_SINT = 52,
  72         RB6_R10G10B10A2_UNORM = 55,
  73         RB6_R10G10B10A2_UINT = 58,
  74         RB6_R11G11B10_FLOAT = 66,
  75         RB6_R16G16_UNORM = 67,
  76         RB6_R16G16_SNORM = 68,
  77         RB6_R16G16_FLOAT = 69,
  78         RB6_R16G16_UINT = 70,
  79         RB6_R16G16_SINT = 71,
  80         RB6_R32_FLOAT = 74,
  81         RB6_R32_UINT = 75,
  82         RB6_R32_SINT = 76,
  83         RB6_R16G16B16A16_UNORM = 96,
  84         RB6_R16G16B16A16_SNORM = 97,
  85         RB6_R16G16B16A16_FLOAT = 98,
  86         RB6_R16G16B16A16_UINT = 99,
  87         RB6_R16G16B16A16_SINT = 100,
  88         RB6_R32G32_FLOAT = 103,
  89         RB6_R32G32_UINT = 104,
  90         RB6_R32G32_SINT = 105,
  91         RB6_R32G32B32A32_FLOAT = 130,
  92         RB6_R32G32B32A32_UINT = 131,
  93         RB6_R32G32B32A32_SINT = 132,
  94         RB6_X8Z24_UNORM = 160,
  95 };
  96 
  97 enum a6xx_tile_mode {
  98         TILE6_LINEAR = 0,
  99         TILE6_2 = 2,
 100         TILE6_3 = 3,
 101 };
 102 
 103 enum a6xx_vtx_fmt {
 104         VFMT6_8_UNORM = 3,
 105         VFMT6_8_SNORM = 4,
 106         VFMT6_8_UINT = 5,
 107         VFMT6_8_SINT = 6,
 108         VFMT6_8_8_UNORM = 15,
 109         VFMT6_8_8_SNORM = 16,
 110         VFMT6_8_8_UINT = 17,
 111         VFMT6_8_8_SINT = 18,
 112         VFMT6_16_UNORM = 21,
 113         VFMT6_16_SNORM = 22,
 114         VFMT6_16_FLOAT = 23,
 115         VFMT6_16_UINT = 24,
 116         VFMT6_16_SINT = 25,
 117         VFMT6_8_8_8_UNORM = 33,
 118         VFMT6_8_8_8_SNORM = 34,
 119         VFMT6_8_8_8_UINT = 35,
 120         VFMT6_8_8_8_SINT = 36,
 121         VFMT6_8_8_8_8_UNORM = 48,
 122         VFMT6_8_8_8_8_SNORM = 50,
 123         VFMT6_8_8_8_8_UINT = 51,
 124         VFMT6_8_8_8_8_SINT = 52,
 125         VFMT6_10_10_10_2_UNORM = 54,
 126         VFMT6_10_10_10_2_SNORM = 57,
 127         VFMT6_10_10_10_2_UINT = 58,
 128         VFMT6_10_10_10_2_SINT = 59,
 129         VFMT6_11_11_10_FLOAT = 66,
 130         VFMT6_16_16_UNORM = 67,
 131         VFMT6_16_16_SNORM = 68,
 132         VFMT6_16_16_FLOAT = 69,
 133         VFMT6_16_16_UINT = 70,
 134         VFMT6_16_16_SINT = 71,
 135         VFMT6_32_UNORM = 72,
 136         VFMT6_32_SNORM = 73,
 137         VFMT6_32_FLOAT = 74,
 138         VFMT6_32_UINT = 75,
 139         VFMT6_32_SINT = 76,
 140         VFMT6_32_FIXED = 77,
 141         VFMT6_16_16_16_UNORM = 88,
 142         VFMT6_16_16_16_SNORM = 89,
 143         VFMT6_16_16_16_FLOAT = 90,
 144         VFMT6_16_16_16_UINT = 91,
 145         VFMT6_16_16_16_SINT = 92,
 146         VFMT6_16_16_16_16_UNORM = 96,
 147         VFMT6_16_16_16_16_SNORM = 97,
 148         VFMT6_16_16_16_16_FLOAT = 98,
 149         VFMT6_16_16_16_16_UINT = 99,
 150         VFMT6_16_16_16_16_SINT = 100,
 151         VFMT6_32_32_UNORM = 101,
 152         VFMT6_32_32_SNORM = 102,
 153         VFMT6_32_32_FLOAT = 103,
 154         VFMT6_32_32_UINT = 104,
 155         VFMT6_32_32_SINT = 105,
 156         VFMT6_32_32_FIXED = 106,
 157         VFMT6_32_32_32_UNORM = 112,
 158         VFMT6_32_32_32_SNORM = 113,
 159         VFMT6_32_32_32_UINT = 114,
 160         VFMT6_32_32_32_SINT = 115,
 161         VFMT6_32_32_32_FLOAT = 116,
 162         VFMT6_32_32_32_FIXED = 117,
 163         VFMT6_32_32_32_32_UNORM = 128,
 164         VFMT6_32_32_32_32_SNORM = 129,
 165         VFMT6_32_32_32_32_FLOAT = 130,
 166         VFMT6_32_32_32_32_UINT = 131,
 167         VFMT6_32_32_32_32_SINT = 132,
 168         VFMT6_32_32_32_32_FIXED = 133,
 169 };
 170 
 171 enum a6xx_tex_fmt {
 172         TFMT6_A8_UNORM = 2,
 173         TFMT6_8_UNORM = 3,
 174         TFMT6_8_SNORM = 4,
 175         TFMT6_8_UINT = 5,
 176         TFMT6_8_SINT = 6,
 177         TFMT6_4_4_4_4_UNORM = 8,
 178         TFMT6_5_5_5_1_UNORM = 10,
 179         TFMT6_5_6_5_UNORM = 14,
 180         TFMT6_8_8_UNORM = 15,
 181         TFMT6_8_8_SNORM = 16,
 182         TFMT6_8_8_UINT = 17,
 183         TFMT6_8_8_SINT = 18,
 184         TFMT6_L8_A8_UNORM = 19,
 185         TFMT6_16_UNORM = 21,
 186         TFMT6_16_SNORM = 22,
 187         TFMT6_16_FLOAT = 23,
 188         TFMT6_16_UINT = 24,
 189         TFMT6_16_SINT = 25,
 190         TFMT6_8_8_8_8_UNORM = 48,
 191         TFMT6_8_8_8_UNORM = 49,
 192         TFMT6_8_8_8_8_SNORM = 50,
 193         TFMT6_8_8_8_8_UINT = 51,
 194         TFMT6_8_8_8_8_SINT = 52,
 195         TFMT6_9_9_9_E5_FLOAT = 53,
 196         TFMT6_10_10_10_2_UNORM = 54,
 197         TFMT6_10_10_10_2_UINT = 58,
 198         TFMT6_11_11_10_FLOAT = 66,
 199         TFMT6_16_16_UNORM = 67,
 200         TFMT6_16_16_SNORM = 68,
 201         TFMT6_16_16_FLOAT = 69,
 202         TFMT6_16_16_UINT = 70,
 203         TFMT6_16_16_SINT = 71,
 204         TFMT6_32_FLOAT = 74,
 205         TFMT6_32_UINT = 75,
 206         TFMT6_32_SINT = 76,
 207         TFMT6_16_16_16_16_UNORM = 96,
 208         TFMT6_16_16_16_16_SNORM = 97,
 209         TFMT6_16_16_16_16_FLOAT = 98,
 210         TFMT6_16_16_16_16_UINT = 99,
 211         TFMT6_16_16_16_16_SINT = 100,
 212         TFMT6_32_32_FLOAT = 103,
 213         TFMT6_32_32_UINT = 104,
 214         TFMT6_32_32_SINT = 105,
 215         TFMT6_32_32_32_UINT = 114,
 216         TFMT6_32_32_32_SINT = 115,
 217         TFMT6_32_32_32_FLOAT = 116,
 218         TFMT6_32_32_32_32_FLOAT = 130,
 219         TFMT6_32_32_32_32_UINT = 131,
 220         TFMT6_32_32_32_32_SINT = 132,
 221         TFMT6_X8Z24_UNORM = 160,
 222         TFMT6_ETC2_RG11_UNORM = 171,
 223         TFMT6_ETC2_RG11_SNORM = 172,
 224         TFMT6_ETC2_R11_UNORM = 173,
 225         TFMT6_ETC2_R11_SNORM = 174,
 226         TFMT6_ETC1 = 175,
 227         TFMT6_ETC2_RGB8 = 176,
 228         TFMT6_ETC2_RGBA8 = 177,
 229         TFMT6_ETC2_RGB8A1 = 178,
 230         TFMT6_DXT1 = 179,
 231         TFMT6_DXT3 = 180,
 232         TFMT6_DXT5 = 181,
 233         TFMT6_RGTC1_UNORM = 183,
 234         TFMT6_RGTC1_SNORM = 184,
 235         TFMT6_RGTC2_UNORM = 187,
 236         TFMT6_RGTC2_SNORM = 188,
 237         TFMT6_BPTC_UFLOAT = 190,
 238         TFMT6_BPTC_FLOAT = 191,
 239         TFMT6_BPTC = 192,
 240         TFMT6_ASTC_4x4 = 193,
 241         TFMT6_ASTC_5x4 = 194,
 242         TFMT6_ASTC_5x5 = 195,
 243         TFMT6_ASTC_6x5 = 196,
 244         TFMT6_ASTC_6x6 = 197,
 245         TFMT6_ASTC_8x5 = 198,
 246         TFMT6_ASTC_8x6 = 199,
 247         TFMT6_ASTC_8x8 = 200,
 248         TFMT6_ASTC_10x5 = 201,
 249         TFMT6_ASTC_10x6 = 202,
 250         TFMT6_ASTC_10x8 = 203,
 251         TFMT6_ASTC_10x10 = 204,
 252         TFMT6_ASTC_12x10 = 205,
 253         TFMT6_ASTC_12x12 = 206,
 254 };
 255 
 256 enum a6xx_tex_fetchsize {
 257         TFETCH6_1_BYTE = 0,
 258         TFETCH6_2_BYTE = 1,
 259         TFETCH6_4_BYTE = 2,
 260         TFETCH6_8_BYTE = 3,
 261         TFETCH6_16_BYTE = 4,
 262 };
 263 
 264 enum a6xx_depth_format {
 265         DEPTH6_NONE = 0,
 266         DEPTH6_16 = 1,
 267         DEPTH6_24_8 = 2,
 268         DEPTH6_32 = 4,
 269 };
 270 
 271 enum a6xx_shader_id {
 272         A6XX_TP0_TMO_DATA = 9,
 273         A6XX_TP0_SMO_DATA = 10,
 274         A6XX_TP0_MIPMAP_BASE_DATA = 11,
 275         A6XX_TP1_TMO_DATA = 25,
 276         A6XX_TP1_SMO_DATA = 26,
 277         A6XX_TP1_MIPMAP_BASE_DATA = 27,
 278         A6XX_SP_INST_DATA = 41,
 279         A6XX_SP_LB_0_DATA = 42,
 280         A6XX_SP_LB_1_DATA = 43,
 281         A6XX_SP_LB_2_DATA = 44,
 282         A6XX_SP_LB_3_DATA = 45,
 283         A6XX_SP_LB_4_DATA = 46,
 284         A6XX_SP_LB_5_DATA = 47,
 285         A6XX_SP_CB_BINDLESS_DATA = 48,
 286         A6XX_SP_CB_LEGACY_DATA = 49,
 287         A6XX_SP_UAV_DATA = 50,
 288         A6XX_SP_INST_TAG = 51,
 289         A6XX_SP_CB_BINDLESS_TAG = 52,
 290         A6XX_SP_TMO_UMO_TAG = 53,
 291         A6XX_SP_SMO_TAG = 54,
 292         A6XX_SP_STATE_DATA = 55,
 293         A6XX_HLSQ_CHUNK_CVS_RAM = 73,
 294         A6XX_HLSQ_CHUNK_CPS_RAM = 74,
 295         A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
 296         A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
 297         A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
 298         A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
 299         A6XX_HLSQ_CVS_MISC_RAM = 80,
 300         A6XX_HLSQ_CPS_MISC_RAM = 81,
 301         A6XX_HLSQ_INST_RAM = 82,
 302         A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
 303         A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
 304         A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
 305         A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
 306         A6XX_HLSQ_INST_RAM_TAG = 87,
 307         A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
 308         A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
 309         A6XX_HLSQ_PWR_REST_RAM = 90,
 310         A6XX_HLSQ_PWR_REST_TAG = 91,
 311         A6XX_HLSQ_DATAPATH_META = 96,
 312         A6XX_HLSQ_FRONTEND_META = 97,
 313         A6XX_HLSQ_INDIRECT_META = 98,
 314         A6XX_HLSQ_BACKEND_META = 99,
 315 };
 316 
 317 enum a6xx_debugbus_id {
 318         A6XX_DBGBUS_CP = 1,
 319         A6XX_DBGBUS_RBBM = 2,
 320         A6XX_DBGBUS_VBIF = 3,
 321         A6XX_DBGBUS_HLSQ = 4,
 322         A6XX_DBGBUS_UCHE = 5,
 323         A6XX_DBGBUS_DPM = 6,
 324         A6XX_DBGBUS_TESS = 7,
 325         A6XX_DBGBUS_PC = 8,
 326         A6XX_DBGBUS_VFDP = 9,
 327         A6XX_DBGBUS_VPC = 10,
 328         A6XX_DBGBUS_TSE = 11,
 329         A6XX_DBGBUS_RAS = 12,
 330         A6XX_DBGBUS_VSC = 13,
 331         A6XX_DBGBUS_COM = 14,
 332         A6XX_DBGBUS_LRZ = 16,
 333         A6XX_DBGBUS_A2D = 17,
 334         A6XX_DBGBUS_CCUFCHE = 18,
 335         A6XX_DBGBUS_GMU_CX = 19,
 336         A6XX_DBGBUS_RBP = 20,
 337         A6XX_DBGBUS_DCS = 21,
 338         A6XX_DBGBUS_DBGC = 22,
 339         A6XX_DBGBUS_CX = 23,
 340         A6XX_DBGBUS_GMU_GX = 24,
 341         A6XX_DBGBUS_TPFCHE = 25,
 342         A6XX_DBGBUS_GBIF_GX = 26,
 343         A6XX_DBGBUS_GPC = 29,
 344         A6XX_DBGBUS_LARC = 30,
 345         A6XX_DBGBUS_HLSQ_SPTP = 31,
 346         A6XX_DBGBUS_RB_0 = 32,
 347         A6XX_DBGBUS_RB_1 = 33,
 348         A6XX_DBGBUS_UCHE_WRAPPER = 36,
 349         A6XX_DBGBUS_CCU_0 = 40,
 350         A6XX_DBGBUS_CCU_1 = 41,
 351         A6XX_DBGBUS_VFD_0 = 56,
 352         A6XX_DBGBUS_VFD_1 = 57,
 353         A6XX_DBGBUS_VFD_2 = 58,
 354         A6XX_DBGBUS_VFD_3 = 59,
 355         A6XX_DBGBUS_SP_0 = 64,
 356         A6XX_DBGBUS_SP_1 = 65,
 357         A6XX_DBGBUS_TPL1_0 = 72,
 358         A6XX_DBGBUS_TPL1_1 = 73,
 359         A6XX_DBGBUS_TPL1_2 = 74,
 360         A6XX_DBGBUS_TPL1_3 = 75,
 361 };
 362 
 363 enum a6xx_cp_perfcounter_select {
 364         PERF_CP_ALWAYS_COUNT = 0,
 365         PERF_CP_BUSY_GFX_CORE_IDLE = 1,
 366         PERF_CP_BUSY_CYCLES = 2,
 367         PERF_CP_NUM_PREEMPTIONS = 3,
 368         PERF_CP_PREEMPTION_REACTION_DELAY = 4,
 369         PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
 370         PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
 371         PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
 372         PERF_CP_PREDICATED_DRAWS_KILLED = 8,
 373         PERF_CP_MODE_SWITCH = 9,
 374         PERF_CP_ZPASS_DONE = 10,
 375         PERF_CP_CONTEXT_DONE = 11,
 376         PERF_CP_CACHE_FLUSH = 12,
 377         PERF_CP_LONG_PREEMPTIONS = 13,
 378         PERF_CP_SQE_I_CACHE_STARVE = 14,
 379         PERF_CP_SQE_IDLE = 15,
 380         PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
 381         PERF_CP_SQE_PM4_STARVE_SDS = 17,
 382         PERF_CP_SQE_MRB_STARVE = 18,
 383         PERF_CP_SQE_RRB_STARVE = 19,
 384         PERF_CP_SQE_VSD_STARVE = 20,
 385         PERF_CP_VSD_DECODE_STARVE = 21,
 386         PERF_CP_SQE_PIPE_OUT_STALL = 22,
 387         PERF_CP_SQE_SYNC_STALL = 23,
 388         PERF_CP_SQE_PM4_WFI_STALL = 24,
 389         PERF_CP_SQE_SYS_WFI_STALL = 25,
 390         PERF_CP_SQE_T4_EXEC = 26,
 391         PERF_CP_SQE_LOAD_STATE_EXEC = 27,
 392         PERF_CP_SQE_SAVE_SDS_STATE = 28,
 393         PERF_CP_SQE_DRAW_EXEC = 29,
 394         PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
 395         PERF_CP_SQE_EXEC_PROFILED = 31,
 396         PERF_CP_MEMORY_POOL_EMPTY = 32,
 397         PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
 398         PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
 399         PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
 400         PERF_CP_AHB_STALL_SQE_GMU = 36,
 401         PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
 402         PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
 403         PERF_CP_CLUSTER0_EMPTY = 39,
 404         PERF_CP_CLUSTER1_EMPTY = 40,
 405         PERF_CP_CLUSTER2_EMPTY = 41,
 406         PERF_CP_CLUSTER3_EMPTY = 42,
 407         PERF_CP_CLUSTER4_EMPTY = 43,
 408         PERF_CP_CLUSTER5_EMPTY = 44,
 409         PERF_CP_PM4_DATA = 45,
 410         PERF_CP_PM4_HEADERS = 46,
 411         PERF_CP_VBIF_READ_BEATS = 47,
 412         PERF_CP_VBIF_WRITE_BEATS = 48,
 413         PERF_CP_SQE_INSTR_COUNTER = 49,
 414 };
 415 
 416 enum a6xx_rbbm_perfcounter_select {
 417         PERF_RBBM_ALWAYS_COUNT = 0,
 418         PERF_RBBM_ALWAYS_ON = 1,
 419         PERF_RBBM_TSE_BUSY = 2,
 420         PERF_RBBM_RAS_BUSY = 3,
 421         PERF_RBBM_PC_DCALL_BUSY = 4,
 422         PERF_RBBM_PC_VSD_BUSY = 5,
 423         PERF_RBBM_STATUS_MASKED = 6,
 424         PERF_RBBM_COM_BUSY = 7,
 425         PERF_RBBM_DCOM_BUSY = 8,
 426         PERF_RBBM_VBIF_BUSY = 9,
 427         PERF_RBBM_VSC_BUSY = 10,
 428         PERF_RBBM_TESS_BUSY = 11,
 429         PERF_RBBM_UCHE_BUSY = 12,
 430         PERF_RBBM_HLSQ_BUSY = 13,
 431 };
 432 
 433 enum a6xx_pc_perfcounter_select {
 434         PERF_PC_BUSY_CYCLES = 0,
 435         PERF_PC_WORKING_CYCLES = 1,
 436         PERF_PC_STALL_CYCLES_VFD = 2,
 437         PERF_PC_STALL_CYCLES_TSE = 3,
 438         PERF_PC_STALL_CYCLES_VPC = 4,
 439         PERF_PC_STALL_CYCLES_UCHE = 5,
 440         PERF_PC_STALL_CYCLES_TESS = 6,
 441         PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
 442         PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
 443         PERF_PC_PASS1_TF_STALL_CYCLES = 9,
 444         PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
 445         PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
 446         PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
 447         PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
 448         PERF_PC_STARVE_CYCLES_DI = 14,
 449         PERF_PC_VIS_STREAMS_LOADED = 15,
 450         PERF_PC_INSTANCES = 16,
 451         PERF_PC_VPC_PRIMITIVES = 17,
 452         PERF_PC_DEAD_PRIM = 18,
 453         PERF_PC_LIVE_PRIM = 19,
 454         PERF_PC_VERTEX_HITS = 20,
 455         PERF_PC_IA_VERTICES = 21,
 456         PERF_PC_IA_PRIMITIVES = 22,
 457         PERF_PC_GS_PRIMITIVES = 23,
 458         PERF_PC_HS_INVOCATIONS = 24,
 459         PERF_PC_DS_INVOCATIONS = 25,
 460         PERF_PC_VS_INVOCATIONS = 26,
 461         PERF_PC_GS_INVOCATIONS = 27,
 462         PERF_PC_DS_PRIMITIVES = 28,
 463         PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
 464         PERF_PC_3D_DRAWCALLS = 30,
 465         PERF_PC_2D_DRAWCALLS = 31,
 466         PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
 467         PERF_TESS_BUSY_CYCLES = 33,
 468         PERF_TESS_WORKING_CYCLES = 34,
 469         PERF_TESS_STALL_CYCLES_PC = 35,
 470         PERF_TESS_STARVE_CYCLES_PC = 36,
 471         PERF_PC_TSE_TRANSACTION = 37,
 472         PERF_PC_TSE_VERTEX = 38,
 473         PERF_PC_TESS_PC_UV_TRANS = 39,
 474         PERF_PC_TESS_PC_UV_PATCHES = 40,
 475         PERF_PC_TESS_FACTOR_TRANS = 41,
 476 };
 477 
 478 enum a6xx_vfd_perfcounter_select {
 479         PERF_VFD_BUSY_CYCLES = 0,
 480         PERF_VFD_STALL_CYCLES_UCHE = 1,
 481         PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
 482         PERF_VFD_STALL_CYCLES_SP_INFO = 3,
 483         PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
 484         PERF_VFD_STARVE_CYCLES_UCHE = 5,
 485         PERF_VFD_RBUFFER_FULL = 6,
 486         PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
 487         PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
 488         PERF_VFD_NUM_ATTRIBUTES = 9,
 489         PERF_VFD_UPPER_SHADER_FIBERS = 10,
 490         PERF_VFD_LOWER_SHADER_FIBERS = 11,
 491         PERF_VFD_MODE_0_FIBERS = 12,
 492         PERF_VFD_MODE_1_FIBERS = 13,
 493         PERF_VFD_MODE_2_FIBERS = 14,
 494         PERF_VFD_MODE_3_FIBERS = 15,
 495         PERF_VFD_MODE_4_FIBERS = 16,
 496         PERF_VFD_TOTAL_VERTICES = 17,
 497         PERF_VFDP_STALL_CYCLES_VFD = 18,
 498         PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
 499         PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
 500         PERF_VFDP_STARVE_CYCLES_PC = 21,
 501         PERF_VFDP_VS_STAGE_WAVES = 22,
 502 };
 503 
 504 enum a6xx_hlsq_perfcounter_select {
 505         PERF_HLSQ_BUSY_CYCLES = 0,
 506         PERF_HLSQ_STALL_CYCLES_UCHE = 1,
 507         PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
 508         PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
 509         PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
 510         PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
 511         PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
 512         PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
 513         PERF_HLSQ_QUADS = 8,
 514         PERF_HLSQ_CS_INVOCATIONS = 9,
 515         PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
 516         PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
 517         PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
 518         PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
 519         PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
 520         PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
 521         PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
 522         PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
 523         PERF_HLSQ_STALL_CYCLES_VPC = 18,
 524         PERF_HLSQ_PIXELS = 19,
 525         PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
 526 };
 527 
 528 enum a6xx_vpc_perfcounter_select {
 529         PERF_VPC_BUSY_CYCLES = 0,
 530         PERF_VPC_WORKING_CYCLES = 1,
 531         PERF_VPC_STALL_CYCLES_UCHE = 2,
 532         PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
 533         PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
 534         PERF_VPC_STALL_CYCLES_PC = 5,
 535         PERF_VPC_STALL_CYCLES_SP_LM = 6,
 536         PERF_VPC_STARVE_CYCLES_SP = 7,
 537         PERF_VPC_STARVE_CYCLES_LRZ = 8,
 538         PERF_VPC_PC_PRIMITIVES = 9,
 539         PERF_VPC_SP_COMPONENTS = 10,
 540         PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
 541         PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
 542         PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
 543         PERF_VPC_LM_TRANSACTION = 14,
 544         PERF_VPC_STREAMOUT_TRANSACTION = 15,
 545         PERF_VPC_VS_BUSY_CYCLES = 16,
 546         PERF_VPC_PS_BUSY_CYCLES = 17,
 547         PERF_VPC_VS_WORKING_CYCLES = 18,
 548         PERF_VPC_PS_WORKING_CYCLES = 19,
 549         PERF_VPC_STARVE_CYCLES_RB = 20,
 550         PERF_VPC_NUM_VPCRAM_READ_POS = 21,
 551         PERF_VPC_WIT_FULL_CYCLES = 22,
 552         PERF_VPC_VPCRAM_FULL_CYCLES = 23,
 553         PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
 554         PERF_VPC_NUM_VPCRAM_WRITE = 25,
 555         PERF_VPC_NUM_VPCRAM_READ_SO = 26,
 556         PERF_VPC_NUM_ATTR_REQ_LM = 27,
 557 };
 558 
 559 enum a6xx_tse_perfcounter_select {
 560         PERF_TSE_BUSY_CYCLES = 0,
 561         PERF_TSE_CLIPPING_CYCLES = 1,
 562         PERF_TSE_STALL_CYCLES_RAS = 2,
 563         PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
 564         PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
 565         PERF_TSE_STARVE_CYCLES_PC = 5,
 566         PERF_TSE_INPUT_PRIM = 6,
 567         PERF_TSE_INPUT_NULL_PRIM = 7,
 568         PERF_TSE_TRIVAL_REJ_PRIM = 8,
 569         PERF_TSE_CLIPPED_PRIM = 9,
 570         PERF_TSE_ZERO_AREA_PRIM = 10,
 571         PERF_TSE_FACENESS_CULLED_PRIM = 11,
 572         PERF_TSE_ZERO_PIXEL_PRIM = 12,
 573         PERF_TSE_OUTPUT_NULL_PRIM = 13,
 574         PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
 575         PERF_TSE_CINVOCATION = 15,
 576         PERF_TSE_CPRIMITIVES = 16,
 577         PERF_TSE_2D_INPUT_PRIM = 17,
 578         PERF_TSE_2D_ALIVE_CYCLES = 18,
 579         PERF_TSE_CLIP_PLANES = 19,
 580 };
 581 
 582 enum a6xx_ras_perfcounter_select {
 583         PERF_RAS_BUSY_CYCLES = 0,
 584         PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
 585         PERF_RAS_STALL_CYCLES_LRZ = 2,
 586         PERF_RAS_STARVE_CYCLES_TSE = 3,
 587         PERF_RAS_SUPER_TILES = 4,
 588         PERF_RAS_8X4_TILES = 5,
 589         PERF_RAS_MASKGEN_ACTIVE = 6,
 590         PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
 591         PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
 592         PERF_RAS_PRIM_KILLED_INVISILBE = 9,
 593         PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
 594         PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
 595         PERF_RAS_BLOCKS = 12,
 596 };
 597 
 598 enum a6xx_uche_perfcounter_select {
 599         PERF_UCHE_BUSY_CYCLES = 0,
 600         PERF_UCHE_STALL_CYCLES_ARBITER = 1,
 601         PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
 602         PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
 603         PERF_UCHE_VBIF_READ_BEATS_TP = 4,
 604         PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
 605         PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
 606         PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
 607         PERF_UCHE_VBIF_READ_BEATS_SP = 8,
 608         PERF_UCHE_READ_REQUESTS_TP = 9,
 609         PERF_UCHE_READ_REQUESTS_VFD = 10,
 610         PERF_UCHE_READ_REQUESTS_HLSQ = 11,
 611         PERF_UCHE_READ_REQUESTS_LRZ = 12,
 612         PERF_UCHE_READ_REQUESTS_SP = 13,
 613         PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
 614         PERF_UCHE_WRITE_REQUESTS_SP = 15,
 615         PERF_UCHE_WRITE_REQUESTS_VPC = 16,
 616         PERF_UCHE_WRITE_REQUESTS_VSC = 17,
 617         PERF_UCHE_EVICTS = 18,
 618         PERF_UCHE_BANK_REQ0 = 19,
 619         PERF_UCHE_BANK_REQ1 = 20,
 620         PERF_UCHE_BANK_REQ2 = 21,
 621         PERF_UCHE_BANK_REQ3 = 22,
 622         PERF_UCHE_BANK_REQ4 = 23,
 623         PERF_UCHE_BANK_REQ5 = 24,
 624         PERF_UCHE_BANK_REQ6 = 25,
 625         PERF_UCHE_BANK_REQ7 = 26,
 626         PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
 627         PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
 628         PERF_UCHE_GMEM_READ_BEATS = 29,
 629         PERF_UCHE_TPH_REF_FULL = 30,
 630         PERF_UCHE_TPH_VICTIM_FULL = 31,
 631         PERF_UCHE_TPH_EXT_FULL = 32,
 632         PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
 633         PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
 634         PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
 635         PERF_UCHE_VBIF_READ_BEATS_PC = 36,
 636         PERF_UCHE_READ_REQUESTS_PC = 37,
 637         PERF_UCHE_RAM_READ_REQ = 38,
 638         PERF_UCHE_RAM_WRITE_REQ = 39,
 639 };
 640 
 641 enum a6xx_tp_perfcounter_select {
 642         PERF_TP_BUSY_CYCLES = 0,
 643         PERF_TP_STALL_CYCLES_UCHE = 1,
 644         PERF_TP_LATENCY_CYCLES = 2,
 645         PERF_TP_LATENCY_TRANS = 3,
 646         PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
 647         PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
 648         PERF_TP_L1_CACHELINE_REQUESTS = 6,
 649         PERF_TP_L1_CACHELINE_MISSES = 7,
 650         PERF_TP_SP_TP_TRANS = 8,
 651         PERF_TP_TP_SP_TRANS = 9,
 652         PERF_TP_OUTPUT_PIXELS = 10,
 653         PERF_TP_FILTER_WORKLOAD_16BIT = 11,
 654         PERF_TP_FILTER_WORKLOAD_32BIT = 12,
 655         PERF_TP_QUADS_RECEIVED = 13,
 656         PERF_TP_QUADS_OFFSET = 14,
 657         PERF_TP_QUADS_SHADOW = 15,
 658         PERF_TP_QUADS_ARRAY = 16,
 659         PERF_TP_QUADS_GRADIENT = 17,
 660         PERF_TP_QUADS_1D = 18,
 661         PERF_TP_QUADS_2D = 19,
 662         PERF_TP_QUADS_BUFFER = 20,
 663         PERF_TP_QUADS_3D = 21,
 664         PERF_TP_QUADS_CUBE = 22,
 665         PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
 666         PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
 667         PERF_TP_OUTPUT_PIXELS_POINT = 25,
 668         PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
 669         PERF_TP_OUTPUT_PIXELS_MIP = 27,
 670         PERF_TP_OUTPUT_PIXELS_ANISO = 28,
 671         PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
 672         PERF_TP_FLAG_CACHE_REQUESTS = 30,
 673         PERF_TP_FLAG_CACHE_MISSES = 31,
 674         PERF_TP_L1_5_L2_REQUESTS = 32,
 675         PERF_TP_2D_OUTPUT_PIXELS = 33,
 676         PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
 677         PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
 678         PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
 679         PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
 680         PERF_TP_TPA2TPC_TRANS = 38,
 681         PERF_TP_L1_MISSES_ASTC_1TILE = 39,
 682         PERF_TP_L1_MISSES_ASTC_2TILE = 40,
 683         PERF_TP_L1_MISSES_ASTC_4TILE = 41,
 684         PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
 685         PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
 686         PERF_TP_L1_BANK_CONFLICT = 44,
 687         PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
 688         PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
 689         PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
 690         PERF_TP_FRONTEND_WORKING_CYCLES = 48,
 691         PERF_TP_L1_TAG_WORKING_CYCLES = 49,
 692         PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
 693         PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
 694         PERF_TP_BACKEND_WORKING_CYCLES = 52,
 695         PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
 696         PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
 697         PERF_TP_STARVE_CYCLES_SP = 55,
 698         PERF_TP_STARVE_CYCLES_UCHE = 56,
 699 };
 700 
 701 enum a6xx_sp_perfcounter_select {
 702         PERF_SP_BUSY_CYCLES = 0,
 703         PERF_SP_ALU_WORKING_CYCLES = 1,
 704         PERF_SP_EFU_WORKING_CYCLES = 2,
 705         PERF_SP_STALL_CYCLES_VPC = 3,
 706         PERF_SP_STALL_CYCLES_TP = 4,
 707         PERF_SP_STALL_CYCLES_UCHE = 5,
 708         PERF_SP_STALL_CYCLES_RB = 6,
 709         PERF_SP_NON_EXECUTION_CYCLES = 7,
 710         PERF_SP_WAVE_CONTEXTS = 8,
 711         PERF_SP_WAVE_CONTEXT_CYCLES = 9,
 712         PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
 713         PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
 714         PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
 715         PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
 716         PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
 717         PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
 718         PERF_SP_WAVE_CTRL_CYCLES = 16,
 719         PERF_SP_WAVE_LOAD_CYCLES = 17,
 720         PERF_SP_WAVE_EMIT_CYCLES = 18,
 721         PERF_SP_WAVE_NOP_CYCLES = 19,
 722         PERF_SP_WAVE_WAIT_CYCLES = 20,
 723         PERF_SP_WAVE_FETCH_CYCLES = 21,
 724         PERF_SP_WAVE_IDLE_CYCLES = 22,
 725         PERF_SP_WAVE_END_CYCLES = 23,
 726         PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
 727         PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
 728         PERF_SP_WAVE_JOIN_CYCLES = 26,
 729         PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
 730         PERF_SP_LM_STORE_INSTRUCTIONS = 28,
 731         PERF_SP_LM_ATOMICS = 29,
 732         PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
 733         PERF_SP_GM_STORE_INSTRUCTIONS = 31,
 734         PERF_SP_GM_ATOMICS = 32,
 735         PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
 736         PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
 737         PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
 738         PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
 739         PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
 740         PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
 741         PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
 742         PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
 743         PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
 744         PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
 745         PERF_SP_VS_INSTRUCTIONS = 43,
 746         PERF_SP_FS_INSTRUCTIONS = 44,
 747         PERF_SP_ADDR_LOCK_COUNT = 45,
 748         PERF_SP_UCHE_READ_TRANS = 46,
 749         PERF_SP_UCHE_WRITE_TRANS = 47,
 750         PERF_SP_EXPORT_VPC_TRANS = 48,
 751         PERF_SP_EXPORT_RB_TRANS = 49,
 752         PERF_SP_PIXELS_KILLED = 50,
 753         PERF_SP_ICL1_REQUESTS = 51,
 754         PERF_SP_ICL1_MISSES = 52,
 755         PERF_SP_HS_INSTRUCTIONS = 53,
 756         PERF_SP_DS_INSTRUCTIONS = 54,
 757         PERF_SP_GS_INSTRUCTIONS = 55,
 758         PERF_SP_CS_INSTRUCTIONS = 56,
 759         PERF_SP_GPR_READ = 57,
 760         PERF_SP_GPR_WRITE = 58,
 761         PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
 762         PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
 763         PERF_SP_LM_BANK_CONFLICTS = 61,
 764         PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
 765         PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
 766         PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
 767         PERF_SP_LM_WORKING_CYCLES = 65,
 768         PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
 769         PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
 770         PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
 771         PERF_SP_STARVE_CYCLES_HLSQ = 69,
 772         PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
 773         PERF_SP_WORKING_EU = 71,
 774         PERF_SP_ANY_EU_WORKING = 72,
 775         PERF_SP_WORKING_EU_FS_STAGE = 73,
 776         PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
 777         PERF_SP_WORKING_EU_VS_STAGE = 75,
 778         PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
 779         PERF_SP_WORKING_EU_CS_STAGE = 77,
 780         PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
 781         PERF_SP_GPR_READ_PREFETCH = 79,
 782         PERF_SP_GPR_READ_CONFLICT = 80,
 783         PERF_SP_GPR_WRITE_CONFLICT = 81,
 784         PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
 785         PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
 786         PERF_SP_EXECUTABLE_WAVES = 84,
 787 };
 788 
 789 enum a6xx_rb_perfcounter_select {
 790         PERF_RB_BUSY_CYCLES = 0,
 791         PERF_RB_STALL_CYCLES_HLSQ = 1,
 792         PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
 793         PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
 794         PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
 795         PERF_RB_STARVE_CYCLES_SP = 5,
 796         PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
 797         PERF_RB_STARVE_CYCLES_CCU = 7,
 798         PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
 799         PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
 800         PERF_RB_Z_WORKLOAD = 10,
 801         PERF_RB_HLSQ_ACTIVE = 11,
 802         PERF_RB_Z_READ = 12,
 803         PERF_RB_Z_WRITE = 13,
 804         PERF_RB_C_READ = 14,
 805         PERF_RB_C_WRITE = 15,
 806         PERF_RB_TOTAL_PASS = 16,
 807         PERF_RB_Z_PASS = 17,
 808         PERF_RB_Z_FAIL = 18,
 809         PERF_RB_S_FAIL = 19,
 810         PERF_RB_BLENDED_FXP_COMPONENTS = 20,
 811         PERF_RB_BLENDED_FP16_COMPONENTS = 21,
 812         PERF_RB_PS_INVOCATIONS = 22,
 813         PERF_RB_2D_ALIVE_CYCLES = 23,
 814         PERF_RB_2D_STALL_CYCLES_A2D = 24,
 815         PERF_RB_2D_STARVE_CYCLES_SRC = 25,
 816         PERF_RB_2D_STARVE_CYCLES_SP = 26,
 817         PERF_RB_2D_STARVE_CYCLES_DST = 27,
 818         PERF_RB_2D_VALID_PIXELS = 28,
 819         PERF_RB_3D_PIXELS = 29,
 820         PERF_RB_BLENDER_WORKING_CYCLES = 30,
 821         PERF_RB_ZPROC_WORKING_CYCLES = 31,
 822         PERF_RB_CPROC_WORKING_CYCLES = 32,
 823         PERF_RB_SAMPLER_WORKING_CYCLES = 33,
 824         PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
 825         PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
 826         PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
 827         PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
 828         PERF_RB_STALL_CYCLES_VPC = 38,
 829         PERF_RB_2D_INPUT_TRANS = 39,
 830         PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
 831         PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
 832         PERF_RB_BLENDED_FP32_COMPONENTS = 42,
 833         PERF_RB_COLOR_PIX_TILES = 43,
 834         PERF_RB_STALL_CYCLES_CCU = 44,
 835         PERF_RB_EARLY_Z_ARB3_GRANT = 45,
 836         PERF_RB_LATE_Z_ARB3_GRANT = 46,
 837         PERF_RB_EARLY_Z_SKIP_GRANT = 47,
 838 };
 839 
 840 enum a6xx_vsc_perfcounter_select {
 841         PERF_VSC_BUSY_CYCLES = 0,
 842         PERF_VSC_WORKING_CYCLES = 1,
 843         PERF_VSC_STALL_CYCLES_UCHE = 2,
 844         PERF_VSC_EOT_NUM = 3,
 845         PERF_VSC_INPUT_TILES = 4,
 846 };
 847 
 848 enum a6xx_ccu_perfcounter_select {
 849         PERF_CCU_BUSY_CYCLES = 0,
 850         PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
 851         PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
 852         PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
 853         PERF_CCU_DEPTH_BLOCKS = 4,
 854         PERF_CCU_COLOR_BLOCKS = 5,
 855         PERF_CCU_DEPTH_BLOCK_HIT = 6,
 856         PERF_CCU_COLOR_BLOCK_HIT = 7,
 857         PERF_CCU_PARTIAL_BLOCK_READ = 8,
 858         PERF_CCU_GMEM_READ = 9,
 859         PERF_CCU_GMEM_WRITE = 10,
 860         PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
 861         PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
 862         PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
 863         PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
 864         PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
 865         PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
 866         PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
 867         PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
 868         PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
 869         PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
 870         PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
 871         PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
 872         PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
 873         PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
 874         PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
 875         PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
 876         PERF_CCU_2D_RD_REQ = 27,
 877         PERF_CCU_2D_WR_REQ = 28,
 878 };
 879 
 880 enum a6xx_lrz_perfcounter_select {
 881         PERF_LRZ_BUSY_CYCLES = 0,
 882         PERF_LRZ_STARVE_CYCLES_RAS = 1,
 883         PERF_LRZ_STALL_CYCLES_RB = 2,
 884         PERF_LRZ_STALL_CYCLES_VSC = 3,
 885         PERF_LRZ_STALL_CYCLES_VPC = 4,
 886         PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
 887         PERF_LRZ_STALL_CYCLES_UCHE = 6,
 888         PERF_LRZ_LRZ_READ = 7,
 889         PERF_LRZ_LRZ_WRITE = 8,
 890         PERF_LRZ_READ_LATENCY = 9,
 891         PERF_LRZ_MERGE_CACHE_UPDATING = 10,
 892         PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
 893         PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
 894         PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
 895         PERF_LRZ_FULL_8X8_TILES = 14,
 896         PERF_LRZ_PARTIAL_8X8_TILES = 15,
 897         PERF_LRZ_TILE_KILLED = 16,
 898         PERF_LRZ_TOTAL_PIXEL = 17,
 899         PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
 900         PERF_LRZ_FULLY_COVERED_TILES = 19,
 901         PERF_LRZ_PARTIAL_COVERED_TILES = 20,
 902         PERF_LRZ_FEEDBACK_ACCEPT = 21,
 903         PERF_LRZ_FEEDBACK_DISCARD = 22,
 904         PERF_LRZ_FEEDBACK_STALL = 23,
 905         PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
 906         PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
 907         PERF_LRZ_STALL_CYCLES_VC = 26,
 908         PERF_LRZ_RAS_MASK_TRANS = 27,
 909 };
 910 
 911 enum a6xx_cmp_perfcounter_select {
 912         PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
 913         PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
 914         PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
 915         PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
 916         PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
 917         PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
 918         PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
 919         PERF_CMPDECMP_VBIF_READ_DATA = 7,
 920         PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
 921         PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
 922         PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
 923         PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
 924         PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
 925         PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
 926         PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
 927         PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
 928         PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
 929         PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
 930         PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
 931         PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
 932         PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
 933         PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
 934         PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
 935         PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
 936         PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
 937         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
 938         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
 939         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
 940         PERF_CMPDECMP_2D_RD_DATA = 28,
 941         PERF_CMPDECMP_2D_WR_DATA = 29,
 942         PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
 943         PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
 944         PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
 945         PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
 946         PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
 947         PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
 948         PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
 949         PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
 950         PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
 951         PERF_CMPDECMP_2D_PIXELS = 39,
 952 };
 953 
 954 enum a6xx_tex_filter {
 955         A6XX_TEX_NEAREST = 0,
 956         A6XX_TEX_LINEAR = 1,
 957         A6XX_TEX_ANISO = 2,
 958 };
 959 
 960 enum a6xx_tex_clamp {
 961         A6XX_TEX_REPEAT = 0,
 962         A6XX_TEX_CLAMP_TO_EDGE = 1,
 963         A6XX_TEX_MIRROR_REPEAT = 2,
 964         A6XX_TEX_CLAMP_TO_BORDER = 3,
 965         A6XX_TEX_MIRROR_CLAMP = 4,
 966 };
 967 
 968 enum a6xx_tex_aniso {
 969         A6XX_TEX_ANISO_1 = 0,
 970         A6XX_TEX_ANISO_2 = 1,
 971         A6XX_TEX_ANISO_4 = 2,
 972         A6XX_TEX_ANISO_8 = 3,
 973         A6XX_TEX_ANISO_16 = 4,
 974 };
 975 
 976 enum a6xx_tex_swiz {
 977         A6XX_TEX_X = 0,
 978         A6XX_TEX_Y = 1,
 979         A6XX_TEX_Z = 2,
 980         A6XX_TEX_W = 3,
 981         A6XX_TEX_ZERO = 4,
 982         A6XX_TEX_ONE = 5,
 983 };
 984 
 985 enum a6xx_tex_type {
 986         A6XX_TEX_1D = 0,
 987         A6XX_TEX_2D = 1,
 988         A6XX_TEX_CUBE = 2,
 989         A6XX_TEX_3D = 3,
 990 };
 991 
 992 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE                      0x00000001
 993 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR                       0x00000002
 994 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW        0x00000040
 995 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR                     0x00000080
 996 #define A6XX_RBBM_INT_0_MASK_CP_SW                              0x00000100
 997 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR                        0x00000200
 998 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS              0x00000400
 999 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS              0x00000800
1000 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS                  0x00001000
1001 #define A6XX_RBBM_INT_0_MASK_CP_IB2                             0x00002000
1002 #define A6XX_RBBM_INT_0_MASK_CP_IB1                             0x00004000
1003 #define A6XX_RBBM_INT_0_MASK_CP_RB                              0x00008000
1004 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS                      0x00020000
1005 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS                      0x00040000
1006 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS                  0x00100000
1007 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW              0x00400000
1008 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT                   0x00800000
1009 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS                    0x01000000
1010 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR                     0x02000000
1011 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0                      0x04000000
1012 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1                      0x08000000
1013 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ                       0x40000000
1014 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG                   0x80000000
1015 #define A6XX_CP_INT_CP_OPCODE_ERROR                             0x00000001
1016 #define A6XX_CP_INT_CP_UCODE_ERROR                              0x00000002
1017 #define A6XX_CP_INT_CP_HW_FAULT_ERROR                           0x00000004
1018 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR                0x00000010
1019 #define A6XX_CP_INT_CP_AHB_ERROR                                0x00000020
1020 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR                         0x00000040
1021 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR                      0x00000080
1022 #define REG_A6XX_CP_RB_BASE                                     0x00000800
1023 
1024 #define REG_A6XX_CP_RB_BASE_HI                                  0x00000801
1025 
1026 #define REG_A6XX_CP_RB_CNTL                                     0x00000802
1027 
1028 #define REG_A6XX_CP_RB_RPTR_ADDR_LO                             0x00000804
1029 
1030 #define REG_A6XX_CP_RB_RPTR_ADDR_HI                             0x00000805
1031 
1032 #define REG_A6XX_CP_RB_RPTR                                     0x00000806
1033 
1034 #define REG_A6XX_CP_RB_WPTR                                     0x00000807
1035 
1036 #define REG_A6XX_CP_SQE_CNTL                                    0x00000808
1037 
1038 #define REG_A6XX_CP_HW_FAULT                                    0x00000821
1039 
1040 #define REG_A6XX_CP_INTERRUPT_STATUS                            0x00000823
1041 
1042 #define REG_A6XX_CP_PROTECT_STATUS                              0x00000824
1043 
1044 #define REG_A6XX_CP_SQE_INSTR_BASE_LO                           0x00000830
1045 
1046 #define REG_A6XX_CP_SQE_INSTR_BASE_HI                           0x00000831
1047 
1048 #define REG_A6XX_CP_MISC_CNTL                                   0x00000840
1049 
1050 #define REG_A6XX_CP_ROQ_THRESHOLDS_1                            0x000008c1
1051 
1052 #define REG_A6XX_CP_ROQ_THRESHOLDS_2                            0x000008c2
1053 
1054 #define REG_A6XX_CP_MEM_POOL_SIZE                               0x000008c3
1055 
1056 #define REG_A6XX_CP_CHICKEN_DBG                                 0x00000841
1057 
1058 #define REG_A6XX_CP_ADDR_MODE_CNTL                              0x00000842
1059 
1060 #define REG_A6XX_CP_DBG_ECO_CNTL                                0x00000843
1061 
1062 #define REG_A6XX_CP_PROTECT_CNTL                                0x0000084f
1063 
1064 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1065 
1066 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1067 
1068 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1069 
1070 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1071 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK                     0x0003ffff
1072 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT                    0
1073 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1074 {
1075         return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1076 }
1077 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK                      0x7ffc0000
1078 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT                     18
1079 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1080 {
1081         return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1082 }
1083 #define A6XX_CP_PROTECT_REG_READ                                0x80000000
1084 
1085 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL                         0x000008a0
1086 
1087 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO                 0x000008a1
1088 
1089 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI                 0x000008a2
1090 
1091 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO      0x000008a3
1092 
1093 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI      0x000008a4
1094 
1095 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO  0x000008a5
1096 
1097 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI  0x000008a6
1098 
1099 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO     0x000008a7
1100 
1101 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI     0x000008a8
1102 
1103 #define REG_A6XX_CP_PERFCTR_CP_SEL_0                            0x000008d0
1104 
1105 #define REG_A6XX_CP_PERFCTR_CP_SEL_1                            0x000008d1
1106 
1107 #define REG_A6XX_CP_PERFCTR_CP_SEL_2                            0x000008d2
1108 
1109 #define REG_A6XX_CP_PERFCTR_CP_SEL_3                            0x000008d3
1110 
1111 #define REG_A6XX_CP_PERFCTR_CP_SEL_4                            0x000008d4
1112 
1113 #define REG_A6XX_CP_PERFCTR_CP_SEL_5                            0x000008d5
1114 
1115 #define REG_A6XX_CP_PERFCTR_CP_SEL_6                            0x000008d6
1116 
1117 #define REG_A6XX_CP_PERFCTR_CP_SEL_7                            0x000008d7
1118 
1119 #define REG_A6XX_CP_PERFCTR_CP_SEL_8                            0x000008d8
1120 
1121 #define REG_A6XX_CP_PERFCTR_CP_SEL_9                            0x000008d9
1122 
1123 #define REG_A6XX_CP_PERFCTR_CP_SEL_10                           0x000008da
1124 
1125 #define REG_A6XX_CP_PERFCTR_CP_SEL_11                           0x000008db
1126 
1127 #define REG_A6XX_CP_PERFCTR_CP_SEL_12                           0x000008dc
1128 
1129 #define REG_A6XX_CP_PERFCTR_CP_SEL_13                           0x000008dd
1130 
1131 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO                        0x00000900
1132 
1133 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI                        0x00000901
1134 
1135 #define REG_A6XX_CP_CRASH_DUMP_CNTL                             0x00000902
1136 
1137 #define REG_A6XX_CP_CRASH_DUMP_STATUS                           0x00000903
1138 
1139 #define REG_A6XX_CP_SQE_STAT_ADDR                               0x00000908
1140 
1141 #define REG_A6XX_CP_SQE_STAT_DATA                               0x00000909
1142 
1143 #define REG_A6XX_CP_DRAW_STATE_ADDR                             0x0000090a
1144 
1145 #define REG_A6XX_CP_DRAW_STATE_DATA                             0x0000090b
1146 
1147 #define REG_A6XX_CP_ROQ_DBG_ADDR                                0x0000090c
1148 
1149 #define REG_A6XX_CP_ROQ_DBG_DATA                                0x0000090d
1150 
1151 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR                           0x0000090e
1152 
1153 #define REG_A6XX_CP_MEM_POOL_DBG_DATA                           0x0000090f
1154 
1155 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR                          0x00000910
1156 
1157 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA                          0x00000911
1158 
1159 #define REG_A6XX_CP_IB1_BASE                                    0x00000928
1160 
1161 #define REG_A6XX_CP_IB1_BASE_HI                                 0x00000929
1162 
1163 #define REG_A6XX_CP_IB1_REM_SIZE                                0x0000092a
1164 
1165 #define REG_A6XX_CP_IB2_BASE                                    0x0000092b
1166 
1167 #define REG_A6XX_CP_IB2_BASE_HI                                 0x0000092c
1168 
1169 #define REG_A6XX_CP_IB2_REM_SIZE                                0x0000092d
1170 
1171 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO                        0x00000980
1172 
1173 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI                        0x00000981
1174 
1175 #define REG_A6XX_CP_AHB_CNTL                                    0x0000098d
1176 
1177 #define REG_A6XX_CP_APERTURE_CNTL_HOST                          0x00000a00
1178 
1179 #define REG_A6XX_CP_APERTURE_CNTL_CD                            0x00000a03
1180 
1181 #define REG_A6XX_VSC_ADDR_MODE_CNTL                             0x00000c01
1182 
1183 #define REG_A6XX_RBBM_INT_0_STATUS                              0x00000201
1184 
1185 #define REG_A6XX_RBBM_STATUS                                    0x00000210
1186 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB                       0x00800000
1187 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP                    0x00400000
1188 #define A6XX_RBBM_STATUS_HLSQ_BUSY                              0x00200000
1189 #define A6XX_RBBM_STATUS_VSC_BUSY                               0x00100000
1190 #define A6XX_RBBM_STATUS_TPL1_BUSY                              0x00080000
1191 #define A6XX_RBBM_STATUS_SP_BUSY                                0x00040000
1192 #define A6XX_RBBM_STATUS_UCHE_BUSY                              0x00020000
1193 #define A6XX_RBBM_STATUS_VPC_BUSY                               0x00010000
1194 #define A6XX_RBBM_STATUS_VFD_BUSY                               0x00008000
1195 #define A6XX_RBBM_STATUS_TESS_BUSY                              0x00004000
1196 #define A6XX_RBBM_STATUS_PC_VSD_BUSY                            0x00002000
1197 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00001000
1198 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY                          0x00000800
1199 #define A6XX_RBBM_STATUS_LRZ_BUSY                               0x00000400
1200 #define A6XX_RBBM_STATUS_A2D_BUSY                               0x00000200
1201 #define A6XX_RBBM_STATUS_CCU_BUSY                               0x00000100
1202 #define A6XX_RBBM_STATUS_RB_BUSY                                0x00000080
1203 #define A6XX_RBBM_STATUS_RAS_BUSY                               0x00000040
1204 #define A6XX_RBBM_STATUS_TSE_BUSY                               0x00000020
1205 #define A6XX_RBBM_STATUS_VBIF_BUSY                              0x00000010
1206 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY                          0x00000008
1207 #define A6XX_RBBM_STATUS_CP_BUSY                                0x00000004
1208 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER                  0x00000002
1209 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER                  0x00000001
1210 
1211 #define REG_A6XX_RBBM_STATUS3                                   0x00000213
1212 
1213 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS                      0x00000215
1214 
1215 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO                           0x00000400
1216 
1217 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI                           0x00000401
1218 
1219 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO                           0x00000402
1220 
1221 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI                           0x00000403
1222 
1223 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO                           0x00000404
1224 
1225 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI                           0x00000405
1226 
1227 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO                           0x00000406
1228 
1229 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI                           0x00000407
1230 
1231 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO                           0x00000408
1232 
1233 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI                           0x00000409
1234 
1235 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO                           0x0000040a
1236 
1237 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI                           0x0000040b
1238 
1239 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO                           0x0000040c
1240 
1241 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI                           0x0000040d
1242 
1243 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO                           0x0000040e
1244 
1245 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI                           0x0000040f
1246 
1247 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO                           0x00000410
1248 
1249 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI                           0x00000411
1250 
1251 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO                           0x00000412
1252 
1253 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI                           0x00000413
1254 
1255 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO                          0x00000414
1256 
1257 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI                          0x00000415
1258 
1259 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO                          0x00000416
1260 
1261 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI                          0x00000417
1262 
1263 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO                          0x00000418
1264 
1265 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI                          0x00000419
1266 
1267 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO                          0x0000041a
1268 
1269 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI                          0x0000041b
1270 
1271 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO                         0x0000041c
1272 
1273 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI                         0x0000041d
1274 
1275 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO                         0x0000041e
1276 
1277 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI                         0x0000041f
1278 
1279 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO                         0x00000420
1280 
1281 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI                         0x00000421
1282 
1283 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO                         0x00000422
1284 
1285 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI                         0x00000423
1286 
1287 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO                           0x00000424
1288 
1289 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI                           0x00000425
1290 
1291 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO                           0x00000426
1292 
1293 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI                           0x00000427
1294 
1295 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO                           0x00000428
1296 
1297 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI                           0x00000429
1298 
1299 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO                           0x0000042a
1300 
1301 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI                           0x0000042b
1302 
1303 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO                           0x0000042c
1304 
1305 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI                           0x0000042d
1306 
1307 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO                           0x0000042e
1308 
1309 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI                           0x0000042f
1310 
1311 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO                           0x00000430
1312 
1313 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI                           0x00000431
1314 
1315 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO                           0x00000432
1316 
1317 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI                           0x00000433
1318 
1319 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO                          0x00000434
1320 
1321 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI                          0x00000435
1322 
1323 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO                          0x00000436
1324 
1325 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI                          0x00000437
1326 
1327 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO                          0x00000438
1328 
1329 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI                          0x00000439
1330 
1331 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO                          0x0000043a
1332 
1333 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI                          0x0000043b
1334 
1335 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO                          0x0000043c
1336 
1337 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI                          0x0000043d
1338 
1339 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO                          0x0000043e
1340 
1341 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI                          0x0000043f
1342 
1343 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO                          0x00000440
1344 
1345 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI                          0x00000441
1346 
1347 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO                          0x00000442
1348 
1349 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI                          0x00000443
1350 
1351 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO                         0x00000444
1352 
1353 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI                         0x00000445
1354 
1355 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO                         0x00000446
1356 
1357 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI                         0x00000447
1358 
1359 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO                         0x00000448
1360 
1361 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI                         0x00000449
1362 
1363 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO                         0x0000044a
1364 
1365 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI                         0x0000044b
1366 
1367 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO                         0x0000044c
1368 
1369 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI                         0x0000044d
1370 
1371 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO                         0x0000044e
1372 
1373 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI                         0x0000044f
1374 
1375 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO                          0x00000450
1376 
1377 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI                          0x00000451
1378 
1379 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO                          0x00000452
1380 
1381 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI                          0x00000453
1382 
1383 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO                          0x00000454
1384 
1385 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI                          0x00000455
1386 
1387 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO                          0x00000456
1388 
1389 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI                          0x00000457
1390 
1391 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO                          0x00000458
1392 
1393 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI                          0x00000459
1394 
1395 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO                          0x0000045a
1396 
1397 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI                          0x0000045b
1398 
1399 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO                          0x0000045c
1400 
1401 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI                          0x0000045d
1402 
1403 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO                          0x0000045e
1404 
1405 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI                          0x0000045f
1406 
1407 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO                          0x00000460
1408 
1409 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI                          0x00000461
1410 
1411 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO                          0x00000462
1412 
1413 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI                          0x00000463
1414 
1415 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO                          0x00000464
1416 
1417 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI                          0x00000465
1418 
1419 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO                          0x00000466
1420 
1421 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI                          0x00000467
1422 
1423 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO                          0x00000468
1424 
1425 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI                          0x00000469
1426 
1427 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO                          0x0000046a
1428 
1429 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI                          0x00000465
1430 
1431 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO                          0x00000466
1432 
1433 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI                          0x00000467
1434 
1435 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO                          0x00000468
1436 
1437 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI                          0x00000469
1438 
1439 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO                          0x0000046a
1440 
1441 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI                          0x0000046b
1442 
1443 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO                          0x0000046c
1444 
1445 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI                          0x0000046d
1446 
1447 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO                          0x0000046e
1448 
1449 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI                          0x0000046f
1450 
1451 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO                          0x00000470
1452 
1453 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI                          0x00000471
1454 
1455 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO                          0x00000472
1456 
1457 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI                          0x00000473
1458 
1459 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO                          0x00000474
1460 
1461 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI                          0x00000475
1462 
1463 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO                         0x00000476
1464 
1465 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI                         0x00000477
1466 
1467 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO                         0x00000478
1468 
1469 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI                         0x00000479
1470 
1471 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO                         0x0000047a
1472 
1473 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI                         0x0000047b
1474 
1475 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO                         0x0000047c
1476 
1477 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI                         0x0000047d
1478 
1479 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO                         0x0000047e
1480 
1481 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI                         0x0000047f
1482 
1483 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO                         0x00000480
1484 
1485 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI                         0x00000481
1486 
1487 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO                         0x00000482
1488 
1489 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI                         0x00000483
1490 
1491 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO                         0x00000484
1492 
1493 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI                         0x00000485
1494 
1495 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO                         0x00000486
1496 
1497 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI                         0x00000487
1498 
1499 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO                         0x00000488
1500 
1501 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI                         0x00000489
1502 
1503 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO                        0x0000048a
1504 
1505 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI                        0x0000048b
1506 
1507 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO                        0x0000048c
1508 
1509 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI                        0x0000048d
1510 
1511 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO                           0x0000048e
1512 
1513 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI                           0x0000048f
1514 
1515 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO                           0x00000490
1516 
1517 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI                           0x00000491
1518 
1519 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO                           0x00000492
1520 
1521 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI                           0x00000493
1522 
1523 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO                           0x00000494
1524 
1525 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI                           0x00000495
1526 
1527 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO                           0x00000496
1528 
1529 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI                           0x00000497
1530 
1531 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO                           0x00000498
1532 
1533 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI                           0x00000499
1534 
1535 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO                           0x0000049a
1536 
1537 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI                           0x0000049b
1538 
1539 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO                           0x0000049c
1540 
1541 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI                           0x0000049d
1542 
1543 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO                           0x0000049e
1544 
1545 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI                           0x0000049f
1546 
1547 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO                           0x000004a0
1548 
1549 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI                           0x000004a1
1550 
1551 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO                          0x000004a2
1552 
1553 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI                          0x000004a3
1554 
1555 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO                          0x000004a4
1556 
1557 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI                          0x000004a5
1558 
1559 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO                           0x000004a6
1560 
1561 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI                           0x000004a7
1562 
1563 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO                           0x000004a8
1564 
1565 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI                           0x000004a9
1566 
1567 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO                           0x000004aa
1568 
1569 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI                           0x000004ab
1570 
1571 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO                           0x000004ac
1572 
1573 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI                           0x000004ad
1574 
1575 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO                           0x000004ae
1576 
1577 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI                           0x000004af
1578 
1579 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO                           0x000004b0
1580 
1581 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI                           0x000004b1
1582 
1583 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO                           0x000004b2
1584 
1585 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI                           0x000004b3
1586 
1587 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO                           0x000004b4
1588 
1589 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI                           0x000004b5
1590 
1591 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO                           0x000004b6
1592 
1593 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI                           0x000004b7
1594 
1595 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO                           0x000004b8
1596 
1597 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI                           0x000004b9
1598 
1599 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO                          0x000004ba
1600 
1601 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI                          0x000004bb
1602 
1603 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO                          0x000004bc
1604 
1605 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI                          0x000004bd
1606 
1607 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO                          0x000004be
1608 
1609 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI                          0x000004bf
1610 
1611 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO                          0x000004c0
1612 
1613 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI                          0x000004c1
1614 
1615 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO                          0x000004c2
1616 
1617 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI                          0x000004c3
1618 
1619 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO                          0x000004c4
1620 
1621 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI                          0x000004c5
1622 
1623 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO                          0x000004c6
1624 
1625 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI                          0x000004c7
1626 
1627 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO                          0x000004c8
1628 
1629 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI                          0x000004c9
1630 
1631 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO                          0x000004ca
1632 
1633 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI                          0x000004cb
1634 
1635 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO                          0x000004cc
1636 
1637 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI                          0x000004cd
1638 
1639 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO                          0x000004ce
1640 
1641 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI                          0x000004cf
1642 
1643 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO                          0x000004d0
1644 
1645 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI                          0x000004d1
1646 
1647 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO                          0x000004d2
1648 
1649 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI                          0x000004d3
1650 
1651 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO                          0x000004d4
1652 
1653 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI                          0x000004d5
1654 
1655 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO                           0x000004d6
1656 
1657 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI                           0x000004d7
1658 
1659 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO                           0x000004d8
1660 
1661 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI                           0x000004d9
1662 
1663 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO                           0x000004da
1664 
1665 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI                           0x000004db
1666 
1667 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO                           0x000004dc
1668 
1669 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI                           0x000004dd
1670 
1671 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO                           0x000004de
1672 
1673 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI                           0x000004df
1674 
1675 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO                           0x000004e0
1676 
1677 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI                           0x000004e1
1678 
1679 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO                           0x000004e2
1680 
1681 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI                           0x000004e3
1682 
1683 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO                           0x000004e4
1684 
1685 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI                           0x000004e5
1686 
1687 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO                          0x000004e6
1688 
1689 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI                          0x000004e7
1690 
1691 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO                          0x000004e8
1692 
1693 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI                          0x000004e9
1694 
1695 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO                          0x000004ea
1696 
1697 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI                          0x000004eb
1698 
1699 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO                          0x000004ec
1700 
1701 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI                          0x000004ed
1702 
1703 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO                          0x000004ee
1704 
1705 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI                          0x000004ef
1706 
1707 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO                          0x000004f0
1708 
1709 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI                          0x000004f1
1710 
1711 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO                          0x000004f2
1712 
1713 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI                          0x000004f3
1714 
1715 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO                          0x000004f4
1716 
1717 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI                          0x000004f5
1718 
1719 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO                          0x000004f6
1720 
1721 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI                          0x000004f7
1722 
1723 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO                          0x000004f8
1724 
1725 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI                          0x000004f9
1726 
1727 #define REG_A6XX_RBBM_PERFCTR_CNTL                              0x00000500
1728 
1729 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000501
1730 
1731 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000502
1732 
1733 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2                         0x00000503
1734 
1735 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3                         0x00000504
1736 
1737 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000505
1738 
1739 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000506
1740 
1741 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0                        0x00000507
1742 
1743 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1                        0x00000508
1744 
1745 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2                        0x00000509
1746 
1747 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3                        0x0000050a
1748 
1749 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED                   0x0000050b
1750 
1751 #define REG_A6XX_RBBM_ISDB_CNT                                  0x00000533
1752 
1753 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL                         0x0000f400
1754 
1755 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO                0x0000f800
1756 
1757 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI                0x0000f801
1758 
1759 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE                   0x0000f802
1760 
1761 #define REG_A6XX_RBBM_SECVID_TSB_CNTL                           0x0000f803
1762 
1763 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL                 0x0000f810
1764 
1765 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL                      0x00000010
1766 
1767 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL                   0x0000001f
1768 
1769 #define REG_A6XX_RBBM_INT_CLEAR_CMD                             0x00000037
1770 
1771 #define REG_A6XX_RBBM_INT_0_MASK                                0x00000038
1772 
1773 #define REG_A6XX_RBBM_SP_HYST_CNT                               0x00000042
1774 
1775 #define REG_A6XX_RBBM_SW_RESET_CMD                              0x00000043
1776 
1777 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT                         0x00000044
1778 
1779 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD                        0x00000045
1780 
1781 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2                       0x00000046
1782 
1783 #define REG_A6XX_RBBM_CLOCK_CNTL                                0x000000ae
1784 
1785 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0                            0x000000b0
1786 
1787 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1                            0x000000b1
1788 
1789 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2                            0x000000b2
1790 
1791 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3                            0x000000b3
1792 
1793 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0                           0x000000b4
1794 
1795 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1                           0x000000b5
1796 
1797 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2                           0x000000b6
1798 
1799 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3                           0x000000b7
1800 
1801 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0                           0x000000b8
1802 
1803 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1                           0x000000b9
1804 
1805 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2                           0x000000ba
1806 
1807 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3                           0x000000bb
1808 
1809 #define REG_A6XX_RBBM_CLOCK_HYST_SP0                            0x000000bc
1810 
1811 #define REG_A6XX_RBBM_CLOCK_HYST_SP1                            0x000000bd
1812 
1813 #define REG_A6XX_RBBM_CLOCK_HYST_SP2                            0x000000be
1814 
1815 #define REG_A6XX_RBBM_CLOCK_HYST_SP3                            0x000000bf
1816 
1817 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0                            0x000000c0
1818 
1819 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1                            0x000000c1
1820 
1821 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2                            0x000000c2
1822 
1823 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3                            0x000000c3
1824 
1825 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0                           0x000000c4
1826 
1827 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1                           0x000000c5
1828 
1829 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2                           0x000000c6
1830 
1831 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3                           0x000000c7
1832 
1833 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0                           0x000000c8
1834 
1835 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1                           0x000000c9
1836 
1837 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2                           0x000000ca
1838 
1839 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3                           0x000000cb
1840 
1841 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0                           0x000000cc
1842 
1843 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1                           0x000000cd
1844 
1845 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2                           0x000000ce
1846 
1847 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3                           0x000000cf
1848 
1849 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0                           0x000000d0
1850 
1851 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1                           0x000000d1
1852 
1853 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2                           0x000000d2
1854 
1855 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3                           0x000000d3
1856 
1857 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0                          0x000000d4
1858 
1859 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1                          0x000000d5
1860 
1861 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2                          0x000000d6
1862 
1863 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3                          0x000000d7
1864 
1865 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0                          0x000000d8
1866 
1867 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1                          0x000000d9
1868 
1869 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2                          0x000000da
1870 
1871 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3                          0x000000db
1872 
1873 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0                          0x000000dc
1874 
1875 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1                          0x000000dd
1876 
1877 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2                          0x000000de
1878 
1879 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3                          0x000000df
1880 
1881 #define REG_A6XX_RBBM_CLOCK_HYST_TP0                            0x000000e0
1882 
1883 #define REG_A6XX_RBBM_CLOCK_HYST_TP1                            0x000000e1
1884 
1885 #define REG_A6XX_RBBM_CLOCK_HYST_TP2                            0x000000e2
1886 
1887 #define REG_A6XX_RBBM_CLOCK_HYST_TP3                            0x000000e3
1888 
1889 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0                           0x000000e4
1890 
1891 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1                           0x000000e5
1892 
1893 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2                           0x000000e6
1894 
1895 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3                           0x000000e7
1896 
1897 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0                           0x000000e8
1898 
1899 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1                           0x000000e9
1900 
1901 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2                           0x000000ea
1902 
1903 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3                           0x000000eb
1904 
1905 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0                           0x000000ec
1906 
1907 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1                           0x000000ed
1908 
1909 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2                           0x000000ee
1910 
1911 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3                           0x000000ef
1912 
1913 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0                            0x000000f0
1914 
1915 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1                            0x000000f1
1916 
1917 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2                            0x000000f2
1918 
1919 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3                            0x000000f3
1920 
1921 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0                           0x000000f4
1922 
1923 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1                           0x000000f5
1924 
1925 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2                           0x000000f6
1926 
1927 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3                           0x000000f7
1928 
1929 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0                           0x000000f8
1930 
1931 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1                           0x000000f9
1932 
1933 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2                           0x000000fa
1934 
1935 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3                           0x000000fb
1936 
1937 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0                        0x00000100
1938 
1939 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1                        0x00000101
1940 
1941 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2                        0x00000102
1942 
1943 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3                        0x00000103
1944 
1945 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC                            0x00000104
1946 
1947 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC                           0x00000105
1948 
1949 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC                           0x00000106
1950 
1951 #define REG_A6XX_RBBM_CLOCK_HYST_RAC                            0x00000107
1952 
1953 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM                   0x00000108
1954 
1955 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM                  0x00000109
1956 
1957 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM                   0x0000010a
1958 
1959 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE                           0x0000010b
1960 
1961 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE                          0x0000010c
1962 
1963 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE                          0x0000010d
1964 
1965 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE                          0x0000010e
1966 
1967 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE                          0x0000010f
1968 
1969 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE                           0x00000110
1970 
1971 #define REG_A6XX_RBBM_CLOCK_MODE_VFD                            0x00000111
1972 
1973 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD                           0x00000112
1974 
1975 #define REG_A6XX_RBBM_CLOCK_HYST_VFD                            0x00000113
1976 
1977 #define REG_A6XX_RBBM_CLOCK_MODE_GPC                            0x00000114
1978 
1979 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC                           0x00000115
1980 
1981 #define REG_A6XX_RBBM_CLOCK_HYST_GPC                            0x00000116
1982 
1983 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2                        0x00000117
1984 
1985 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX                         0x00000118
1986 
1987 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX                        0x00000119
1988 
1989 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX                         0x0000011a
1990 
1991 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ                           0x0000011b
1992 
1993 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ                          0x0000011c
1994 
1995 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A                          0x00000600
1996 
1997 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B                          0x00000601
1998 
1999 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C                          0x00000602
2000 
2001 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D                          0x00000603
2002 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK             0x000000ff
2003 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT            0
2004 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
2005 {
2006         return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
2007 }
2008 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK           0x0000ff00
2009 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT          8
2010 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
2011 {
2012         return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
2013 }
2014 
2015 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT                          0x00000604
2016 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK                0x0000003f
2017 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT               0
2018 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
2019 {
2020         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
2021 }
2022 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK                  0x00007000
2023 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT                 12
2024 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
2025 {
2026         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
2027 }
2028 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK                   0xf0000000
2029 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT                  28
2030 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
2031 {
2032         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
2033 }
2034 
2035 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM                          0x00000605
2036 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK                 0x0f000000
2037 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT                24
2038 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
2039 {
2040         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
2041 }
2042 
2043 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0                         0x00000608
2044 
2045 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1                         0x00000609
2046 
2047 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2                         0x0000060a
2048 
2049 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3                         0x0000060b
2050 
2051 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0                        0x0000060c
2052 
2053 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1                        0x0000060d
2054 
2055 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2                        0x0000060e
2056 
2057 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3                        0x0000060f
2058 
2059 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0                        0x00000610
2060 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK               0x0000000f
2061 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT              0
2062 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
2063 {
2064         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
2065 }
2066 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK               0x000000f0
2067 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT              4
2068 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
2069 {
2070         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
2071 }
2072 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK               0x00000f00
2073 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT              8
2074 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
2075 {
2076         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
2077 }
2078 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK               0x0000f000
2079 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT              12
2080 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
2081 {
2082         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
2083 }
2084 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK               0x000f0000
2085 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT              16
2086 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
2087 {
2088         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
2089 }
2090 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK               0x00f00000
2091 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT              20
2092 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
2093 {
2094         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
2095 }
2096 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK               0x0f000000
2097 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT              24
2098 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
2099 {
2100         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
2101 }
2102 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK               0xf0000000
2103 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT              28
2104 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
2105 {
2106         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
2107 }
2108 
2109 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1                        0x00000611
2110 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK               0x0000000f
2111 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT              0
2112 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
2113 {
2114         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
2115 }
2116 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK               0x000000f0
2117 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT              4
2118 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
2119 {
2120         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
2121 }
2122 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK              0x00000f00
2123 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT             8
2124 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
2125 {
2126         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
2127 }
2128 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK              0x0000f000
2129 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT             12
2130 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
2131 {
2132         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
2133 }
2134 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK              0x000f0000
2135 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT             16
2136 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
2137 {
2138         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
2139 }
2140 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK              0x00f00000
2141 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT             20
2142 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
2143 {
2144         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
2145 }
2146 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK              0x0f000000
2147 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT             24
2148 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
2149 {
2150         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
2151 }
2152 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK              0xf0000000
2153 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT             28
2154 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2155 {
2156         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2157 }
2158 
2159 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1                     0x0000062f
2160 
2161 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2                     0x00000630
2162 
2163 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0                          0x00000cd8
2164 
2165 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1                          0x00000cd9
2166 
2167 #define REG_A6XX_GRAS_ADDR_MODE_CNTL                            0x00008601
2168 
2169 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0                         0x00008610
2170 
2171 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1                         0x00008611
2172 
2173 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2                         0x00008612
2174 
2175 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3                         0x00008613
2176 
2177 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0                         0x00008614
2178 
2179 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1                         0x00008615
2180 
2181 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2                         0x00008616
2182 
2183 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3                         0x00008617
2184 
2185 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0                         0x00008618
2186 
2187 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1                         0x00008619
2188 
2189 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2                         0x0000861a
2190 
2191 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3                         0x0000861b
2192 
2193 #define REG_A6XX_RB_ADDR_MODE_CNTL                              0x00008e05
2194 
2195 #define REG_A6XX_RB_NC_MODE_CNTL                                0x00008e08
2196 
2197 #define REG_A6XX_RB_PERFCTR_RB_SEL_0                            0x00008e10
2198 
2199 #define REG_A6XX_RB_PERFCTR_RB_SEL_1                            0x00008e11
2200 
2201 #define REG_A6XX_RB_PERFCTR_RB_SEL_2                            0x00008e12
2202 
2203 #define REG_A6XX_RB_PERFCTR_RB_SEL_3                            0x00008e13
2204 
2205 #define REG_A6XX_RB_PERFCTR_RB_SEL_4                            0x00008e14
2206 
2207 #define REG_A6XX_RB_PERFCTR_RB_SEL_5                            0x00008e15
2208 
2209 #define REG_A6XX_RB_PERFCTR_RB_SEL_6                            0x00008e16
2210 
2211 #define REG_A6XX_RB_PERFCTR_RB_SEL_7                            0x00008e17
2212 
2213 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0                           0x00008e18
2214 
2215 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1                           0x00008e19
2216 
2217 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2                           0x00008e1a
2218 
2219 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3                           0x00008e1b
2220 
2221 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4                           0x00008e1c
2222 
2223 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0                           0x00008e2c
2224 
2225 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1                           0x00008e2d
2226 
2227 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2                           0x00008e2e
2228 
2229 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3                           0x00008e2f
2230 
2231 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD                    0x00008e3d
2232 
2233 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE            0x00008e50
2234 
2235 #define REG_A6XX_PC_DBG_ECO_CNTL                                0x00009e00
2236 
2237 #define REG_A6XX_PC_ADDR_MODE_CNTL                              0x00009e01
2238 
2239 #define REG_A6XX_PC_PERFCTR_PC_SEL_0                            0x00009e34
2240 
2241 #define REG_A6XX_PC_PERFCTR_PC_SEL_1                            0x00009e35
2242 
2243 #define REG_A6XX_PC_PERFCTR_PC_SEL_2                            0x00009e36
2244 
2245 #define REG_A6XX_PC_PERFCTR_PC_SEL_3                            0x00009e37
2246 
2247 #define REG_A6XX_PC_PERFCTR_PC_SEL_4                            0x00009e38
2248 
2249 #define REG_A6XX_PC_PERFCTR_PC_SEL_5                            0x00009e39
2250 
2251 #define REG_A6XX_PC_PERFCTR_PC_SEL_6                            0x00009e3a
2252 
2253 #define REG_A6XX_PC_PERFCTR_PC_SEL_7                            0x00009e3b
2254 
2255 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL                            0x0000be05
2256 
2257 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0                        0x0000be10
2258 
2259 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1                        0x0000be11
2260 
2261 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2                        0x0000be12
2262 
2263 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3                        0x0000be13
2264 
2265 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4                        0x0000be14
2266 
2267 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5                        0x0000be15
2268 
2269 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE                     0x0000c800
2270 
2271 #define REG_A6XX_HLSQ_DBG_READ_SEL                              0x0000d000
2272 
2273 #define REG_A6XX_VFD_ADDR_MODE_CNTL                             0x0000a601
2274 
2275 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0                          0x0000a610
2276 
2277 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1                          0x0000a611
2278 
2279 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2                          0x0000a612
2280 
2281 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3                          0x0000a613
2282 
2283 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4                          0x0000a614
2284 
2285 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5                          0x0000a615
2286 
2287 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6                          0x0000a616
2288 
2289 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7                          0x0000a617
2290 
2291 #define REG_A6XX_VPC_ADDR_MODE_CNTL                             0x00009601
2292 
2293 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0                          0x00009604
2294 
2295 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1                          0x00009605
2296 
2297 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2                          0x00009606
2298 
2299 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3                          0x00009607
2300 
2301 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4                          0x00009608
2302 
2303 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5                          0x00009609
2304 
2305 #define REG_A6XX_UCHE_ADDR_MODE_CNTL                            0x00000e00
2306 
2307 #define REG_A6XX_UCHE_MODE_CNTL                                 0x00000e01
2308 
2309 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO                        0x00000e05
2310 
2311 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI                        0x00000e06
2312 
2313 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO                        0x00000e07
2314 
2315 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI                        0x00000e08
2316 
2317 #define REG_A6XX_UCHE_TRAP_BASE_LO                              0x00000e09
2318 
2319 #define REG_A6XX_UCHE_TRAP_BASE_HI                              0x00000e0a
2320 
2321 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO                         0x00000e0b
2322 
2323 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI                         0x00000e0c
2324 
2325 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO                         0x00000e0d
2326 
2327 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI                         0x00000e0e
2328 
2329 #define REG_A6XX_UCHE_CACHE_WAYS                                0x00000e17
2330 
2331 #define REG_A6XX_UCHE_FILTER_CNTL                               0x00000e18
2332 
2333 #define REG_A6XX_UCHE_CLIENT_PF                                 0x00000e19
2334 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK                       0x000000ff
2335 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT                      0
2336 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2337 {
2338         return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2339 }
2340 
2341 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0                        0x00000e1c
2342 
2343 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1                        0x00000e1d
2344 
2345 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2                        0x00000e1e
2346 
2347 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3                        0x00000e1f
2348 
2349 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4                        0x00000e20
2350 
2351 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5                        0x00000e21
2352 
2353 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6                        0x00000e22
2354 
2355 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7                        0x00000e23
2356 
2357 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8                        0x00000e24
2358 
2359 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9                        0x00000e25
2360 
2361 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10                       0x00000e26
2362 
2363 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11                       0x00000e27
2364 
2365 #define REG_A6XX_SP_ADDR_MODE_CNTL                              0x0000ae01
2366 
2367 #define REG_A6XX_SP_NC_MODE_CNTL                                0x0000ae02
2368 
2369 #define REG_A6XX_SP_PERFCTR_SP_SEL_0                            0x0000ae10
2370 
2371 #define REG_A6XX_SP_PERFCTR_SP_SEL_1                            0x0000ae11
2372 
2373 #define REG_A6XX_SP_PERFCTR_SP_SEL_2                            0x0000ae12
2374 
2375 #define REG_A6XX_SP_PERFCTR_SP_SEL_3                            0x0000ae13
2376 
2377 #define REG_A6XX_SP_PERFCTR_SP_SEL_4                            0x0000ae14
2378 
2379 #define REG_A6XX_SP_PERFCTR_SP_SEL_5                            0x0000ae15
2380 
2381 #define REG_A6XX_SP_PERFCTR_SP_SEL_6                            0x0000ae16
2382 
2383 #define REG_A6XX_SP_PERFCTR_SP_SEL_7                            0x0000ae17
2384 
2385 #define REG_A6XX_SP_PERFCTR_SP_SEL_8                            0x0000ae18
2386 
2387 #define REG_A6XX_SP_PERFCTR_SP_SEL_9                            0x0000ae19
2388 
2389 #define REG_A6XX_SP_PERFCTR_SP_SEL_10                           0x0000ae1a
2390 
2391 #define REG_A6XX_SP_PERFCTR_SP_SEL_11                           0x0000ae1b
2392 
2393 #define REG_A6XX_SP_PERFCTR_SP_SEL_12                           0x0000ae1c
2394 
2395 #define REG_A6XX_SP_PERFCTR_SP_SEL_13                           0x0000ae1d
2396 
2397 #define REG_A6XX_SP_PERFCTR_SP_SEL_14                           0x0000ae1e
2398 
2399 #define REG_A6XX_SP_PERFCTR_SP_SEL_15                           0x0000ae1f
2400 
2401 #define REG_A6XX_SP_PERFCTR_SP_SEL_16                           0x0000ae20
2402 
2403 #define REG_A6XX_SP_PERFCTR_SP_SEL_17                           0x0000ae21
2404 
2405 #define REG_A6XX_SP_PERFCTR_SP_SEL_18                           0x0000ae22
2406 
2407 #define REG_A6XX_SP_PERFCTR_SP_SEL_19                           0x0000ae23
2408 
2409 #define REG_A6XX_SP_PERFCTR_SP_SEL_20                           0x0000ae24
2410 
2411 #define REG_A6XX_SP_PERFCTR_SP_SEL_21                           0x0000ae25
2412 
2413 #define REG_A6XX_SP_PERFCTR_SP_SEL_22                           0x0000ae26
2414 
2415 #define REG_A6XX_SP_PERFCTR_SP_SEL_23                           0x0000ae27
2416 
2417 #define REG_A6XX_TPL1_ADDR_MODE_CNTL                            0x0000b601
2418 
2419 #define REG_A6XX_TPL1_NC_MODE_CNTL                              0x0000b604
2420 
2421 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0                          0x0000b610
2422 
2423 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1                          0x0000b611
2424 
2425 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2                          0x0000b612
2426 
2427 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3                          0x0000b613
2428 
2429 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4                          0x0000b614
2430 
2431 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5                          0x0000b615
2432 
2433 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6                          0x0000b616
2434 
2435 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7                          0x0000b617
2436 
2437 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8                          0x0000b618
2438 
2439 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9                          0x0000b619
2440 
2441 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10                         0x0000b61a
2442 
2443 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11                         0x0000b61b
2444 
2445 #define REG_A6XX_VBIF_VERSION                                   0x00003000
2446 
2447 #define REG_A6XX_VBIF_CLKON                                     0x00003001
2448 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS                        0x00000002
2449 
2450 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
2451 
2452 #define REG_A6XX_VBIF_XIN_HALT_CTRL0                            0x00003080
2453 
2454 #define REG_A6XX_VBIF_XIN_HALT_CTRL1                            0x00003081
2455 
2456 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL                         0x00003084
2457 
2458 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0                           0x00003085
2459 
2460 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1                           0x00003086
2461 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK                0x0000000f
2462 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT               0
2463 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
2464 {
2465         return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
2466 }
2467 
2468 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0                           0x00003087
2469 
2470 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1                           0x00003088
2471 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK                0x000001ff
2472 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT               0
2473 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
2474 {
2475         return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
2476 }
2477 
2478 #define REG_A6XX_VBIF_TEST_BUS_OUT                              0x0000308c
2479 
2480 #define REG_A6XX_VBIF_PERF_CNT_SEL0                             0x000030d0
2481 
2482 #define REG_A6XX_VBIF_PERF_CNT_SEL1                             0x000030d1
2483 
2484 #define REG_A6XX_VBIF_PERF_CNT_SEL2                             0x000030d2
2485 
2486 #define REG_A6XX_VBIF_PERF_CNT_SEL3                             0x000030d3
2487 
2488 #define REG_A6XX_VBIF_PERF_CNT_LOW0                             0x000030d8
2489 
2490 #define REG_A6XX_VBIF_PERF_CNT_LOW1                             0x000030d9
2491 
2492 #define REG_A6XX_VBIF_PERF_CNT_LOW2                             0x000030da
2493 
2494 #define REG_A6XX_VBIF_PERF_CNT_LOW3                             0x000030db
2495 
2496 #define REG_A6XX_VBIF_PERF_CNT_HIGH0                            0x000030e0
2497 
2498 #define REG_A6XX_VBIF_PERF_CNT_HIGH1                            0x000030e1
2499 
2500 #define REG_A6XX_VBIF_PERF_CNT_HIGH2                            0x000030e2
2501 
2502 #define REG_A6XX_VBIF_PERF_CNT_HIGH3                            0x000030e3
2503 
2504 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0                          0x00003100
2505 
2506 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1                          0x00003101
2507 
2508 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2                          0x00003102
2509 
2510 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0                         0x00003110
2511 
2512 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1                         0x00003111
2513 
2514 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2                         0x00003112
2515 
2516 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0                        0x00003118
2517 
2518 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1                        0x00003119
2519 
2520 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2                        0x0000311a
2521 
2522 #define REG_A6XX_RB_WINDOW_OFFSET2                              0x000088d4
2523 #define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE            0x80000000
2524 #define A6XX_RB_WINDOW_OFFSET2_X__MASK                          0x00007fff
2525 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT                         0
2526 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
2527 {
2528         return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
2529 }
2530 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK                          0x7fff0000
2531 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT                         16
2532 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
2533 {
2534         return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
2535 }
2536 
2537 #define REG_A6XX_SP_WINDOW_OFFSET                               0x0000b4d1
2538 #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE             0x80000000
2539 #define A6XX_SP_WINDOW_OFFSET_X__MASK                           0x00007fff
2540 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT                          0
2541 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2542 {
2543         return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2544 }
2545 #define A6XX_SP_WINDOW_OFFSET_Y__MASK                           0x7fff0000
2546 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT                          16
2547 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2548 {
2549         return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2550 }
2551 
2552 #define REG_A6XX_SP_TP_WINDOW_OFFSET                            0x0000b307
2553 #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE          0x80000000
2554 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK                        0x00007fff
2555 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT                       0
2556 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2557 {
2558         return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2559 }
2560 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK                        0x7fff0000
2561 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT                       16
2562 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2563 {
2564         return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2565 }
2566 
2567 #define REG_A6XX_GRAS_BIN_CONTROL                               0x000080a1
2568 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK                        0x000000ff
2569 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT                       0
2570 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2571 {
2572         return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2573 }
2574 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK                        0x0001ff00
2575 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT                       8
2576 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2577 {
2578         return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2579 }
2580 #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS                      0x00040000
2581 #define A6XX_GRAS_BIN_CONTROL_USE_VIZ                           0x00200000
2582 
2583 #define REG_A6XX_RB_BIN_CONTROL2                                0x000088d3
2584 #define A6XX_RB_BIN_CONTROL2_BINW__MASK                         0x000000ff
2585 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT                        0
2586 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
2587 {
2588         return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
2589 }
2590 #define A6XX_RB_BIN_CONTROL2_BINH__MASK                         0x0001ff00
2591 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT                        8
2592 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
2593 {
2594         return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
2595 }
2596 
2597 #define REG_A6XX_VSC_BIN_SIZE                                   0x00000c02
2598 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK                           0x000000ff
2599 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
2600 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2601 {
2602         return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2603 }
2604 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x0001ff00
2605 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         8
2606 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2607 {
2608         return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2609 }
2610 
2611 #define REG_A6XX_VSC_SIZE_ADDRESS_LO                            0x00000c03
2612 
2613 #define REG_A6XX_VSC_SIZE_ADDRESS_HI                            0x00000c04
2614 
2615 #define REG_A6XX_VSC_BIN_COUNT                                  0x00000c06
2616 #define A6XX_VSC_BIN_COUNT_NX__MASK                             0x000007fe
2617 #define A6XX_VSC_BIN_COUNT_NX__SHIFT                            1
2618 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2619 {
2620         return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2621 }
2622 #define A6XX_VSC_BIN_COUNT_NY__MASK                             0x001ff800
2623 #define A6XX_VSC_BIN_COUNT_NY__SHIFT                            11
2624 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2625 {
2626         return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2627 }
2628 
2629 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2630 
2631 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2632 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK                        0x000003ff
2633 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT                       0
2634 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2635 {
2636         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2637 }
2638 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK                        0x000ffc00
2639 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                       10
2640 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2641 {
2642         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2643 }
2644 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK                        0x03f00000
2645 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT                       20
2646 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2647 {
2648         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2649 }
2650 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK                        0xfc000000
2651 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT                       26
2652 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2653 {
2654         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2655 }
2656 
2657 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO                      0x00000c30
2658 
2659 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI                      0x00000c31
2660 
2661 #define REG_A6XX_VSC_PIPE_DATA2_PITCH                           0x00000c32
2662 
2663 #define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH                     0x00000c33
2664 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK                   0xffffffff
2665 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT                  0
2666 static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val)
2667 {
2668         return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK;
2669 }
2670 
2671 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO                       0x00000c34
2672 
2673 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI                       0x00000c35
2674 
2675 #define REG_A6XX_VSC_PIPE_DATA_PITCH                            0x00000c36
2676 
2677 #define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH                      0x00000c37
2678 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK                    0xffffffff
2679 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT                   0
2680 static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val)
2681 {
2682         return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK;
2683 }
2684 
2685 static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2686 
2687 static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2688 
2689 #define REG_A6XX_UCHE_UNKNOWN_0E12                              0x00000e12
2690 
2691 #define REG_A6XX_GRAS_UNKNOWN_8000                              0x00008000
2692 
2693 #define REG_A6XX_GRAS_UNKNOWN_8001                              0x00008001
2694 
2695 #define REG_A6XX_GRAS_UNKNOWN_8004                              0x00008004
2696 
2697 #define REG_A6XX_GRAS_CNTL                                      0x00008005
2698 #define A6XX_GRAS_CNTL_VARYING                                  0x00000001
2699 #define A6XX_GRAS_CNTL_UNK3                                     0x00000008
2700 #define A6XX_GRAS_CNTL_XCOORD                                   0x00000040
2701 #define A6XX_GRAS_CNTL_YCOORD                                   0x00000080
2702 #define A6XX_GRAS_CNTL_ZCOORD                                   0x00000100
2703 #define A6XX_GRAS_CNTL_WCOORD                                   0x00000200
2704 
2705 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ                     0x00008006
2706 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK              0x000003ff
2707 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT             0
2708 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2709 {
2710         return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2711 }
2712 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK              0x000ffc00
2713 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT             10
2714 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2715 {
2716         return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2717 }
2718 
2719 #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0                        0x00008010
2720 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK                      0xffffffff
2721 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT                     0
2722 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2723 {
2724         return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2725 }
2726 
2727 #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0                         0x00008011
2728 #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK                       0xffffffff
2729 #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT                      0
2730 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val)
2731 {
2732         return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2733 }
2734 
2735 #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0                        0x00008012
2736 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK                      0xffffffff
2737 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT                     0
2738 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2739 {
2740         return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2741 }
2742 
2743 #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0                         0x00008013
2744 #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK                       0xffffffff
2745 #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT                      0
2746 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val)
2747 {
2748         return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2749 }
2750 
2751 #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0                        0x00008014
2752 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK                      0xffffffff
2753 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT                     0
2754 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2755 {
2756         return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2757 }
2758 
2759 #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0                         0x00008015
2760 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK                       0xffffffff
2761 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT                      0
2762 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2763 {
2764         return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2765 }
2766 
2767 #define REG_A6XX_GRAS_SU_CNTL                                   0x00008090
2768 #define A6XX_GRAS_SU_CNTL_CULL_FRONT                            0x00000001
2769 #define A6XX_GRAS_SU_CNTL_CULL_BACK                             0x00000002
2770 #define A6XX_GRAS_SU_CNTL_FRONT_CW                              0x00000004
2771 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK                   0x000007f8
2772 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT                  3
2773 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2774 {
2775         return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2776 }
2777 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET                           0x00000800
2778 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE                           0x00002000
2779 
2780 #define REG_A6XX_GRAS_SU_POINT_MINMAX                           0x00008091
2781 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
2782 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
2783 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2784 {
2785         return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2786 }
2787 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
2788 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
2789 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2790 {
2791         return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2792 }
2793 
2794 #define REG_A6XX_GRAS_SU_POINT_SIZE                             0x00008092
2795 #define A6XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
2796 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT                          0
2797 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2798 {
2799         return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2800 }
2801 
2802 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL                       0x00008094
2803 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z             0x00000001
2804 
2805 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE                      0x00008095
2806 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK                    0xffffffff
2807 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT                   0
2808 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2809 {
2810         return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2811 }
2812 
2813 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x00008096
2814 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
2815 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
2816 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2817 {
2818         return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2819 }
2820 
2821 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP               0x00008097
2822 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK             0xffffffff
2823 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT            0
2824 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2825 {
2826         return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2827 }
2828 
2829 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO                      0x00008098
2830 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK       0x00000007
2831 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT      0
2832 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2833 {
2834         return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2835 }
2836 
2837 #define REG_A6XX_GRAS_UNKNOWN_8099                              0x00008099
2838 
2839 #define REG_A6XX_GRAS_UNKNOWN_809B                              0x0000809b
2840 
2841 #define REG_A6XX_GRAS_UNKNOWN_80A0                              0x000080a0
2842 
2843 #define REG_A6XX_GRAS_RAS_MSAA_CNTL                             0x000080a2
2844 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK                   0x00000003
2845 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT                  0
2846 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2847 {
2848         return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2849 }
2850 
2851 #define REG_A6XX_GRAS_DEST_MSAA_CNTL                            0x000080a3
2852 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK                  0x00000003
2853 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT                 0
2854 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2855 {
2856         return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2857 }
2858 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE                   0x00000004
2859 
2860 #define REG_A6XX_GRAS_UNKNOWN_80A4                              0x000080a4
2861 
2862 #define REG_A6XX_GRAS_UNKNOWN_80A5                              0x000080a5
2863 
2864 #define REG_A6XX_GRAS_UNKNOWN_80A6                              0x000080a6
2865 
2866 #define REG_A6XX_GRAS_UNKNOWN_80AF                              0x000080af
2867 
2868 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0                    0x000080b0
2869 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE  0x80000000
2870 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK                0x00007fff
2871 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT               0
2872 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2873 {
2874         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2875 }
2876 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK                0x7fff0000
2877 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT               16
2878 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2879 {
2880         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2881 }
2882 
2883 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0                    0x000080b1
2884 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE  0x80000000
2885 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK                0x00007fff
2886 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT               0
2887 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2888 {
2889         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2890 }
2891 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK                0x7fff0000
2892 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT               16
2893 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2894 {
2895         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2896 }
2897 
2898 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0                  0x000080d0
2899 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE        0x80000000
2900 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK              0x00007fff
2901 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT             0
2902 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2903 {
2904         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2905 }
2906 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK              0x7fff0000
2907 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT             16
2908 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2909 {
2910         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2911 }
2912 
2913 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0                  0x000080d1
2914 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE        0x80000000
2915 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK              0x00007fff
2916 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT             0
2917 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2918 {
2919         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2920 }
2921 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK              0x7fff0000
2922 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT             16
2923 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2924 {
2925         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2926 }
2927 
2928 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x000080f0
2929 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
2930 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
2931 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
2932 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2933 {
2934         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2935 }
2936 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
2937 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
2938 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2939 {
2940         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2941 }
2942 
2943 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x000080f1
2944 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
2945 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
2946 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
2947 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2948 {
2949         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2950 }
2951 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
2952 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
2953 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2954 {
2955         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2956 }
2957 
2958 #define REG_A6XX_GRAS_LRZ_CNTL                                  0x00008100
2959 #define A6XX_GRAS_LRZ_CNTL_ENABLE                               0x00000001
2960 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE                            0x00000002
2961 #define A6XX_GRAS_LRZ_CNTL_GREATER                              0x00000004
2962 #define A6XX_GRAS_LRZ_CNTL_UNK3                                 0x00000008
2963 #define A6XX_GRAS_LRZ_CNTL_UNK4                                 0x00000010
2964 
2965 #define REG_A6XX_GRAS_UNKNOWN_8101                              0x00008101
2966 
2967 #define REG_A6XX_GRAS_2D_BLIT_INFO                              0x00008102
2968 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK               0x000000ff
2969 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT              0
2970 static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
2971 {
2972         return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2973 }
2974 
2975 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO                        0x00008103
2976 
2977 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI                        0x00008104
2978 
2979 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH                          0x00008105
2980 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK                  0x000007ff
2981 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT                 0
2982 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2983 {
2984         return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
2985 }
2986 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK            0x003ff800
2987 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT           11
2988 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2989 {
2990         return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2991 }
2992 
2993 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO             0x00008106
2994 
2995 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI             0x00008107
2996 
2997 #define REG_A6XX_GRAS_UNKNOWN_8109                              0x00008109
2998 
2999 #define REG_A6XX_GRAS_UNKNOWN_8110                              0x00008110
3000 
3001 #define REG_A6XX_GRAS_2D_BLIT_CNTL                              0x00008400
3002 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK               0x0000ff00
3003 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT              8
3004 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3005 {
3006         return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3007 }
3008 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR                          0x00010000
3009 
3010 #define REG_A6XX_GRAS_2D_SRC_TL_X                               0x00008401
3011 #define A6XX_GRAS_2D_SRC_TL_X_X__MASK                           0x00ffff00
3012 #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT                          8
3013 static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val)
3014 {
3015         return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
3016 }
3017 
3018 #define REG_A6XX_GRAS_2D_SRC_BR_X                               0x00008402
3019 #define A6XX_GRAS_2D_SRC_BR_X_X__MASK                           0x00ffff00
3020 #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT                          8
3021 static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val)
3022 {
3023         return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
3024 }
3025 
3026 #define REG_A6XX_GRAS_2D_SRC_TL_Y                               0x00008403
3027 #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK                           0x00ffff00
3028 #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT                          8
3029 static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val)
3030 {
3031         return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
3032 }
3033 
3034 #define REG_A6XX_GRAS_2D_SRC_BR_Y                               0x00008404
3035 #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK                           0x00ffff00
3036 #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT                          8
3037 static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val)
3038 {
3039         return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
3040 }
3041 
3042 #define REG_A6XX_GRAS_2D_DST_TL                                 0x00008405
3043 #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE               0x80000000
3044 #define A6XX_GRAS_2D_DST_TL_X__MASK                             0x00007fff
3045 #define A6XX_GRAS_2D_DST_TL_X__SHIFT                            0
3046 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
3047 {
3048         return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
3049 }
3050 #define A6XX_GRAS_2D_DST_TL_Y__MASK                             0x7fff0000
3051 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT                            16
3052 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
3053 {
3054         return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
3055 }
3056 
3057 #define REG_A6XX_GRAS_2D_DST_BR                                 0x00008406
3058 #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE               0x80000000
3059 #define A6XX_GRAS_2D_DST_BR_X__MASK                             0x00007fff
3060 #define A6XX_GRAS_2D_DST_BR_X__SHIFT                            0
3061 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
3062 {
3063         return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
3064 }
3065 #define A6XX_GRAS_2D_DST_BR_Y__MASK                             0x7fff0000
3066 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT                            16
3067 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
3068 {
3069         return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
3070 }
3071 
3072 #define REG_A6XX_GRAS_RESOLVE_CNTL_1                            0x0000840a
3073 #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE          0x80000000
3074 #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK                        0x00007fff
3075 #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT                       0
3076 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val)
3077 {
3078         return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK;
3079 }
3080 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK                        0x7fff0000
3081 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT                       16
3082 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val)
3083 {
3084         return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK;
3085 }
3086 
3087 #define REG_A6XX_GRAS_RESOLVE_CNTL_2                            0x0000840b
3088 #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE          0x80000000
3089 #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK                        0x00007fff
3090 #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT                       0
3091 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val)
3092 {
3093         return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK;
3094 }
3095 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK                        0x7fff0000
3096 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT                       16
3097 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
3098 {
3099         return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK;
3100 }
3101 
3102 #define REG_A6XX_GRAS_UNKNOWN_8600                              0x00008600
3103 
3104 #define REG_A6XX_RB_BIN_CONTROL                                 0x00008800
3105 #define A6XX_RB_BIN_CONTROL_BINW__MASK                          0x000000ff
3106 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT                         0
3107 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3108 {
3109         return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3110 }
3111 #define A6XX_RB_BIN_CONTROL_BINH__MASK                          0x0001ff00
3112 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT                         8
3113 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
3114 {
3115         return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
3116 }
3117 #define A6XX_RB_BIN_CONTROL_BINNING_PASS                        0x00040000
3118 #define A6XX_RB_BIN_CONTROL_USE_VIZ                             0x00200000
3119 
3120 #define REG_A6XX_RB_RENDER_CNTL                                 0x00008801
3121 #define A6XX_RB_RENDER_CNTL_UNK4                                0x00000010
3122 #define A6XX_RB_RENDER_CNTL_BINNING                             0x00000080
3123 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH                          0x00004000
3124 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK                     0x00ff0000
3125 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT                    16
3126 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3127 {
3128         return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3129 }
3130 
3131 #define REG_A6XX_RB_RAS_MSAA_CNTL                               0x00008802
3132 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK                     0x00000003
3133 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT                    0
3134 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3135 {
3136         return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3137 }
3138 
3139 #define REG_A6XX_RB_DEST_MSAA_CNTL                              0x00008803
3140 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK                    0x00000003
3141 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT                   0
3142 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3143 {
3144         return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3145 }
3146 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE                     0x00000004
3147 
3148 #define REG_A6XX_RB_UNKNOWN_8804                                0x00008804
3149 
3150 #define REG_A6XX_RB_UNKNOWN_8805                                0x00008805
3151 
3152 #define REG_A6XX_RB_UNKNOWN_8806                                0x00008806
3153 
3154 #define REG_A6XX_RB_RENDER_CONTROL0                             0x00008809
3155 #define A6XX_RB_RENDER_CONTROL0_VARYING                         0x00000001
3156 #define A6XX_RB_RENDER_CONTROL0_UNK3                            0x00000008
3157 #define A6XX_RB_RENDER_CONTROL0_XCOORD                          0x00000040
3158 #define A6XX_RB_RENDER_CONTROL0_YCOORD                          0x00000080
3159 #define A6XX_RB_RENDER_CONTROL0_ZCOORD                          0x00000100
3160 #define A6XX_RB_RENDER_CONTROL0_WCOORD                          0x00000200
3161 #define A6XX_RB_RENDER_CONTROL0_UNK10                           0x00000400
3162 
3163 #define REG_A6XX_RB_RENDER_CONTROL1                             0x0000880a
3164 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK                      0x00000001
3165 #define A6XX_RB_RENDER_CONTROL1_FACENESS                        0x00000002
3166 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID                        0x00000008
3167 
3168 #define REG_A6XX_RB_FS_OUTPUT_CNTL0                             0x0000880b
3169 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z                   0x00000002
3170 
3171 #define REG_A6XX_RB_FS_OUTPUT_CNTL1                             0x0000880c
3172 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK                       0x0000000f
3173 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT                      0
3174 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3175 {
3176         return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3177 }
3178 
3179 #define REG_A6XX_RB_RENDER_COMPONENTS                           0x0000880d
3180 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK                     0x0000000f
3181 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT                    0
3182 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3183 {
3184         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3185 }
3186 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK                     0x000000f0
3187 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT                    4
3188 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3189 {
3190         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3191 }
3192 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK                     0x00000f00
3193 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT                    8
3194 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3195 {
3196         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3197 }
3198 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK                     0x0000f000
3199 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT                    12
3200 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3201 {
3202         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3203 }
3204 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK                     0x000f0000
3205 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT                    16
3206 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3207 {
3208         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3209 }
3210 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK                     0x00f00000
3211 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT                    20
3212 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3213 {
3214         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3215 }
3216 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK                     0x0f000000
3217 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT                    24
3218 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3219 {
3220         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3221 }
3222 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK                     0xf0000000
3223 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT                    28
3224 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3225 {
3226         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3227 }
3228 
3229 #define REG_A6XX_RB_DITHER_CNTL                                 0x0000880e
3230 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK              0x00000003
3231 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT             0
3232 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3233 {
3234         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3235 }
3236 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK              0x0000000c
3237 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT             2
3238 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3239 {
3240         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3241 }
3242 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK              0x00000030
3243 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT             4
3244 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3245 {
3246         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3247 }
3248 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK              0x000000c0
3249 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT             6
3250 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3251 {
3252         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3253 }
3254 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK              0x00000300
3255 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT             8
3256 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3257 {
3258         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3259 }
3260 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK              0x00000c00
3261 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT             10
3262 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3263 {
3264         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3265 }
3266 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK              0x00001000
3267 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT             12
3268 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3269 {
3270         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3271 }
3272 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK              0x0000c000
3273 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT             14
3274 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3275 {
3276         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3277 }
3278 
3279 #define REG_A6XX_RB_SRGB_CNTL                                   0x0000880f
3280 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0                             0x00000001
3281 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1                             0x00000002
3282 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2                             0x00000004
3283 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3                             0x00000008
3284 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4                             0x00000010
3285 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5                             0x00000020
3286 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6                             0x00000040
3287 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7                             0x00000080
3288 
3289 #define REG_A6XX_RB_UNKNOWN_8810                                0x00008810
3290 
3291 #define REG_A6XX_RB_UNKNOWN_8811                                0x00008811
3292 
3293 #define REG_A6XX_RB_UNKNOWN_8818                                0x00008818
3294 
3295 #define REG_A6XX_RB_UNKNOWN_8819                                0x00008819
3296 
3297 #define REG_A6XX_RB_UNKNOWN_881A                                0x0000881a
3298 
3299 #define REG_A6XX_RB_UNKNOWN_881B                                0x0000881b
3300 
3301 #define REG_A6XX_RB_UNKNOWN_881C                                0x0000881c
3302 
3303 #define REG_A6XX_RB_UNKNOWN_881D                                0x0000881d
3304 
3305 #define REG_A6XX_RB_UNKNOWN_881E                                0x0000881e
3306 
3307 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3308 
3309 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3310 #define A6XX_RB_MRT_CONTROL_BLEND                               0x00000001
3311 #define A6XX_RB_MRT_CONTROL_BLEND2                              0x00000002
3312 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE                          0x00000004
3313 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000078
3314 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     3
3315 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3316 {
3317         return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3318 }
3319 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x00000780
3320 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             7
3321 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3322 {
3323         return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3324 }
3325 
3326 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3327 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
3328 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
3329 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3330 {
3331         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3332 }
3333 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
3334 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
3335 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3336 {
3337         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3338 }
3339 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
3340 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
3341 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3342 {
3343         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3344 }
3345 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
3346 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
3347 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3348 {
3349         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3350 }
3351 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
3352 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
3353 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3354 {
3355         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3356 }
3357 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
3358 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
3359 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3360 {
3361         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3362 }
3363 
3364 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3365 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x000000ff
3366 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
3367 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3368 {
3369         return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3370 }
3371 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x00000300
3372 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             8
3373 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3374 {
3375         return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3376 }
3377 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00006000
3378 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  13
3379 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3380 {
3381         return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3382 }
3383 
3384 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3385 #define A6XX_RB_MRT_PITCH__MASK                                 0xffffffff
3386 #define A6XX_RB_MRT_PITCH__SHIFT                                0
3387 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3388 {
3389         return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3390 }
3391 
3392 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3393 #define A6XX_RB_MRT_ARRAY_PITCH__MASK                           0xffffffff
3394 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT                          0
3395 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3396 {
3397         return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3398 }
3399 
3400 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3401 
3402 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3403 
3404 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3405 
3406 #define REG_A6XX_RB_BLEND_RED_F32                               0x00008860
3407 #define A6XX_RB_BLEND_RED_F32__MASK                             0xffffffff
3408 #define A6XX_RB_BLEND_RED_F32__SHIFT                            0
3409 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3410 {
3411         return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3412 }
3413 
3414 #define REG_A6XX_RB_BLEND_GREEN_F32                             0x00008861
3415 #define A6XX_RB_BLEND_GREEN_F32__MASK                           0xffffffff
3416 #define A6XX_RB_BLEND_GREEN_F32__SHIFT                          0
3417 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3418 {
3419         return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3420 }
3421 
3422 #define REG_A6XX_RB_BLEND_BLUE_F32                              0x00008862
3423 #define A6XX_RB_BLEND_BLUE_F32__MASK                            0xffffffff
3424 #define A6XX_RB_BLEND_BLUE_F32__SHIFT                           0
3425 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3426 {
3427         return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3428 }
3429 
3430 #define REG_A6XX_RB_BLEND_ALPHA_F32                             0x00008863
3431 #define A6XX_RB_BLEND_ALPHA_F32__MASK                           0xffffffff
3432 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT                          0
3433 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3434 {
3435         return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3436 }
3437 
3438 #define REG_A6XX_RB_ALPHA_CONTROL                               0x00008864
3439 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK                   0x000000ff
3440 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT                  0
3441 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3442 {
3443         return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3444 }
3445 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST                        0x00000100
3446 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK             0x00000e00
3447 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT            9
3448 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3449 {
3450         return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3451 }
3452 
3453 #define REG_A6XX_RB_BLEND_CNTL                                  0x00008865
3454 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK                   0x000000ff
3455 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT                  0
3456 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3457 {
3458         return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3459 }
3460 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND                    0x00000100
3461 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE                    0x00000400
3462 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK                    0xffff0000
3463 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT                   16
3464 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3465 {
3466         return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3467 }
3468 
3469 #define REG_A6XX_RB_DEPTH_PLANE_CNTL                            0x00008870
3470 #define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z                  0x00000001
3471 
3472 #define REG_A6XX_RB_DEPTH_CNTL                                  0x00008871
3473 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE                             0x00000001
3474 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE                       0x00000002
3475 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK                          0x0000001c
3476 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT                         2
3477 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3478 {
3479         return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3480 }
3481 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE                        0x00000040
3482 
3483 #define REG_A6XX_RB_DEPTH_BUFFER_INFO                           0x00008872
3484 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK            0x00000007
3485 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT           0
3486 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3487 {
3488         return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3489 }
3490 
3491 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH                          0x00008873
3492 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK                        0xffffffff
3493 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT                       0
3494 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3495 {
3496         return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3497 }
3498 
3499 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH                    0x00008874
3500 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK                  0xffffffff
3501 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT                 0
3502 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3503 {
3504         return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3505 }
3506 
3507 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO                        0x00008875
3508 
3509 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI                        0x00008876
3510 
3511 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM                      0x00008877
3512 
3513 #define REG_A6XX_RB_UNKNOWN_8878                                0x00008878
3514 
3515 #define REG_A6XX_RB_UNKNOWN_8879                                0x00008879
3516 
3517 #define REG_A6XX_RB_STENCIL_CONTROL                             0x00008880
3518 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
3519 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
3520 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
3521 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
3522 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
3523 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3524 {
3525         return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3526 }
3527 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
3528 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
3529 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3530 {
3531         return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3532 }
3533 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
3534 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
3535 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3536 {
3537         return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3538 }
3539 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
3540 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
3541 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3542 {
3543         return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3544 }
3545 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
3546 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
3547 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3548 {
3549         return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3550 }
3551 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
3552 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
3553 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3554 {
3555         return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3556 }
3557 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
3558 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
3559 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3560 {
3561         return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3562 }
3563 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
3564 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
3565 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3566 {
3567         return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3568 }
3569 
3570 #define REG_A6XX_RB_STENCIL_INFO                                0x00008881
3571 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL                   0x00000001
3572 
3573 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH                        0x00008882
3574 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK                      0xffffffff
3575 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT                     0
3576 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3577 {
3578         return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3579 }
3580 
3581 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH                  0x00008883
3582 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK                0xffffffff
3583 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT               0
3584 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3585 {
3586         return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3587 }
3588 
3589 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO                      0x00008884
3590 
3591 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI                      0x00008885
3592 
3593 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM                    0x00008886
3594 
3595 #define REG_A6XX_RB_STENCILREF                                  0x00008887
3596 #define A6XX_RB_STENCILREF_REF__MASK                            0x000000ff
3597 #define A6XX_RB_STENCILREF_REF__SHIFT                           0
3598 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3599 {
3600         return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3601 }
3602 #define A6XX_RB_STENCILREF_BFREF__MASK                          0x0000ff00
3603 #define A6XX_RB_STENCILREF_BFREF__SHIFT                         8
3604 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3605 {
3606         return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3607 }
3608 
3609 #define REG_A6XX_RB_STENCILMASK                                 0x00008888
3610 #define A6XX_RB_STENCILMASK_MASK__MASK                          0x000000ff
3611 #define A6XX_RB_STENCILMASK_MASK__SHIFT                         0
3612 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3613 {
3614         return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3615 }
3616 #define A6XX_RB_STENCILMASK_BFMASK__MASK                        0x0000ff00
3617 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT                       8
3618 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3619 {
3620         return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3621 }
3622 
3623 #define REG_A6XX_RB_STENCILWRMASK                               0x00008889
3624 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK                      0x000000ff
3625 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT                     0
3626 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3627 {
3628         return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3629 }
3630 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK                    0x0000ff00
3631 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT                   8
3632 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3633 {
3634         return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3635 }
3636 
3637 #define REG_A6XX_RB_WINDOW_OFFSET                               0x00008890
3638 #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE             0x80000000
3639 #define A6XX_RB_WINDOW_OFFSET_X__MASK                           0x00007fff
3640 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT                          0
3641 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3642 {
3643         return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3644 }
3645 #define A6XX_RB_WINDOW_OFFSET_Y__MASK                           0x7fff0000
3646 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT                          16
3647 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3648 {
3649         return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3650 }
3651 
3652 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL                        0x00008891
3653 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY                       0x00000002
3654 
3655 #define REG_A6XX_RB_LRZ_CNTL                                    0x00008898
3656 #define A6XX_RB_LRZ_CNTL_ENABLE                                 0x00000001
3657 
3658 #define REG_A6XX_RB_UNKNOWN_88D0                                0x000088d0
3659 
3660 #define REG_A6XX_RB_BLIT_SCISSOR_TL                             0x000088d1
3661 #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE           0x80000000
3662 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK                         0x00007fff
3663 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT                        0
3664 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3665 {
3666         return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3667 }
3668 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK                         0x7fff0000
3669 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT                        16
3670 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3671 {
3672         return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3673 }
3674 
3675 #define REG_A6XX_RB_BLIT_SCISSOR_BR                             0x000088d2
3676 #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE           0x80000000
3677 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK                         0x00007fff
3678 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT                        0
3679 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3680 {
3681         return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3682 }
3683 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK                         0x7fff0000
3684 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT                        16
3685 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3686 {
3687         return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3688 }
3689 
3690 #define REG_A6XX_RB_MSAA_CNTL                                   0x000088d5
3691 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK                         0x00000018
3692 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT                        3
3693 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3694 {
3695         return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
3696 }
3697 
3698 #define REG_A6XX_RB_BLIT_BASE_GMEM                              0x000088d6
3699 
3700 #define REG_A6XX_RB_BLIT_DST_INFO                               0x000088d7
3701 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK                   0x00000003
3702 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT                  0
3703 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3704 {
3705         return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3706 }
3707 #define A6XX_RB_BLIT_DST_INFO_FLAGS                             0x00000004
3708 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK                     0x00000018
3709 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT                    3
3710 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3711 {
3712         return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
3713 }
3714 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK                0x00007f80
3715 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT               7
3716 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3717 {
3718         return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3719 }
3720 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK                  0x00000060
3721 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT                 5
3722 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3723 {
3724         return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3725 }
3726 
3727 #define REG_A6XX_RB_BLIT_DST_LO                                 0x000088d8
3728 
3729 #define REG_A6XX_RB_BLIT_DST_HI                                 0x000088d9
3730 
3731 #define REG_A6XX_RB_BLIT_DST_PITCH                              0x000088da
3732 #define A6XX_RB_BLIT_DST_PITCH__MASK                            0xffffffff
3733 #define A6XX_RB_BLIT_DST_PITCH__SHIFT                           0
3734 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3735 {
3736         return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3737 }
3738 
3739 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH                        0x000088db
3740 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK                      0xffffffff
3741 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT                     0
3742 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3743 {
3744         return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3745 }
3746 
3747 #define REG_A6XX_RB_BLIT_FLAG_DST_LO                            0x000088dc
3748 
3749 #define REG_A6XX_RB_BLIT_FLAG_DST_HI                            0x000088dd
3750 
3751 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0                        0x000088df
3752 
3753 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1                        0x000088e0
3754 
3755 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2                        0x000088e1
3756 
3757 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3                        0x000088e2
3758 
3759 #define REG_A6XX_RB_BLIT_INFO                                   0x000088e3
3760 #define A6XX_RB_BLIT_INFO_UNK0                                  0x00000001
3761 #define A6XX_RB_BLIT_INFO_GMEM                                  0x00000002
3762 #define A6XX_RB_BLIT_INFO_INTEGER                               0x00000004
3763 #define A6XX_RB_BLIT_INFO_DEPTH                                 0x00000008
3764 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK                      0x000000f0
3765 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT                     4
3766 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3767 {
3768         return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3769 }
3770 
3771 #define REG_A6XX_RB_UNKNOWN_88F0                                0x000088f0
3772 
3773 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO                   0x00008900
3774 
3775 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI                   0x00008901
3776 
3777 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH                     0x00008902
3778 
3779 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3780 
3781 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3782 
3783 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
3784 
3785 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3786 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK               0x000007ff
3787 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT              0
3788 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3789 {
3790         return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3791 }
3792 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK         0x003ff800
3793 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT        11
3794 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3795 {
3796         return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3797 }
3798 
3799 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO                        0x00008927
3800 
3801 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI                        0x00008928
3802 
3803 #define REG_A6XX_RB_2D_BLIT_CNTL                                0x00008c00
3804 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK                 0x0000ff00
3805 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT                8
3806 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3807 {
3808         return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3809 }
3810 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR                            0x00010000
3811 
3812 #define REG_A6XX_RB_UNKNOWN_8C01                                0x00008c01
3813 
3814 #define REG_A6XX_RB_2D_DST_INFO                                 0x00008c17
3815 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK                  0x000000ff
3816 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT                 0
3817 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3818 {
3819         return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3820 }
3821 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK                     0x00000300
3822 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT                    8
3823 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3824 {
3825         return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
3826 }
3827 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK                    0x00000c00
3828 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT                   10
3829 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3830 {
3831         return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3832 }
3833 #define A6XX_RB_2D_DST_INFO_FLAGS                               0x00001000
3834 
3835 #define REG_A6XX_RB_2D_DST_LO                                   0x00008c18
3836 
3837 #define REG_A6XX_RB_2D_DST_HI                                   0x00008c19
3838 
3839 #define REG_A6XX_RB_2D_DST_SIZE                                 0x00008c1a
3840 #define A6XX_RB_2D_DST_SIZE_PITCH__MASK                         0x0000ffff
3841 #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT                        0
3842 static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
3843 {
3844         return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK;
3845 }
3846 
3847 #define REG_A6XX_RB_2D_DST_FLAGS_LO                             0x00008c20
3848 
3849 #define REG_A6XX_RB_2D_DST_FLAGS_HI                             0x00008c21
3850 
3851 #define REG_A6XX_RB_2D_SRC_SOLID_C0                             0x00008c2c
3852 
3853 #define REG_A6XX_RB_2D_SRC_SOLID_C1                             0x00008c2d
3854 
3855 #define REG_A6XX_RB_2D_SRC_SOLID_C2                             0x00008c2e
3856 
3857 #define REG_A6XX_RB_2D_SRC_SOLID_C3                             0x00008c2f
3858 
3859 #define REG_A6XX_RB_UNKNOWN_8E01                                0x00008e01
3860 
3861 #define REG_A6XX_RB_UNKNOWN_8E04                                0x00008e04
3862 
3863 #define REG_A6XX_RB_CCU_CNTL                                    0x00008e07
3864 
3865 #define REG_A6XX_VPC_UNKNOWN_9101                               0x00009101
3866 
3867 #define REG_A6XX_VPC_GS_SIV_CNTL                                0x00009104
3868 
3869 #define REG_A6XX_VPC_UNKNOWN_9107                               0x00009107
3870 
3871 #define REG_A6XX_VPC_UNKNOWN_9108                               0x00009108
3872 
3873 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3874 
3875 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3876 
3877 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3878 
3879 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3880 
3881 #define REG_A6XX_VPC_UNKNOWN_9210                               0x00009210
3882 
3883 #define REG_A6XX_VPC_UNKNOWN_9211                               0x00009211
3884 
3885 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
3886 
3887 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
3888 
3889 #define REG_A6XX_VPC_SO_CNTL                                    0x00009216
3890 #define A6XX_VPC_SO_CNTL_ENABLE                                 0x00010000
3891 
3892 #define REG_A6XX_VPC_SO_PROG                                    0x00009217
3893 #define A6XX_VPC_SO_PROG_A_BUF__MASK                            0x00000003
3894 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT                           0
3895 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
3896 {
3897         return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
3898 }
3899 #define A6XX_VPC_SO_PROG_A_OFF__MASK                            0x000007fc
3900 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT                           2
3901 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
3902 {
3903         return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
3904 }
3905 #define A6XX_VPC_SO_PROG_A_EN                                   0x00000800
3906 #define A6XX_VPC_SO_PROG_B_BUF__MASK                            0x00003000
3907 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT                           12
3908 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
3909 {
3910         return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
3911 }
3912 #define A6XX_VPC_SO_PROG_B_OFF__MASK                            0x007fc000
3913 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT                           14
3914 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
3915 {
3916         return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
3917 }
3918 #define A6XX_VPC_SO_PROG_B_EN                                   0x00800000
3919 
3920 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
3921 
3922 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
3923 
3924 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
3925 
3926 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
3927 
3928 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
3929 
3930 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
3931 
3932 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
3933 
3934 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
3935 
3936 #define REG_A6XX_VPC_UNKNOWN_9236                               0x00009236
3937 
3938 #define REG_A6XX_VPC_UNKNOWN_9300                               0x00009300
3939 
3940 #define REG_A6XX_VPC_PACK                                       0x00009301
3941 #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK                       0x000000ff
3942 #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT                      0
3943 static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
3944 {
3945         return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
3946 }
3947 #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK                        0x0000ff00
3948 #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT                       8
3949 static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3950 {
3951         return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
3952 }
3953 #define A6XX_VPC_PACK_PSIZELOC__MASK                            0x00ff0000
3954 #define A6XX_VPC_PACK_PSIZELOC__SHIFT                           16
3955 static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
3956 {
3957         return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
3958 }
3959 
3960 #define REG_A6XX_VPC_CNTL_0                                     0x00009304
3961 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK                      0x000000ff
3962 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT                     0
3963 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
3964 {
3965         return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
3966 }
3967 #define A6XX_VPC_CNTL_0_VARYING                                 0x00010000
3968 
3969 #define REG_A6XX_VPC_SO_BUF_CNTL                                0x00009305
3970 #define A6XX_VPC_SO_BUF_CNTL_BUF0                               0x00000001
3971 #define A6XX_VPC_SO_BUF_CNTL_BUF1                               0x00000008
3972 #define A6XX_VPC_SO_BUF_CNTL_BUF2                               0x00000040
3973 #define A6XX_VPC_SO_BUF_CNTL_BUF3                               0x00000200
3974 #define A6XX_VPC_SO_BUF_CNTL_ENABLE                             0x00008000
3975 
3976 #define REG_A6XX_VPC_SO_OVERRIDE                                0x00009306
3977 #define A6XX_VPC_SO_OVERRIDE_SO_DISABLE                         0x00000001
3978 
3979 #define REG_A6XX_VPC_UNKNOWN_9600                               0x00009600
3980 
3981 #define REG_A6XX_VPC_UNKNOWN_9602                               0x00009602
3982 
3983 #define REG_A6XX_PC_UNKNOWN_9801                                0x00009801
3984 
3985 #define REG_A6XX_PC_RESTART_INDEX                               0x00009803
3986 
3987 #define REG_A6XX_PC_MODE_CNTL                                   0x00009804
3988 
3989 #define REG_A6XX_PC_UNKNOWN_9805                                0x00009805
3990 
3991 #define REG_A6XX_PC_UNKNOWN_9806                                0x00009806
3992 
3993 #define REG_A6XX_PC_UNKNOWN_9980                                0x00009980
3994 
3995 #define REG_A6XX_PC_UNKNOWN_9981                                0x00009981
3996 
3997 #define REG_A6XX_PC_UNKNOWN_9990                                0x00009990
3998 
3999 #define REG_A6XX_PC_PRIMITIVE_CNTL_0                            0x00009b00
4000 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART              0x00000001
4001 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST             0x00000002
4002 
4003 #define REG_A6XX_PC_PRIMITIVE_CNTL_1                            0x00009b01
4004 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK            0x0000007f
4005 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT           0
4006 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
4007 {
4008         return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
4009 }
4010 #define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE                          0x00000100
4011 
4012 #define REG_A6XX_PC_UNKNOWN_9B06                                0x00009b06
4013 
4014 #define REG_A6XX_PC_UNKNOWN_9B07                                0x00009b07
4015 
4016 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO                          0x00009e08
4017 
4018 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI                          0x00009e09
4019 
4020 #define REG_A6XX_PC_UNKNOWN_9E72                                0x00009e72
4021 
4022 #define REG_A6XX_VFD_CONTROL_0                                  0x0000a000
4023 #define A6XX_VFD_CONTROL_0_VTXCNT__MASK                         0x0000003f
4024 #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT                        0
4025 static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
4026 {
4027         return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
4028 }
4029 
4030 #define REG_A6XX_VFD_CONTROL_1                                  0x0000a001
4031 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x000000ff
4032 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     0
4033 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4034 {
4035         return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
4036 }
4037 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK                     0x0000ff00
4038 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT                    8
4039 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4040 {
4041         return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4042 }
4043 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK                   0x00ff0000
4044 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT                  16
4045 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4046 {
4047         return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4048 }
4049 
4050 #define REG_A6XX_VFD_CONTROL_2                                  0x0000a002
4051 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK                  0x000000ff
4052 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT                 0
4053 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
4054 {
4055         return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
4056 }
4057 
4058 #define REG_A6XX_VFD_CONTROL_3                                  0x0000a003
4059 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK                  0x0000ff00
4060 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT                 8
4061 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
4062 {
4063         return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
4064 }
4065 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK                    0x00ff0000
4066 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT                   16
4067 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4068 {
4069         return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4070 }
4071 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK                    0xff000000
4072 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT                   24
4073 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4074 {
4075         return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4076 }
4077 
4078 #define REG_A6XX_VFD_CONTROL_4                                  0x0000a004
4079 
4080 #define REG_A6XX_VFD_CONTROL_5                                  0x0000a005
4081 
4082 #define REG_A6XX_VFD_CONTROL_6                                  0x0000a006
4083 
4084 #define REG_A6XX_VFD_MODE_CNTL                                  0x0000a007
4085 #define A6XX_VFD_MODE_CNTL_BINNING_PASS                         0x00000001
4086 
4087 #define REG_A6XX_VFD_UNKNOWN_A008                               0x0000a008
4088 
4089 #define REG_A6XX_VFD_UNKNOWN_A009                               0x0000a009
4090 
4091 #define REG_A6XX_VFD_INDEX_OFFSET                               0x0000a00e
4092 
4093 #define REG_A6XX_VFD_INSTANCE_START_OFFSET                      0x0000a00f
4094 
4095 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4096 
4097 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4098 
4099 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
4100 
4101 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
4102 
4103 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
4104 
4105 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4106 
4107 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4108 #define A6XX_VFD_DECODE_INSTR_IDX__MASK                         0x0000001f
4109 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT                        0
4110 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4111 {
4112         return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
4113 }
4114 #define A6XX_VFD_DECODE_INSTR_INSTANCED                         0x00020000
4115 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x0ff00000
4116 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     20
4117 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
4118 {
4119         return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
4120 }
4121 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK                        0x30000000
4122 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT                       28
4123 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4124 {
4125         return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
4126 }
4127 #define A6XX_VFD_DECODE_INSTR_UNK30                             0x40000000
4128 #define A6XX_VFD_DECODE_INSTR_FLOAT                             0x80000000
4129 
4130 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
4131 
4132 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4133 
4134 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4135 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK                0x0000000f
4136 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT               0
4137 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4138 {
4139         return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4140 }
4141 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK                    0x00000ff0
4142 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT                   4
4143 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4144 {
4145         return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4146 }
4147 
4148 #define REG_A6XX_SP_UNKNOWN_A0F8                                0x0000a0f8
4149 
4150 #define REG_A6XX_SP_PRIMITIVE_CNTL                              0x0000a802
4151 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK                      0x0000001f
4152 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT                     0
4153 static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4154 {
4155         return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4156 }
4157 
4158 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4159 
4160 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4161 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000000ff
4162 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
4163 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4164 {
4165         return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
4166 }
4167 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00000f00
4168 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    8
4169 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4170 {
4171         return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4172 }
4173 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK                        0x00ff0000
4174 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
4175 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4176 {
4177         return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
4178 }
4179 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x0f000000
4180 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    24
4181 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4182 {
4183         return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4184 }
4185 
4186 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4187 
4188 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4189 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
4190 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
4191 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4192 {
4193         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4194 }
4195 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
4196 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
4197 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4198 {
4199         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4200 }
4201 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
4202 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
4203 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4204 {
4205         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4206 }
4207 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
4208 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
4209 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4210 {
4211         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4212 }
4213 
4214 #define REG_A6XX_SP_VS_CTRL_REG0                                0x0000a800
4215 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4216 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4217 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4218 {
4219         return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4220 }
4221 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4222 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4223 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4224 {
4225         return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4226 }
4227 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4228 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4229 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4230 {
4231         return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4232 }
4233 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4234 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
4235 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4236 {
4237         return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4238 }
4239 #define A6XX_SP_VS_CTRL_REG0_VARYING                            0x00400000
4240 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x04000000
4241 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS                         0x80000000
4242 
4243 #define REG_A6XX_SP_UNKNOWN_A81B                                0x0000a81b
4244 
4245 #define REG_A6XX_SP_VS_OBJ_START_LO                             0x0000a81c
4246 
4247 #define REG_A6XX_SP_VS_OBJ_START_HI                             0x0000a81d
4248 
4249 #define REG_A6XX_SP_VS_TEX_COUNT                                0x0000a822
4250 
4251 #define REG_A6XX_SP_VS_CONFIG                                   0x0000a823
4252 #define A6XX_SP_VS_CONFIG_ENABLED                               0x00000100
4253 #define A6XX_SP_VS_CONFIG_NTEX__MASK                            0x0001fe00
4254 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT                           9
4255 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
4256 {
4257         return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
4258 }
4259 #define A6XX_SP_VS_CONFIG_NSAMP__MASK                           0x01fe0000
4260 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT                          17
4261 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
4262 {
4263         return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
4264 }
4265 
4266 #define REG_A6XX_SP_VS_INSTRLEN                                 0x0000a824
4267 
4268 #define REG_A6XX_SP_HS_CTRL_REG0                                0x0000a830
4269 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4270 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4271 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4272 {
4273         return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4274 }
4275 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4276 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4277 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4278 {
4279         return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4280 }
4281 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4282 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4283 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4284 {
4285         return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4286 }
4287 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4288 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT                  20
4289 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4290 {
4291         return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4292 }
4293 #define A6XX_SP_HS_CTRL_REG0_VARYING                            0x00400000
4294 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE                       0x04000000
4295 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS                         0x80000000
4296 
4297 #define REG_A6XX_SP_HS_UNKNOWN_A831                             0x0000a831
4298 
4299 #define REG_A6XX_SP_HS_OBJ_START_LO                             0x0000a834
4300 
4301 #define REG_A6XX_SP_HS_OBJ_START_HI                             0x0000a835
4302 
4303 #define REG_A6XX_SP_HS_TEX_COUNT                                0x0000a83a
4304 
4305 #define REG_A6XX_SP_HS_CONFIG                                   0x0000a83b
4306 #define A6XX_SP_HS_CONFIG_ENABLED                               0x00000100
4307 #define A6XX_SP_HS_CONFIG_NTEX__MASK                            0x0001fe00
4308 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT                           9
4309 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
4310 {
4311         return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
4312 }
4313 #define A6XX_SP_HS_CONFIG_NSAMP__MASK                           0x01fe0000
4314 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT                          17
4315 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
4316 {
4317         return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
4318 }
4319 
4320 #define REG_A6XX_SP_HS_INSTRLEN                                 0x0000a83c
4321 
4322 #define REG_A6XX_SP_DS_CTRL_REG0                                0x0000a840
4323 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4324 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4325 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4326 {
4327         return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4328 }
4329 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4330 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4331 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4332 {
4333         return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4334 }
4335 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4336 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4337 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4338 {
4339         return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4340 }
4341 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4342 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT                  20
4343 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4344 {
4345         return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4346 }
4347 #define A6XX_SP_DS_CTRL_REG0_VARYING                            0x00400000
4348 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE                       0x04000000
4349 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS                         0x80000000
4350 
4351 #define REG_A6XX_SP_DS_OBJ_START_LO                             0x0000a85c
4352 
4353 #define REG_A6XX_SP_DS_OBJ_START_HI                             0x0000a85d
4354 
4355 #define REG_A6XX_SP_DS_TEX_COUNT                                0x0000a862
4356 
4357 #define REG_A6XX_SP_DS_CONFIG                                   0x0000a863
4358 #define A6XX_SP_DS_CONFIG_ENABLED                               0x00000100
4359 #define A6XX_SP_DS_CONFIG_NTEX__MASK                            0x0001fe00
4360 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT                           9
4361 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
4362 {
4363         return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
4364 }
4365 #define A6XX_SP_DS_CONFIG_NSAMP__MASK                           0x01fe0000
4366 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT                          17
4367 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
4368 {
4369         return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
4370 }
4371 
4372 #define REG_A6XX_SP_DS_INSTRLEN                                 0x0000a864
4373 
4374 #define REG_A6XX_SP_GS_CTRL_REG0                                0x0000a870
4375 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4376 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4377 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4378 {
4379         return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4380 }
4381 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4382 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4383 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4384 {
4385         return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4386 }
4387 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4388 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4389 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4390 {
4391         return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4392 }
4393 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4394 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT                  20
4395 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4396 {
4397         return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4398 }
4399 #define A6XX_SP_GS_CTRL_REG0_VARYING                            0x00400000
4400 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE                       0x04000000
4401 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS                         0x80000000
4402 
4403 #define REG_A6XX_SP_GS_UNKNOWN_A871                             0x0000a871
4404 
4405 #define REG_A6XX_SP_GS_OBJ_START_LO                             0x0000a88d
4406 
4407 #define REG_A6XX_SP_GS_OBJ_START_HI                             0x0000a88e
4408 
4409 #define REG_A6XX_SP_GS_TEX_COUNT                                0x0000a893
4410 
4411 #define REG_A6XX_SP_GS_CONFIG                                   0x0000a894
4412 #define A6XX_SP_GS_CONFIG_ENABLED                               0x00000100
4413 #define A6XX_SP_GS_CONFIG_NTEX__MASK                            0x0001fe00
4414 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT                           9
4415 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
4416 {
4417         return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
4418 }
4419 #define A6XX_SP_GS_CONFIG_NSAMP__MASK                           0x01fe0000
4420 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT                          17
4421 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
4422 {
4423         return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
4424 }
4425 
4426 #define REG_A6XX_SP_GS_INSTRLEN                                 0x0000a895
4427 
4428 #define REG_A6XX_SP_VS_TEX_SAMP_LO                              0x0000a8a0
4429 
4430 #define REG_A6XX_SP_VS_TEX_SAMP_HI                              0x0000a8a1
4431 
4432 #define REG_A6XX_SP_HS_TEX_SAMP_LO                              0x0000a8a2
4433 
4434 #define REG_A6XX_SP_HS_TEX_SAMP_HI                              0x0000a8a3
4435 
4436 #define REG_A6XX_SP_DS_TEX_SAMP_LO                              0x0000a8a4
4437 
4438 #define REG_A6XX_SP_DS_TEX_SAMP_HI                              0x0000a8a5
4439 
4440 #define REG_A6XX_SP_GS_TEX_SAMP_LO                              0x0000a8a6
4441 
4442 #define REG_A6XX_SP_GS_TEX_SAMP_HI                              0x0000a8a7
4443 
4444 #define REG_A6XX_SP_VS_TEX_CONST_LO                             0x0000a8a8
4445 
4446 #define REG_A6XX_SP_VS_TEX_CONST_HI                             0x0000a8a9
4447 
4448 #define REG_A6XX_SP_HS_TEX_CONST_LO                             0x0000a8aa
4449 
4450 #define REG_A6XX_SP_HS_TEX_CONST_HI                             0x0000a8ab
4451 
4452 #define REG_A6XX_SP_DS_TEX_CONST_LO                             0x0000a8ac
4453 
4454 #define REG_A6XX_SP_DS_TEX_CONST_HI                             0x0000a8ad
4455 
4456 #define REG_A6XX_SP_GS_TEX_CONST_LO                             0x0000a8ae
4457 
4458 #define REG_A6XX_SP_GS_TEX_CONST_HI                             0x0000a8af
4459 
4460 #define REG_A6XX_SP_FS_CTRL_REG0                                0x0000a980
4461 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4462 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4463 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4464 {
4465         return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4466 }
4467 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4468 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4469 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4470 {
4471         return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4472 }
4473 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4474 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4475 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4476 {
4477         return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4478 }
4479 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4480 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
4481 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4482 {
4483         return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4484 }
4485 #define A6XX_SP_FS_CTRL_REG0_VARYING                            0x00400000
4486 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x04000000
4487 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS                         0x80000000
4488 
4489 #define REG_A6XX_SP_UNKNOWN_A982                                0x0000a982
4490 
4491 #define REG_A6XX_SP_FS_OBJ_START_LO                             0x0000a983
4492 
4493 #define REG_A6XX_SP_FS_OBJ_START_HI                             0x0000a984
4494 
4495 #define REG_A6XX_SP_BLEND_CNTL                                  0x0000a989
4496 #define A6XX_SP_BLEND_CNTL_ENABLED                              0x00000001
4497 #define A6XX_SP_BLEND_CNTL_UNK8                                 0x00000100
4498 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE                    0x00000400
4499 
4500 #define REG_A6XX_SP_SRGB_CNTL                                   0x0000a98a
4501 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0                             0x00000001
4502 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1                             0x00000002
4503 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2                             0x00000004
4504 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3                             0x00000008
4505 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4                             0x00000010
4506 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5                             0x00000020
4507 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6                             0x00000040
4508 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7                             0x00000080
4509 
4510 #define REG_A6XX_SP_FS_RENDER_COMPONENTS                        0x0000a98b
4511 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK                  0x0000000f
4512 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT                 0
4513 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
4514 {
4515         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
4516 }
4517 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK                  0x000000f0
4518 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT                 4
4519 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
4520 {
4521         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
4522 }
4523 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK                  0x00000f00
4524 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT                 8
4525 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
4526 {
4527         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
4528 }
4529 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK                  0x0000f000
4530 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT                 12
4531 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
4532 {
4533         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
4534 }
4535 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK                  0x000f0000
4536 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT                 16
4537 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
4538 {
4539         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
4540 }
4541 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK                  0x00f00000
4542 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT                 20
4543 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
4544 {
4545         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
4546 }
4547 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK                  0x0f000000
4548 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT                 24
4549 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
4550 {
4551         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
4552 }
4553 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK                  0xf0000000
4554 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT                 28
4555 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
4556 {
4557         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
4558 }
4559 
4560 #define REG_A6XX_SP_FS_OUTPUT_CNTL0                             0x0000a98c
4561 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK               0x0000ff00
4562 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT              8
4563 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
4564 {
4565         return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
4566 }
4567 
4568 #define REG_A6XX_SP_FS_OUTPUT_CNTL1                             0x0000a98d
4569 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK                       0x0000000f
4570 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT                      0
4571 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
4572 {
4573         return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
4574 }
4575 
4576 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
4577 
4578 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
4579 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK                   0x000000ff
4580 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT                  0
4581 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
4582 {
4583         return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4584 }
4585 #define A6XX_SP_FS_MRT_REG_COLOR_SINT                           0x00000100
4586 #define A6XX_SP_FS_MRT_REG_COLOR_UINT                           0x00000200
4587 
4588 #define REG_A6XX_SP_UNKNOWN_A99E                                0x0000a99e
4589 
4590 #define REG_A6XX_SP_FS_TEX_COUNT                                0x0000a9a7
4591 
4592 #define REG_A6XX_SP_UNKNOWN_A9A8                                0x0000a9a8
4593 
4594 #define REG_A6XX_SP_FS_TEX_SAMP_LO                              0x0000a9e0
4595 
4596 #define REG_A6XX_SP_FS_TEX_SAMP_HI                              0x0000a9e1
4597 
4598 #define REG_A6XX_SP_CS_TEX_SAMP_LO                              0x0000a9e2
4599 
4600 #define REG_A6XX_SP_CS_TEX_SAMP_HI                              0x0000a9e3
4601 
4602 #define REG_A6XX_SP_FS_TEX_CONST_LO                             0x0000a9e4
4603 
4604 #define REG_A6XX_SP_FS_TEX_CONST_HI                             0x0000a9e5
4605 
4606 #define REG_A6XX_SP_CS_TEX_CONST_LO                             0x0000a9e6
4607 
4608 #define REG_A6XX_SP_CS_TEX_CONST_HI                             0x0000a9e7
4609 
4610 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4611 
4612 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4613 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK                       0x000000ff
4614 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT                      0
4615 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4616 {
4617         return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
4618 }
4619 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION                    0x00000100
4620 
4621 #define REG_A6XX_SP_CS_CTRL_REG0                                0x0000a9b0
4622 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4623 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4624 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4625 {
4626         return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4627 }
4628 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4629 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4630 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4631 {
4632         return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4633 }
4634 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4635 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4636 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4637 {
4638         return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4639 }
4640 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4641 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT                  20
4642 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4643 {
4644         return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4645 }
4646 #define A6XX_SP_CS_CTRL_REG0_VARYING                            0x00400000
4647 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE                       0x04000000
4648 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS                         0x80000000
4649 
4650 #define REG_A6XX_SP_CS_OBJ_START_LO                             0x0000a9b4
4651 
4652 #define REG_A6XX_SP_CS_OBJ_START_HI                             0x0000a9b5
4653 
4654 #define REG_A6XX_SP_CS_INSTRLEN                                 0x0000a9bc
4655 
4656 #define REG_A6XX_SP_UNKNOWN_AB00                                0x0000ab00
4657 
4658 #define REG_A6XX_SP_FS_CONFIG                                   0x0000ab04
4659 #define A6XX_SP_FS_CONFIG_ENABLED                               0x00000100
4660 #define A6XX_SP_FS_CONFIG_NTEX__MASK                            0x0001fe00
4661 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT                           9
4662 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
4663 {
4664         return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
4665 }
4666 #define A6XX_SP_FS_CONFIG_NSAMP__MASK                           0x01fe0000
4667 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT                          17
4668 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
4669 {
4670         return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
4671 }
4672 
4673 #define REG_A6XX_SP_FS_INSTRLEN                                 0x0000ab05
4674 
4675 #define REG_A6XX_SP_UNKNOWN_AB20                                0x0000ab20
4676 
4677 #define REG_A6XX_SP_UNKNOWN_ACC0                                0x0000acc0
4678 
4679 #define REG_A6XX_SP_UNKNOWN_AE00                                0x0000ae00
4680 
4681 #define REG_A6XX_SP_UNKNOWN_AE03                                0x0000ae03
4682 
4683 #define REG_A6XX_SP_UNKNOWN_AE04                                0x0000ae04
4684 
4685 #define REG_A6XX_SP_UNKNOWN_AE0F                                0x0000ae0f
4686 
4687 #define REG_A6XX_SP_UNKNOWN_B182                                0x0000b182
4688 
4689 #define REG_A6XX_SP_UNKNOWN_B183                                0x0000b183
4690 
4691 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL                            0x0000b300
4692 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK                  0x00000003
4693 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT                 0
4694 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4695 {
4696         return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4697 }
4698 
4699 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL                           0x0000b301
4700 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK                 0x00000003
4701 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT                0
4702 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4703 {
4704         return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4705 }
4706 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE                  0x00000004
4707 
4708 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO                0x0000b302
4709 
4710 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI                0x0000b303
4711 
4712 #define REG_A6XX_SP_TP_UNKNOWN_B304                             0x0000b304
4713 
4714 #define REG_A6XX_SP_TP_UNKNOWN_B309                             0x0000b309
4715 
4716 #define REG_A6XX_SP_PS_2D_SRC_INFO                              0x0000b4c0
4717 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK               0x000000ff
4718 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT              0
4719 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
4720 {
4721         return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
4722 }
4723 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK                  0x00000300
4724 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT                 8
4725 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
4726 {
4727         return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
4728 }
4729 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK                 0x00000c00
4730 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT                10
4731 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4732 {
4733         return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
4734 }
4735 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS                            0x00001000
4736 #define A6XX_SP_PS_2D_SRC_INFO_FILTER                           0x00010000
4737 
4738 #define REG_A6XX_SP_PS_2D_SRC_SIZE                              0x0000b4c1
4739 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK                      0x00007fff
4740 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT                     0
4741 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
4742 {
4743         return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
4744 }
4745 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK                     0x3fff8000
4746 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT                    15
4747 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
4748 {
4749         return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
4750 }
4751 
4752 #define REG_A6XX_SP_PS_2D_SRC_LO                                0x0000b4c2
4753 
4754 #define REG_A6XX_SP_PS_2D_SRC_HI                                0x0000b4c3
4755 
4756 #define REG_A6XX_SP_PS_2D_SRC_PITCH                             0x0000b4c4
4757 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK                     0x01fffe00
4758 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT                    9
4759 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
4760 {
4761         return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
4762 }
4763 
4764 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO                          0x0000b4ca
4765 
4766 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI                          0x0000b4cb
4767 
4768 #define REG_A6XX_SP_UNKNOWN_B600                                0x0000b600
4769 
4770 #define REG_A6XX_SP_UNKNOWN_B605                                0x0000b605
4771 
4772 #define REG_A6XX_HLSQ_VS_CNTL                                   0x0000b800
4773 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK                        0x000000ff
4774 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT                       0
4775 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
4776 {
4777         return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
4778 }
4779 
4780 #define REG_A6XX_HLSQ_HS_CNTL                                   0x0000b801
4781 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK                        0x000000ff
4782 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT                       0
4783 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
4784 {
4785         return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
4786 }
4787 
4788 #define REG_A6XX_HLSQ_DS_CNTL                                   0x0000b802
4789 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK                        0x000000ff
4790 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT                       0
4791 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
4792 {
4793         return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
4794 }
4795 
4796 #define REG_A6XX_HLSQ_GS_CNTL                                   0x0000b803
4797 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK                        0x000000ff
4798 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT                       0
4799 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
4800 {
4801         return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
4802 }
4803 
4804 #define REG_A6XX_HLSQ_UNKNOWN_B980                              0x0000b980
4805 
4806 #define REG_A6XX_HLSQ_CONTROL_1_REG                             0x0000b982
4807 
4808 #define REG_A6XX_HLSQ_CONTROL_2_REG                             0x0000b983
4809 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK                 0x000000ff
4810 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT                0
4811 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4812 {
4813         return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4814 }
4815 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK                  0x0000ff00
4816 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT                 8
4817 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4818 {
4819         return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4820 }
4821 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK                0x00ff0000
4822 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT               16
4823 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4824 {
4825         return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4826 }
4827 
4828 #define REG_A6XX_HLSQ_CONTROL_3_REG                             0x0000b984
4829 #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK          0x000000ff
4830 #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT         0
4831 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4832 {
4833         return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4834 }
4835 
4836 #define REG_A6XX_HLSQ_CONTROL_4_REG                             0x0000b985
4837 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK              0x00ff0000
4838 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT             16
4839 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4840 {
4841         return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4842 }
4843 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK              0xff000000
4844 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT             24
4845 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4846 {
4847         return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4848 }
4849 
4850 #define REG_A6XX_HLSQ_CONTROL_5_REG                             0x0000b986
4851 
4852 #define REG_A6XX_HLSQ_CS_NDRANGE_0                              0x0000b990
4853 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK                  0x00000003
4854 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT                 0
4855 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4856 {
4857         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4858 }
4859 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK                 0x00000ffc
4860 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT                2
4861 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4862 {
4863         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4864 }
4865 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK                 0x003ff000
4866 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT                12
4867 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4868 {
4869         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4870 }
4871 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK                 0xffc00000
4872 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT                22
4873 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4874 {
4875         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4876 }
4877 
4878 #define REG_A6XX_HLSQ_CS_NDRANGE_1                              0x0000b991
4879 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK               0xffffffff
4880 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT              0
4881 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4882 {
4883         return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4884 }
4885 
4886 #define REG_A6XX_HLSQ_CS_NDRANGE_2                              0x0000b992
4887 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK                0xffffffff
4888 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT               0
4889 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4890 {
4891         return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4892 }
4893 
4894 #define REG_A6XX_HLSQ_CS_NDRANGE_3                              0x0000b993
4895 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK               0xffffffff
4896 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT              0
4897 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4898 {
4899         return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4900 }
4901 
4902 #define REG_A6XX_HLSQ_CS_NDRANGE_4                              0x0000b994
4903 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK                0xffffffff
4904 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT               0
4905 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4906 {
4907         return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4908 }
4909 
4910 #define REG_A6XX_HLSQ_CS_NDRANGE_5                              0x0000b995
4911 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK               0xffffffff
4912 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT              0
4913 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4914 {
4915         return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4916 }
4917 
4918 #define REG_A6XX_HLSQ_CS_NDRANGE_6                              0x0000b996
4919 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK                0xffffffff
4920 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT               0
4921 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4922 {
4923         return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4924 }
4925 
4926 #define REG_A6XX_HLSQ_CS_CNTL_0                                 0x0000b997
4927 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK                   0x000000ff
4928 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT                  0
4929 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4930 {
4931         return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4932 }
4933 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK                          0x0000ff00
4934 #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT                         8
4935 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4936 {
4937         return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4938 }
4939 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK                          0x00ff0000
4940 #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT                         16
4941 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4942 {
4943         return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4944 }
4945 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK                  0xff000000
4946 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT                 24
4947 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4948 {
4949         return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4950 }
4951 
4952 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X                         0x0000b999
4953 
4954 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y                         0x0000b99a
4955 
4956 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z                         0x0000b99b
4957 
4958 #define REG_A6XX_HLSQ_UPDATE_CNTL                               0x0000bb08
4959 
4960 #define REG_A6XX_HLSQ_FS_CNTL                                   0x0000bb10
4961 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK                        0x000000ff
4962 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT                       0
4963 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
4964 {
4965         return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
4966 }
4967 
4968 #define REG_A6XX_HLSQ_UNKNOWN_BB11                              0x0000bb11
4969 
4970 #define REG_A6XX_HLSQ_UNKNOWN_BE00                              0x0000be00
4971 
4972 #define REG_A6XX_HLSQ_UNKNOWN_BE01                              0x0000be01
4973 
4974 #define REG_A6XX_HLSQ_UNKNOWN_BE04                              0x0000be04
4975 
4976 #define REG_A6XX_TEX_SAMP_0                                     0x00000000
4977 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR                   0x00000001
4978 #define A6XX_TEX_SAMP_0_XY_MAG__MASK                            0x00000006
4979 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT                           1
4980 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
4981 {
4982         return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
4983 }
4984 #define A6XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000018
4985 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT                           3
4986 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
4987 {
4988         return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
4989 }
4990 #define A6XX_TEX_SAMP_0_WRAP_S__MASK                            0x000000e0
4991 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT                           5
4992 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
4993 {
4994         return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
4995 }
4996 #define A6XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000700
4997 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT                           8
4998 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
4999 {
5000         return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
5001 }
5002 #define A6XX_TEX_SAMP_0_WRAP_R__MASK                            0x00003800
5003 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT                           11
5004 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
5005 {
5006         return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
5007 }
5008 #define A6XX_TEX_SAMP_0_ANISO__MASK                             0x0001c000
5009 #define A6XX_TEX_SAMP_0_ANISO__SHIFT                            14
5010 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
5011 {
5012         return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
5013 }
5014 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK                          0xfff80000
5015 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT                         19
5016 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
5017 {
5018         return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
5019 }
5020 
5021 #define REG_A6XX_TEX_SAMP_1                                     0x00000001
5022 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK                      0x0000000e
5023 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT                     1
5024 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
5025 {
5026         return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
5027 }
5028 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF                  0x00000010
5029 #define A6XX_TEX_SAMP_1_UNNORM_COORDS                           0x00000020
5030 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR                    0x00000040
5031 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK                           0x000fff00
5032 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT                          8
5033 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
5034 {
5035         return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
5036 }
5037 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK                           0xfff00000
5038 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT                          20
5039 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
5040 {
5041         return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
5042 }
5043 
5044 #define REG_A6XX_TEX_SAMP_2                                     0x00000002
5045 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK                     0xfffffff0
5046 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT                    4
5047 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5048 {
5049         return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5050 }
5051 
5052 #define REG_A6XX_TEX_SAMP_3                                     0x00000003
5053 
5054 #define REG_A6XX_TEX_CONST_0                                    0x00000000
5055 #define A6XX_TEX_CONST_0_TILE_MODE__MASK                        0x00000003
5056 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT                       0
5057 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
5058 {
5059         return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
5060 }
5061 #define A6XX_TEX_CONST_0_SRGB                                   0x00000004
5062 #define A6XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
5063 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
5064 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
5065 {
5066         return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
5067 }
5068 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
5069 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
5070 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
5071 {
5072         return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
5073 }
5074 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
5075 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
5076 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
5077 {
5078         return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
5079 }
5080 #define A6XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
5081 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
5082 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
5083 {
5084         return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
5085 }
5086 #define A6XX_TEX_CONST_0_MIPLVLS__MASK                          0x000f0000
5087 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT                         16
5088 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5089 {
5090         return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
5091 }
5092 #define A6XX_TEX_CONST_0_SAMPLES__MASK                          0x00300000
5093 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT                         20
5094 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5095 {
5096         return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
5097 }
5098 #define A6XX_TEX_CONST_0_FMT__MASK                              0x3fc00000
5099 #define A6XX_TEX_CONST_0_FMT__SHIFT                             22
5100 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
5101 {
5102         return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
5103 }
5104 #define A6XX_TEX_CONST_0_SWAP__MASK                             0xc0000000
5105 #define A6XX_TEX_CONST_0_SWAP__SHIFT                            30
5106 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5107 {
5108         return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
5109 }
5110 
5111 #define REG_A6XX_TEX_CONST_1                                    0x00000001
5112 #define A6XX_TEX_CONST_1_WIDTH__MASK                            0x00007fff
5113 #define A6XX_TEX_CONST_1_WIDTH__SHIFT                           0
5114 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
5115 {
5116         return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
5117 }
5118 #define A6XX_TEX_CONST_1_HEIGHT__MASK                           0x3fff8000
5119 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT                          15
5120 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
5121 {
5122         return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
5123 }
5124 
5125 #define REG_A6XX_TEX_CONST_2                                    0x00000002
5126 #define A6XX_TEX_CONST_2_FETCHSIZE__MASK                        0x0000000f
5127 #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT                       0
5128 static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
5129 {
5130         return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
5131 }
5132 #define A6XX_TEX_CONST_2_PITCH__MASK                            0x1fffff80
5133 #define A6XX_TEX_CONST_2_PITCH__SHIFT                           7
5134 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
5135 {
5136         return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
5137 }
5138 #define A6XX_TEX_CONST_2_TYPE__MASK                             0x60000000
5139 #define A6XX_TEX_CONST_2_TYPE__SHIFT                            29
5140 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
5141 {
5142         return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
5143 }
5144 
5145 #define REG_A6XX_TEX_CONST_3                                    0x00000003
5146 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK                      0x00003fff
5147 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT                     0
5148 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5149 {
5150         return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5151 }
5152 #define A6XX_TEX_CONST_3_FLAG                                   0x10000000
5153 
5154 #define REG_A6XX_TEX_CONST_4                                    0x00000004
5155 #define A6XX_TEX_CONST_4_BASE_LO__MASK                          0xffffffe0
5156 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT                         5
5157 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
5158 {
5159         return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
5160 }
5161 
5162 #define REG_A6XX_TEX_CONST_5                                    0x00000005
5163 #define A6XX_TEX_CONST_5_BASE_HI__MASK                          0x0001ffff
5164 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT                         0
5165 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
5166 {
5167         return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
5168 }
5169 #define A6XX_TEX_CONST_5_DEPTH__MASK                            0x3ffe0000
5170 #define A6XX_TEX_CONST_5_DEPTH__SHIFT                           17
5171 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
5172 {
5173         return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
5174 }
5175 
5176 #define REG_A6XX_TEX_CONST_6                                    0x00000006
5177 
5178 #define REG_A6XX_TEX_CONST_7                                    0x00000007
5179 #define A6XX_TEX_CONST_7_FLAG_LO__MASK                          0xffffffe0
5180 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT                         5
5181 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
5182 {
5183         return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
5184 }
5185 
5186 #define REG_A6XX_TEX_CONST_8                                    0x00000008
5187 #define A6XX_TEX_CONST_8_FLAG_HI__MASK                          0x0001ffff
5188 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT                         0
5189 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
5190 {
5191         return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
5192 }
5193 
5194 #define REG_A6XX_TEX_CONST_9                                    0x00000009
5195 
5196 #define REG_A6XX_TEX_CONST_10                                   0x0000000a
5197 
5198 #define REG_A6XX_TEX_CONST_11                                   0x0000000b
5199 
5200 #define REG_A6XX_TEX_CONST_12                                   0x0000000c
5201 
5202 #define REG_A6XX_TEX_CONST_13                                   0x0000000d
5203 
5204 #define REG_A6XX_TEX_CONST_14                                   0x0000000e
5205 
5206 #define REG_A6XX_TEX_CONST_15                                   0x0000000f
5207 
5208 #define REG_A6XX_PDC_GPU_ENABLE_PDC                             0x00001140
5209 
5210 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR                         0x00001148
5211 
5212 #define REG_A6XX_PDC_GPU_TCS0_CONTROL                           0x00001540
5213 
5214 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK                   0x00001541
5215 
5216 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK            0x00001542
5217 
5218 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID                        0x00001543
5219 
5220 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR                         0x00001544
5221 
5222 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA                         0x00001545
5223 
5224 #define REG_A6XX_PDC_GPU_TCS1_CONTROL                           0x00001572
5225 
5226 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK                   0x00001573
5227 
5228 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK            0x00001574
5229 
5230 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID                        0x00001575
5231 
5232 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR                         0x00001576
5233 
5234 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA                         0x00001577
5235 
5236 #define REG_A6XX_PDC_GPU_TCS2_CONTROL                           0x000015a4
5237 
5238 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK                   0x000015a5
5239 
5240 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK            0x000015a6
5241 
5242 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID                        0x000015a7
5243 
5244 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR                         0x000015a8
5245 
5246 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA                         0x000015a9
5247 
5248 #define REG_A6XX_PDC_GPU_TCS3_CONTROL                           0x000015d6
5249 
5250 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK                   0x000015d7
5251 
5252 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK            0x000015d8
5253 
5254 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID                        0x000015d9
5255 
5256 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR                         0x000015da
5257 
5258 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA                         0x000015db
5259 
5260 #define REG_A6XX_PDC_GPU_SEQ_MEM_0                              0x00000000
5261 
5262 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A                       0x00000000
5263 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK          0x000000ff
5264 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT         0
5265 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
5266 {
5267         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
5268 }
5269 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK        0x0000ff00
5270 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT       8
5271 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
5272 {
5273         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
5274 }
5275 
5276 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B                       0x00000001
5277 
5278 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C                       0x00000002
5279 
5280 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D                       0x00000003
5281 
5282 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT                       0x00000004
5283 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK             0x0000003f
5284 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT            0
5285 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
5286 {
5287         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
5288 }
5289 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK               0x00007000
5290 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT              12
5291 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
5292 {
5293         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
5294 }
5295 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK                0xf0000000
5296 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT               28
5297 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
5298 {
5299         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
5300 }
5301 
5302 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM                       0x00000005
5303 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK              0x0f000000
5304 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT             24
5305 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
5306 {
5307         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
5308 }
5309 
5310 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0                      0x00000008
5311 
5312 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1                      0x00000009
5313 
5314 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2                      0x0000000a
5315 
5316 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3                      0x0000000b
5317 
5318 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0                     0x0000000c
5319 
5320 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1                     0x0000000d
5321 
5322 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2                     0x0000000e
5323 
5324 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3                     0x0000000f
5325 
5326 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0                     0x00000010
5327 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK            0x0000000f
5328 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT           0
5329 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
5330 {
5331         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
5332 }
5333 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK            0x000000f0
5334 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT           4
5335 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
5336 {
5337         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
5338 }
5339 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK            0x00000f00
5340 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT           8
5341 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
5342 {
5343         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
5344 }
5345 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK            0x0000f000
5346 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT           12
5347 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
5348 {
5349         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
5350 }
5351 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK            0x000f0000
5352 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT           16
5353 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
5354 {
5355         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
5356 }
5357 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK            0x00f00000
5358 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT           20
5359 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
5360 {
5361         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
5362 }
5363 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK            0x0f000000
5364 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT           24
5365 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
5366 {
5367         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
5368 }
5369 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK            0xf0000000
5370 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT           28
5371 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
5372 {
5373         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
5374 }
5375 
5376 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1                     0x00000011
5377 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK            0x0000000f
5378 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT           0
5379 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
5380 {
5381         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
5382 }
5383 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK            0x000000f0
5384 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT           4
5385 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
5386 {
5387         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
5388 }
5389 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK           0x00000f00
5390 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT          8
5391 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
5392 {
5393         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
5394 }
5395 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK           0x0000f000
5396 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT          12
5397 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
5398 {
5399         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
5400 }
5401 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK           0x000f0000
5402 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT          16
5403 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
5404 {
5405         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
5406 }
5407 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK           0x00f00000
5408 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT          20
5409 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
5410 {
5411         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
5412 }
5413 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK           0x0f000000
5414 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT          24
5415 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
5416 {
5417         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
5418 }
5419 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK           0xf0000000
5420 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT          28
5421 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
5422 {
5423         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
5424 }
5425 
5426 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1                  0x0000002f
5427 
5428 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2                  0x00000030
5429 
5430 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0                    0x00000001
5431 
5432 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1                    0x00000002
5433 
5434 
5435 #endif /* A6XX_XML */
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