This source file includes following definitions.
- vmw_cbs_context
- vmw_binding_loc
- vmw_binding_drop
- vmw_binding_add
- vmw_binding_transfer
- vmw_binding_state_kill
- vmw_binding_state_scrub
- vmw_binding_res_list_kill
- vmw_binding_res_list_scrub
- vmw_binding_state_commit
- vmw_binding_rebind_all
- vmw_binding_scrub_shader
- vmw_binding_scrub_render_target
- vmw_binding_scrub_texture
- vmw_binding_scrub_dx_shader
- vmw_binding_scrub_cb
- vmw_collect_view_ids
- vmw_collect_dirty_view_ids
- vmw_emit_set_sr
- vmw_emit_set_rt
- vmw_collect_so_targets
- vmw_emit_set_so
- vmw_binding_emit_dirty_ps
- vmw_collect_dirty_vbs
- vmw_emit_set_vb
- vmw_binding_emit_dirty
- vmw_binding_scrub_sr
- vmw_binding_scrub_dx_rt
- vmw_binding_scrub_so
- vmw_binding_scrub_vb
- vmw_binding_scrub_ib
- vmw_binding_state_alloc
- vmw_binding_state_free
- vmw_binding_state_list
- vmw_binding_state_reset
- vmw_binding_dirtying
- vmw_binding_build_asserts
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54 #include "vmwgfx_drv.h"
55 #include "vmwgfx_binding.h"
56 #include "device_include/svga3d_reg.h"
57
58 #define VMW_BINDING_RT_BIT 0
59 #define VMW_BINDING_PS_BIT 1
60 #define VMW_BINDING_SO_BIT 2
61 #define VMW_BINDING_VB_BIT 3
62 #define VMW_BINDING_NUM_BITS 4
63
64 #define VMW_BINDING_PS_SR_BIT 0
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92 struct vmw_ctx_binding_state {
93 struct vmw_private *dev_priv;
94 struct list_head list;
95 struct vmw_ctx_bindinfo_view render_targets[SVGA3D_RT_MAX];
96 struct vmw_ctx_bindinfo_tex texture_units[SVGA3D_NUM_TEXTURE_UNITS];
97 struct vmw_ctx_bindinfo_view ds_view;
98 struct vmw_ctx_bindinfo_so so_targets[SVGA3D_DX_MAX_SOTARGETS];
99 struct vmw_ctx_bindinfo_vb vertex_buffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
100 struct vmw_ctx_bindinfo_ib index_buffer;
101 struct vmw_dx_shader_bindings per_shader[SVGA3D_NUM_SHADERTYPE_DX10];
102
103 unsigned long dirty;
104 DECLARE_BITMAP(dirty_vb, SVGA3D_DX_MAX_VERTEXBUFFERS);
105
106 u32 bind_cmd_buffer[VMW_MAX_VIEW_BINDINGS];
107 u32 bind_cmd_count;
108 u32 bind_first_slot;
109 };
110
111 static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind);
112 static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi,
113 bool rebind);
114 static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, bool rebind);
115 static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind);
116 static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind);
117 static int vmw_binding_scrub_sr(struct vmw_ctx_bindinfo *bi, bool rebind);
118 static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind);
119 static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs);
120 static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi,
121 bool rebind);
122 static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind);
123 static int vmw_binding_scrub_vb(struct vmw_ctx_bindinfo *bi, bool rebind);
124 static void vmw_binding_build_asserts(void) __attribute__ ((unused));
125
126 typedef int (*vmw_scrub_func)(struct vmw_ctx_bindinfo *, bool);
127
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139
140 struct vmw_binding_info {
141 size_t size;
142 const size_t *offsets;
143 vmw_scrub_func scrub_func;
144 };
145
146
147
148
149
150 static const size_t vmw_binding_shader_offsets[] = {
151 offsetof(struct vmw_ctx_binding_state, per_shader[0].shader),
152 offsetof(struct vmw_ctx_binding_state, per_shader[1].shader),
153 offsetof(struct vmw_ctx_binding_state, per_shader[2].shader),
154 };
155 static const size_t vmw_binding_rt_offsets[] = {
156 offsetof(struct vmw_ctx_binding_state, render_targets),
157 };
158 static const size_t vmw_binding_tex_offsets[] = {
159 offsetof(struct vmw_ctx_binding_state, texture_units),
160 };
161 static const size_t vmw_binding_cb_offsets[] = {
162 offsetof(struct vmw_ctx_binding_state, per_shader[0].const_buffers),
163 offsetof(struct vmw_ctx_binding_state, per_shader[1].const_buffers),
164 offsetof(struct vmw_ctx_binding_state, per_shader[2].const_buffers),
165 };
166 static const size_t vmw_binding_dx_ds_offsets[] = {
167 offsetof(struct vmw_ctx_binding_state, ds_view),
168 };
169 static const size_t vmw_binding_sr_offsets[] = {
170 offsetof(struct vmw_ctx_binding_state, per_shader[0].shader_res),
171 offsetof(struct vmw_ctx_binding_state, per_shader[1].shader_res),
172 offsetof(struct vmw_ctx_binding_state, per_shader[2].shader_res),
173 };
174 static const size_t vmw_binding_so_offsets[] = {
175 offsetof(struct vmw_ctx_binding_state, so_targets),
176 };
177 static const size_t vmw_binding_vb_offsets[] = {
178 offsetof(struct vmw_ctx_binding_state, vertex_buffers),
179 };
180 static const size_t vmw_binding_ib_offsets[] = {
181 offsetof(struct vmw_ctx_binding_state, index_buffer),
182 };
183
184 static const struct vmw_binding_info vmw_binding_infos[] = {
185 [vmw_ctx_binding_shader] = {
186 .size = sizeof(struct vmw_ctx_bindinfo_shader),
187 .offsets = vmw_binding_shader_offsets,
188 .scrub_func = vmw_binding_scrub_shader},
189 [vmw_ctx_binding_rt] = {
190 .size = sizeof(struct vmw_ctx_bindinfo_view),
191 .offsets = vmw_binding_rt_offsets,
192 .scrub_func = vmw_binding_scrub_render_target},
193 [vmw_ctx_binding_tex] = {
194 .size = sizeof(struct vmw_ctx_bindinfo_tex),
195 .offsets = vmw_binding_tex_offsets,
196 .scrub_func = vmw_binding_scrub_texture},
197 [vmw_ctx_binding_cb] = {
198 .size = sizeof(struct vmw_ctx_bindinfo_cb),
199 .offsets = vmw_binding_cb_offsets,
200 .scrub_func = vmw_binding_scrub_cb},
201 [vmw_ctx_binding_dx_shader] = {
202 .size = sizeof(struct vmw_ctx_bindinfo_shader),
203 .offsets = vmw_binding_shader_offsets,
204 .scrub_func = vmw_binding_scrub_dx_shader},
205 [vmw_ctx_binding_dx_rt] = {
206 .size = sizeof(struct vmw_ctx_bindinfo_view),
207 .offsets = vmw_binding_rt_offsets,
208 .scrub_func = vmw_binding_scrub_dx_rt},
209 [vmw_ctx_binding_sr] = {
210 .size = sizeof(struct vmw_ctx_bindinfo_view),
211 .offsets = vmw_binding_sr_offsets,
212 .scrub_func = vmw_binding_scrub_sr},
213 [vmw_ctx_binding_ds] = {
214 .size = sizeof(struct vmw_ctx_bindinfo_view),
215 .offsets = vmw_binding_dx_ds_offsets,
216 .scrub_func = vmw_binding_scrub_dx_rt},
217 [vmw_ctx_binding_so] = {
218 .size = sizeof(struct vmw_ctx_bindinfo_so),
219 .offsets = vmw_binding_so_offsets,
220 .scrub_func = vmw_binding_scrub_so},
221 [vmw_ctx_binding_vb] = {
222 .size = sizeof(struct vmw_ctx_bindinfo_vb),
223 .offsets = vmw_binding_vb_offsets,
224 .scrub_func = vmw_binding_scrub_vb},
225 [vmw_ctx_binding_ib] = {
226 .size = sizeof(struct vmw_ctx_bindinfo_ib),
227 .offsets = vmw_binding_ib_offsets,
228 .scrub_func = vmw_binding_scrub_ib},
229 };
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243 static const struct vmw_resource *
244 vmw_cbs_context(const struct vmw_ctx_binding_state *cbs)
245 {
246 if (list_empty(&cbs->list))
247 return NULL;
248
249 return list_first_entry(&cbs->list, struct vmw_ctx_bindinfo,
250 ctx_list)->ctx;
251 }
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261 static struct vmw_ctx_bindinfo *
262 vmw_binding_loc(struct vmw_ctx_binding_state *cbs,
263 enum vmw_ctx_binding_type bt, u32 shader_slot, u32 slot)
264 {
265 const struct vmw_binding_info *b = &vmw_binding_infos[bt];
266 size_t offset = b->offsets[shader_slot] + b->size*slot;
267
268 return (struct vmw_ctx_bindinfo *)((u8 *) cbs + offset);
269 }
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280 static void vmw_binding_drop(struct vmw_ctx_bindinfo *bi)
281 {
282 list_del(&bi->ctx_list);
283 if (!list_empty(&bi->res_list))
284 list_del(&bi->res_list);
285 bi->ctx = NULL;
286 }
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297 void vmw_binding_add(struct vmw_ctx_binding_state *cbs,
298 const struct vmw_ctx_bindinfo *bi,
299 u32 shader_slot, u32 slot)
300 {
301 struct vmw_ctx_bindinfo *loc =
302 vmw_binding_loc(cbs, bi->bt, shader_slot, slot);
303 const struct vmw_binding_info *b = &vmw_binding_infos[bi->bt];
304
305 if (loc->ctx != NULL)
306 vmw_binding_drop(loc);
307
308 memcpy(loc, bi, b->size);
309 loc->scrubbed = false;
310 list_add(&loc->ctx_list, &cbs->list);
311 INIT_LIST_HEAD(&loc->res_list);
312 }
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321 static void vmw_binding_transfer(struct vmw_ctx_binding_state *cbs,
322 const struct vmw_ctx_binding_state *from,
323 const struct vmw_ctx_bindinfo *bi)
324 {
325 size_t offset = (unsigned long)bi - (unsigned long)from;
326 struct vmw_ctx_bindinfo *loc = (struct vmw_ctx_bindinfo *)
327 ((unsigned long) cbs + offset);
328
329 if (loc->ctx != NULL) {
330 WARN_ON(bi->scrubbed);
331
332 vmw_binding_drop(loc);
333 }
334
335 if (bi->res != NULL) {
336 memcpy(loc, bi, vmw_binding_infos[bi->bt].size);
337 list_add_tail(&loc->ctx_list, &cbs->list);
338 list_add_tail(&loc->res_list, &loc->res->binding_head);
339 }
340 }
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351 void vmw_binding_state_kill(struct vmw_ctx_binding_state *cbs)
352 {
353 struct vmw_ctx_bindinfo *entry, *next;
354
355 vmw_binding_state_scrub(cbs);
356 list_for_each_entry_safe(entry, next, &cbs->list, ctx_list)
357 vmw_binding_drop(entry);
358 }
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369 void vmw_binding_state_scrub(struct vmw_ctx_binding_state *cbs)
370 {
371 struct vmw_ctx_bindinfo *entry;
372
373 list_for_each_entry(entry, &cbs->list, ctx_list) {
374 if (!entry->scrubbed) {
375 (void) vmw_binding_infos[entry->bt].scrub_func
376 (entry, false);
377 entry->scrubbed = true;
378 }
379 }
380
381 (void) vmw_binding_emit_dirty(cbs);
382 }
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393 void vmw_binding_res_list_kill(struct list_head *head)
394 {
395 struct vmw_ctx_bindinfo *entry, *next;
396
397 vmw_binding_res_list_scrub(head);
398 list_for_each_entry_safe(entry, next, head, res_list)
399 vmw_binding_drop(entry);
400 }
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411 void vmw_binding_res_list_scrub(struct list_head *head)
412 {
413 struct vmw_ctx_bindinfo *entry;
414
415 list_for_each_entry(entry, head, res_list) {
416 if (!entry->scrubbed) {
417 (void) vmw_binding_infos[entry->bt].scrub_func
418 (entry, false);
419 entry->scrubbed = true;
420 }
421 }
422
423 list_for_each_entry(entry, head, res_list) {
424 struct vmw_ctx_binding_state *cbs =
425 vmw_context_binding_state(entry->ctx);
426
427 (void) vmw_binding_emit_dirty(cbs);
428 }
429 }
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444 void vmw_binding_state_commit(struct vmw_ctx_binding_state *to,
445 struct vmw_ctx_binding_state *from)
446 {
447 struct vmw_ctx_bindinfo *entry, *next;
448
449 list_for_each_entry_safe(entry, next, &from->list, ctx_list) {
450 vmw_binding_transfer(to, from, entry);
451 vmw_binding_drop(entry);
452 }
453 }
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463 int vmw_binding_rebind_all(struct vmw_ctx_binding_state *cbs)
464 {
465 struct vmw_ctx_bindinfo *entry;
466 int ret;
467
468 list_for_each_entry(entry, &cbs->list, ctx_list) {
469 if (likely(!entry->scrubbed))
470 continue;
471
472 if ((entry->res == NULL || entry->res->id ==
473 SVGA3D_INVALID_ID))
474 continue;
475
476 ret = vmw_binding_infos[entry->bt].scrub_func(entry, true);
477 if (unlikely(ret != 0))
478 return ret;
479
480 entry->scrubbed = false;
481 }
482
483 return vmw_binding_emit_dirty(cbs);
484 }
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492 static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
493 {
494 struct vmw_ctx_bindinfo_shader *binding =
495 container_of(bi, typeof(*binding), bi);
496 struct vmw_private *dev_priv = bi->ctx->dev_priv;
497 struct {
498 SVGA3dCmdHeader header;
499 SVGA3dCmdSetShader body;
500 } *cmd;
501
502 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
503 if (unlikely(cmd == NULL))
504 return -ENOMEM;
505
506 cmd->header.id = SVGA_3D_CMD_SET_SHADER;
507 cmd->header.size = sizeof(cmd->body);
508 cmd->body.cid = bi->ctx->id;
509 cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
510 cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
511 vmw_fifo_commit(dev_priv, sizeof(*cmd));
512
513 return 0;
514 }
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523 static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi,
524 bool rebind)
525 {
526 struct vmw_ctx_bindinfo_view *binding =
527 container_of(bi, typeof(*binding), bi);
528 struct vmw_private *dev_priv = bi->ctx->dev_priv;
529 struct {
530 SVGA3dCmdHeader header;
531 SVGA3dCmdSetRenderTarget body;
532 } *cmd;
533
534 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
535 if (unlikely(cmd == NULL))
536 return -ENOMEM;
537
538 cmd->header.id = SVGA_3D_CMD_SETRENDERTARGET;
539 cmd->header.size = sizeof(cmd->body);
540 cmd->body.cid = bi->ctx->id;
541 cmd->body.type = binding->slot;
542 cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
543 cmd->body.target.face = 0;
544 cmd->body.target.mipmap = 0;
545 vmw_fifo_commit(dev_priv, sizeof(*cmd));
546
547 return 0;
548 }
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559 static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi,
560 bool rebind)
561 {
562 struct vmw_ctx_bindinfo_tex *binding =
563 container_of(bi, typeof(*binding), bi);
564 struct vmw_private *dev_priv = bi->ctx->dev_priv;
565 struct {
566 SVGA3dCmdHeader header;
567 struct {
568 SVGA3dCmdSetTextureState c;
569 SVGA3dTextureState s1;
570 } body;
571 } *cmd;
572
573 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
574 if (unlikely(cmd == NULL))
575 return -ENOMEM;
576
577 cmd->header.id = SVGA_3D_CMD_SETTEXTURESTATE;
578 cmd->header.size = sizeof(cmd->body);
579 cmd->body.c.cid = bi->ctx->id;
580 cmd->body.s1.stage = binding->texture_stage;
581 cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
582 cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
583 vmw_fifo_commit(dev_priv, sizeof(*cmd));
584
585 return 0;
586 }
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594 static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
595 {
596 struct vmw_ctx_bindinfo_shader *binding =
597 container_of(bi, typeof(*binding), bi);
598 struct vmw_private *dev_priv = bi->ctx->dev_priv;
599 struct {
600 SVGA3dCmdHeader header;
601 SVGA3dCmdDXSetShader body;
602 } *cmd;
603
604 cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
605 if (unlikely(cmd == NULL))
606 return -ENOMEM;
607
608 cmd->header.id = SVGA_3D_CMD_DX_SET_SHADER;
609 cmd->header.size = sizeof(cmd->body);
610 cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
611 cmd->body.shaderId = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
612 vmw_fifo_commit(dev_priv, sizeof(*cmd));
613
614 return 0;
615 }
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623 static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind)
624 {
625 struct vmw_ctx_bindinfo_cb *binding =
626 container_of(bi, typeof(*binding), bi);
627 struct vmw_private *dev_priv = bi->ctx->dev_priv;
628 struct {
629 SVGA3dCmdHeader header;
630 SVGA3dCmdDXSetSingleConstantBuffer body;
631 } *cmd;
632
633 cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
634 if (unlikely(cmd == NULL))
635 return -ENOMEM;
636
637 cmd->header.id = SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER;
638 cmd->header.size = sizeof(cmd->body);
639 cmd->body.slot = binding->slot;
640 cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
641 if (rebind) {
642 cmd->body.offsetInBytes = binding->offset;
643 cmd->body.sizeInBytes = binding->size;
644 cmd->body.sid = bi->res->id;
645 } else {
646 cmd->body.offsetInBytes = 0;
647 cmd->body.sizeInBytes = 0;
648 cmd->body.sid = SVGA3D_INVALID_ID;
649 }
650 vmw_fifo_commit(dev_priv, sizeof(*cmd));
651
652 return 0;
653 }
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669 static void vmw_collect_view_ids(struct vmw_ctx_binding_state *cbs,
670 const struct vmw_ctx_bindinfo *bi,
671 u32 max_num)
672 {
673 const struct vmw_ctx_bindinfo_view *biv =
674 container_of(bi, struct vmw_ctx_bindinfo_view, bi);
675 unsigned long i;
676
677 cbs->bind_cmd_count = 0;
678 cbs->bind_first_slot = 0;
679
680 for (i = 0; i < max_num; ++i, ++biv) {
681 if (!biv->bi.ctx)
682 break;
683
684 cbs->bind_cmd_buffer[cbs->bind_cmd_count++] =
685 ((biv->bi.scrubbed) ?
686 SVGA3D_INVALID_ID : biv->bi.res->id);
687 }
688 }
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704 static void vmw_collect_dirty_view_ids(struct vmw_ctx_binding_state *cbs,
705 const struct vmw_ctx_bindinfo *bi,
706 unsigned long *dirty,
707 u32 max_num)
708 {
709 const struct vmw_ctx_bindinfo_view *biv =
710 container_of(bi, struct vmw_ctx_bindinfo_view, bi);
711 unsigned long i, next_bit;
712
713 cbs->bind_cmd_count = 0;
714 i = find_first_bit(dirty, max_num);
715 next_bit = i;
716 cbs->bind_first_slot = i;
717
718 biv += i;
719 for (; i < max_num; ++i, ++biv) {
720 cbs->bind_cmd_buffer[cbs->bind_cmd_count++] =
721 ((!biv->bi.ctx || biv->bi.scrubbed) ?
722 SVGA3D_INVALID_ID : biv->bi.res->id);
723
724 if (next_bit == i) {
725 next_bit = find_next_bit(dirty, max_num, i + 1);
726 if (next_bit >= max_num)
727 break;
728 }
729 }
730 }
731
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734
735
736
737 static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs,
738 int shader_slot)
739 {
740 const struct vmw_ctx_bindinfo *loc =
741 &cbs->per_shader[shader_slot].shader_res[0].bi;
742 struct {
743 SVGA3dCmdHeader header;
744 SVGA3dCmdDXSetShaderResources body;
745 } *cmd;
746 size_t cmd_size, view_id_size;
747 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
748
749 vmw_collect_dirty_view_ids(cbs, loc,
750 cbs->per_shader[shader_slot].dirty_sr,
751 SVGA3D_DX_MAX_SRVIEWS);
752 if (cbs->bind_cmd_count == 0)
753 return 0;
754
755 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
756 cmd_size = sizeof(*cmd) + view_id_size;
757 cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
758 if (unlikely(cmd == NULL))
759 return -ENOMEM;
760
761 cmd->header.id = SVGA_3D_CMD_DX_SET_SHADER_RESOURCES;
762 cmd->header.size = sizeof(cmd->body) + view_id_size;
763 cmd->body.type = shader_slot + SVGA3D_SHADERTYPE_MIN;
764 cmd->body.startView = cbs->bind_first_slot;
765
766 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
767
768 vmw_fifo_commit(ctx->dev_priv, cmd_size);
769 bitmap_clear(cbs->per_shader[shader_slot].dirty_sr,
770 cbs->bind_first_slot, cbs->bind_cmd_count);
771
772 return 0;
773 }
774
775
776
777
778
779
780 static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs)
781 {
782 const struct vmw_ctx_bindinfo *loc = &cbs->render_targets[0].bi;
783 struct {
784 SVGA3dCmdHeader header;
785 SVGA3dCmdDXSetRenderTargets body;
786 } *cmd;
787 size_t cmd_size, view_id_size;
788 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
789
790 vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
791 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
792 cmd_size = sizeof(*cmd) + view_id_size;
793 cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
794 if (unlikely(cmd == NULL))
795 return -ENOMEM;
796
797 cmd->header.id = SVGA_3D_CMD_DX_SET_RENDERTARGETS;
798 cmd->header.size = sizeof(cmd->body) + view_id_size;
799
800 if (cbs->ds_view.bi.ctx && !cbs->ds_view.bi.scrubbed)
801 cmd->body.depthStencilViewId = cbs->ds_view.bi.res->id;
802 else
803 cmd->body.depthStencilViewId = SVGA3D_INVALID_ID;
804
805 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
806
807 vmw_fifo_commit(ctx->dev_priv, cmd_size);
808
809 return 0;
810
811 }
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827 static void vmw_collect_so_targets(struct vmw_ctx_binding_state *cbs,
828 const struct vmw_ctx_bindinfo *bi,
829 u32 max_num)
830 {
831 const struct vmw_ctx_bindinfo_so *biso =
832 container_of(bi, struct vmw_ctx_bindinfo_so, bi);
833 unsigned long i;
834 SVGA3dSoTarget *so_buffer = (SVGA3dSoTarget *) cbs->bind_cmd_buffer;
835
836 cbs->bind_cmd_count = 0;
837 cbs->bind_first_slot = 0;
838
839 for (i = 0; i < max_num; ++i, ++biso, ++so_buffer,
840 ++cbs->bind_cmd_count) {
841 if (!biso->bi.ctx)
842 break;
843
844 if (!biso->bi.scrubbed) {
845 so_buffer->sid = biso->bi.res->id;
846 so_buffer->offset = biso->offset;
847 so_buffer->sizeInBytes = biso->size;
848 } else {
849 so_buffer->sid = SVGA3D_INVALID_ID;
850 so_buffer->offset = 0;
851 so_buffer->sizeInBytes = 0;
852 }
853 }
854 }
855
856
857
858
859
860
861 static int vmw_emit_set_so(struct vmw_ctx_binding_state *cbs)
862 {
863 const struct vmw_ctx_bindinfo *loc = &cbs->so_targets[0].bi;
864 struct {
865 SVGA3dCmdHeader header;
866 SVGA3dCmdDXSetSOTargets body;
867 } *cmd;
868 size_t cmd_size, so_target_size;
869 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
870
871 vmw_collect_so_targets(cbs, loc, SVGA3D_DX_MAX_SOTARGETS);
872 if (cbs->bind_cmd_count == 0)
873 return 0;
874
875 so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);
876 cmd_size = sizeof(*cmd) + so_target_size;
877 cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
878 if (unlikely(cmd == NULL))
879 return -ENOMEM;
880
881 cmd->header.id = SVGA_3D_CMD_DX_SET_SOTARGETS;
882 cmd->header.size = sizeof(cmd->body) + so_target_size;
883 memcpy(&cmd[1], cbs->bind_cmd_buffer, so_target_size);
884
885 vmw_fifo_commit(ctx->dev_priv, cmd_size);
886
887 return 0;
888
889 }
890
891
892
893
894
895
896
897 static int vmw_binding_emit_dirty_ps(struct vmw_ctx_binding_state *cbs)
898 {
899 struct vmw_dx_shader_bindings *sb = &cbs->per_shader[0];
900 u32 i;
901 int ret;
902
903 for (i = 0; i < SVGA3D_NUM_SHADERTYPE_DX10; ++i, ++sb) {
904 if (!test_bit(VMW_BINDING_PS_SR_BIT, &sb->dirty))
905 continue;
906
907 ret = vmw_emit_set_sr(cbs, i);
908 if (ret)
909 break;
910
911 __clear_bit(VMW_BINDING_PS_SR_BIT, &sb->dirty);
912 }
913
914 return 0;
915 }
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932 static void vmw_collect_dirty_vbs(struct vmw_ctx_binding_state *cbs,
933 const struct vmw_ctx_bindinfo *bi,
934 unsigned long *dirty,
935 u32 max_num)
936 {
937 const struct vmw_ctx_bindinfo_vb *biv =
938 container_of(bi, struct vmw_ctx_bindinfo_vb, bi);
939 unsigned long i, next_bit;
940 SVGA3dVertexBuffer *vbs = (SVGA3dVertexBuffer *) &cbs->bind_cmd_buffer;
941
942 cbs->bind_cmd_count = 0;
943 i = find_first_bit(dirty, max_num);
944 next_bit = i;
945 cbs->bind_first_slot = i;
946
947 biv += i;
948 for (; i < max_num; ++i, ++biv, ++vbs) {
949 if (!biv->bi.ctx || biv->bi.scrubbed) {
950 vbs->sid = SVGA3D_INVALID_ID;
951 vbs->stride = 0;
952 vbs->offset = 0;
953 } else {
954 vbs->sid = biv->bi.res->id;
955 vbs->stride = biv->stride;
956 vbs->offset = biv->offset;
957 }
958 cbs->bind_cmd_count++;
959 if (next_bit == i) {
960 next_bit = find_next_bit(dirty, max_num, i + 1);
961 if (next_bit >= max_num)
962 break;
963 }
964 }
965 }
966
967
968
969
970
971
972
973 static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs)
974 {
975 const struct vmw_ctx_bindinfo *loc =
976 &cbs->vertex_buffers[0].bi;
977 struct {
978 SVGA3dCmdHeader header;
979 SVGA3dCmdDXSetVertexBuffers body;
980 } *cmd;
981 size_t cmd_size, set_vb_size;
982 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
983
984 vmw_collect_dirty_vbs(cbs, loc, cbs->dirty_vb,
985 SVGA3D_DX_MAX_VERTEXBUFFERS);
986 if (cbs->bind_cmd_count == 0)
987 return 0;
988
989 set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);
990 cmd_size = sizeof(*cmd) + set_vb_size;
991 cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
992 if (unlikely(cmd == NULL))
993 return -ENOMEM;
994
995 cmd->header.id = SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS;
996 cmd->header.size = sizeof(cmd->body) + set_vb_size;
997 cmd->body.startBuffer = cbs->bind_first_slot;
998
999 memcpy(&cmd[1], cbs->bind_cmd_buffer, set_vb_size);
1000
1001 vmw_fifo_commit(ctx->dev_priv, cmd_size);
1002 bitmap_clear(cbs->dirty_vb,
1003 cbs->bind_first_slot, cbs->bind_cmd_count);
1004
1005 return 0;
1006 }
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018 static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs)
1019 {
1020 int ret = 0;
1021 unsigned long hit = 0;
1022
1023 while ((hit = find_next_bit(&cbs->dirty, VMW_BINDING_NUM_BITS, hit))
1024 < VMW_BINDING_NUM_BITS) {
1025
1026 switch (hit) {
1027 case VMW_BINDING_RT_BIT:
1028 ret = vmw_emit_set_rt(cbs);
1029 break;
1030 case VMW_BINDING_PS_BIT:
1031 ret = vmw_binding_emit_dirty_ps(cbs);
1032 break;
1033 case VMW_BINDING_SO_BIT:
1034 ret = vmw_emit_set_so(cbs);
1035 break;
1036 case VMW_BINDING_VB_BIT:
1037 ret = vmw_emit_set_vb(cbs);
1038 break;
1039 default:
1040 BUG();
1041 }
1042 if (ret)
1043 return ret;
1044
1045 __clear_bit(hit, &cbs->dirty);
1046 hit++;
1047 }
1048
1049 return 0;
1050 }
1051
1052
1053
1054
1055
1056
1057
1058
1059 static int vmw_binding_scrub_sr(struct vmw_ctx_bindinfo *bi, bool rebind)
1060 {
1061 struct vmw_ctx_bindinfo_view *biv =
1062 container_of(bi, struct vmw_ctx_bindinfo_view, bi);
1063 struct vmw_ctx_binding_state *cbs =
1064 vmw_context_binding_state(bi->ctx);
1065
1066 __set_bit(biv->slot, cbs->per_shader[biv->shader_slot].dirty_sr);
1067 __set_bit(VMW_BINDING_PS_SR_BIT,
1068 &cbs->per_shader[biv->shader_slot].dirty);
1069 __set_bit(VMW_BINDING_PS_BIT, &cbs->dirty);
1070
1071 return 0;
1072 }
1073
1074
1075
1076
1077
1078
1079
1080
1081 static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind)
1082 {
1083 struct vmw_ctx_binding_state *cbs =
1084 vmw_context_binding_state(bi->ctx);
1085
1086 __set_bit(VMW_BINDING_RT_BIT, &cbs->dirty);
1087
1088 return 0;
1089 }
1090
1091
1092
1093
1094
1095
1096
1097
1098 static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind)
1099 {
1100 struct vmw_ctx_binding_state *cbs =
1101 vmw_context_binding_state(bi->ctx);
1102
1103 __set_bit(VMW_BINDING_SO_BIT, &cbs->dirty);
1104
1105 return 0;
1106 }
1107
1108
1109
1110
1111
1112
1113
1114
1115 static int vmw_binding_scrub_vb(struct vmw_ctx_bindinfo *bi, bool rebind)
1116 {
1117 struct vmw_ctx_bindinfo_vb *bivb =
1118 container_of(bi, struct vmw_ctx_bindinfo_vb, bi);
1119 struct vmw_ctx_binding_state *cbs =
1120 vmw_context_binding_state(bi->ctx);
1121
1122 __set_bit(bivb->slot, cbs->dirty_vb);
1123 __set_bit(VMW_BINDING_VB_BIT, &cbs->dirty);
1124
1125 return 0;
1126 }
1127
1128
1129
1130
1131
1132
1133
1134 static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind)
1135 {
1136 struct vmw_ctx_bindinfo_ib *binding =
1137 container_of(bi, typeof(*binding), bi);
1138 struct vmw_private *dev_priv = bi->ctx->dev_priv;
1139 struct {
1140 SVGA3dCmdHeader header;
1141 SVGA3dCmdDXSetIndexBuffer body;
1142 } *cmd;
1143
1144 cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
1145 if (unlikely(cmd == NULL))
1146 return -ENOMEM;
1147
1148 cmd->header.id = SVGA_3D_CMD_DX_SET_INDEX_BUFFER;
1149 cmd->header.size = sizeof(cmd->body);
1150 if (rebind) {
1151 cmd->body.sid = bi->res->id;
1152 cmd->body.format = binding->format;
1153 cmd->body.offset = binding->offset;
1154 } else {
1155 cmd->body.sid = SVGA3D_INVALID_ID;
1156 cmd->body.format = 0;
1157 cmd->body.offset = 0;
1158 }
1159
1160 vmw_fifo_commit(dev_priv, sizeof(*cmd));
1161
1162 return 0;
1163 }
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173 struct vmw_ctx_binding_state *
1174 vmw_binding_state_alloc(struct vmw_private *dev_priv)
1175 {
1176 struct vmw_ctx_binding_state *cbs;
1177 struct ttm_operation_ctx ctx = {
1178 .interruptible = false,
1179 .no_wait_gpu = false
1180 };
1181 int ret;
1182
1183 ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), sizeof(*cbs),
1184 &ctx);
1185 if (ret)
1186 return ERR_PTR(ret);
1187
1188 cbs = vzalloc(sizeof(*cbs));
1189 if (!cbs) {
1190 ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs));
1191 return ERR_PTR(-ENOMEM);
1192 }
1193
1194 cbs->dev_priv = dev_priv;
1195 INIT_LIST_HEAD(&cbs->list);
1196
1197 return cbs;
1198 }
1199
1200
1201
1202
1203
1204
1205
1206 void vmw_binding_state_free(struct vmw_ctx_binding_state *cbs)
1207 {
1208 struct vmw_private *dev_priv = cbs->dev_priv;
1209
1210 vfree(cbs);
1211 ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs));
1212 }
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223 struct list_head *vmw_binding_state_list(struct vmw_ctx_binding_state *cbs)
1224 {
1225 return &cbs->list;
1226 }
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236 void vmw_binding_state_reset(struct vmw_ctx_binding_state *cbs)
1237 {
1238 struct vmw_ctx_bindinfo *entry, *next;
1239
1240 list_for_each_entry_safe(entry, next, &cbs->list, ctx_list)
1241 vmw_binding_drop(entry);
1242 }
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256 u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
1257 {
1258 static u32 is_binding_dirtying[vmw_ctx_binding_max] = {
1259 [vmw_ctx_binding_rt] = VMW_RES_DIRTY_SET,
1260 [vmw_ctx_binding_dx_rt] = VMW_RES_DIRTY_SET,
1261 [vmw_ctx_binding_ds] = VMW_RES_DIRTY_SET,
1262 [vmw_ctx_binding_so] = VMW_RES_DIRTY_SET,
1263 };
1264
1265
1266 BUILD_BUG_ON(vmw_ctx_binding_max != 11);
1267 return is_binding_dirtying[binding_type];
1268 }
1269
1270
1271
1272
1273
1274 static void vmw_binding_build_asserts(void)
1275 {
1276 BUILD_BUG_ON(SVGA3D_NUM_SHADERTYPE_DX10 != 3);
1277 BUILD_BUG_ON(SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS > SVGA3D_RT_MAX);
1278 BUILD_BUG_ON(sizeof(uint32) != sizeof(u32));
1279
1280
1281
1282
1283
1284 BUILD_BUG_ON(VMW_MAX_VIEW_BINDINGS < SVGA3D_RT_MAX);
1285 BUILD_BUG_ON(VMW_MAX_VIEW_BINDINGS < SVGA3D_DX_MAX_SRVIEWS);
1286 BUILD_BUG_ON(VMW_MAX_VIEW_BINDINGS < SVGA3D_DX_MAX_CONSTBUFFERS);
1287
1288
1289
1290
1291
1292 BUILD_BUG_ON(SVGA3D_DX_MAX_SOTARGETS*sizeof(SVGA3dSoTarget) >
1293 VMW_MAX_VIEW_BINDINGS*sizeof(u32));
1294 BUILD_BUG_ON(SVGA3D_DX_MAX_VERTEXBUFFERS*sizeof(SVGA3dVertexBuffer) >
1295 VMW_MAX_VIEW_BINDINGS*sizeof(u32));
1296 }