1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4 * Author: James.Qian.Wang <james.qian.wang@arm.com>
5 *
6 */
7 #ifndef _KOMEDA_DEV_H_
8 #define _KOMEDA_DEV_H_
9
10 #include <linux/device.h>
11 #include <linux/clk.h>
12 #include "komeda_pipeline.h"
13 #include "malidp_product.h"
14 #include "komeda_format_caps.h"
15
16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23
24 #define KOMEDA_ERR_TETO BIT_ULL(14)
25 #define KOMEDA_ERR_TEMR BIT_ULL(15)
26 #define KOMEDA_ERR_TITR BIT_ULL(16)
27 #define KOMEDA_ERR_CPE BIT_ULL(17)
28 #define KOMEDA_ERR_CFGE BIT_ULL(18)
29 #define KOMEDA_ERR_AXIE BIT_ULL(19)
30 #define KOMEDA_ERR_ACE0 BIT_ULL(20)
31 #define KOMEDA_ERR_ACE1 BIT_ULL(21)
32 #define KOMEDA_ERR_ACE2 BIT_ULL(22)
33 #define KOMEDA_ERR_ACE3 BIT_ULL(23)
34 #define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
35 #define KOMEDA_ERR_FRAMETO BIT_ULL(25)
36 #define KOMEDA_ERR_CSCE BIT_ULL(26)
37 #define KOMEDA_ERR_ZME BIT_ULL(27)
38 #define KOMEDA_ERR_MERR BIT_ULL(28)
39 #define KOMEDA_ERR_TCF BIT_ULL(29)
40 #define KOMEDA_ERR_TTNG BIT_ULL(30)
41 #define KOMEDA_ERR_TTF BIT_ULL(31)
42
43 /* malidp device id */
44 enum {
45 MALI_D71 = 0,
46 };
47
48 /* pipeline DT ports */
49 enum {
50 KOMEDA_OF_PORT_OUTPUT = 0,
51 KOMEDA_OF_PORT_COPROC = 1,
52 };
53
54 struct komeda_chip_info {
55 u32 arch_id;
56 u32 core_id;
57 u32 core_info;
58 u32 bus_width;
59 };
60
61 struct komeda_product_data {
62 u32 product_id;
63 const struct komeda_dev_funcs *(*identify)(u32 __iomem *reg,
64 struct komeda_chip_info *info);
65 };
66
67 struct komeda_dev;
68
69 struct komeda_events {
70 u64 global;
71 u64 pipes[KOMEDA_MAX_PIPELINES];
72 };
73
74 /**
75 * struct komeda_dev_funcs
76 *
77 * Supplied by chip level and returned by the chip entry function xxx_identify,
78 */
79 struct komeda_dev_funcs {
80 /**
81 * @init_format_table:
82 *
83 * initialize &komeda_dev->format_table, this function should be called
84 * before the &enum_resource
85 */
86 void (*init_format_table)(struct komeda_dev *mdev);
87 /**
88 * @enum_resources:
89 *
90 * for CHIP to report or add pipeline and component resources to CORE
91 */
92 int (*enum_resources)(struct komeda_dev *mdev);
93 /** @cleanup: call to chip to cleanup komeda_dev->chip data */
94 void (*cleanup)(struct komeda_dev *mdev);
95 /** @connect_iommu: Optional, connect to external iommu */
96 int (*connect_iommu)(struct komeda_dev *mdev);
97 /** @disconnect_iommu: Optional, disconnect to external iommu */
98 int (*disconnect_iommu)(struct komeda_dev *mdev);
99 /**
100 * @irq_handler:
101 *
102 * for CORE to get the HW event from the CHIP when interrupt happened.
103 */
104 irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
105 struct komeda_events *events);
106 /** @enable_irq: enable irq */
107 int (*enable_irq)(struct komeda_dev *mdev);
108 /** @disable_irq: disable irq */
109 int (*disable_irq)(struct komeda_dev *mdev);
110 /** @on_off_vblank: notify HW to on/off vblank */
111 void (*on_off_vblank)(struct komeda_dev *mdev,
112 int master_pipe, bool on);
113
114 /** @dump_register: Optional, dump registers to seq_file */
115 void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
116 /**
117 * @change_opmode:
118 *
119 * Notify HW to switch to a new display operation mode.
120 */
121 int (*change_opmode)(struct komeda_dev *mdev, int new_mode);
122 /** @flush: Notify the HW to flush or kickoff the update */
123 void (*flush)(struct komeda_dev *mdev,
124 int master_pipe, u32 active_pipes);
125 };
126
127 /*
128 * DISPLAY_MODE describes how many display been enabled, and which will be
129 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
130 * pipeline resources assignment according to this usage hint.
131 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
132 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
133 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
134 * And D71 supports assign two pipelines to one single display on mode
135 * KOMEDA_MODE_DISP0/DISP1
136 */
137 enum {
138 KOMEDA_MODE_INACTIVE = 0,
139 KOMEDA_MODE_DISP0 = BIT(0),
140 KOMEDA_MODE_DISP1 = BIT(1),
141 KOMEDA_MODE_DUAL_DISP = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,
142 };
143
144 /**
145 * struct komeda_dev
146 *
147 * Pipeline and component are used to describe how to handle the pixel data.
148 * komeda_device is for describing the whole view of the device, and the
149 * control-abilites of device.
150 */
151 struct komeda_dev {
152 /** @dev: the base device structure */
153 struct device *dev;
154 /** @reg_base: the base address of komeda io space */
155 u32 __iomem *reg_base;
156 /** @dma_parms: the dma parameters of komeda */
157 struct device_dma_parameters dma_parms;
158
159 /** @chip: the basic chip information */
160 struct komeda_chip_info chip;
161 /** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
162 struct komeda_format_caps_table fmt_tbl;
163 /** @aclk: HW main engine clk */
164 struct clk *aclk;
165
166 /** @irq: irq number */
167 int irq;
168
169 /** @lock: used to protect dpmode */
170 struct mutex lock;
171 /** @dpmode: current display mode */
172 u32 dpmode;
173
174 /** @n_pipelines: the number of pipe in @pipelines */
175 int n_pipelines;
176 /** @pipelines: the komeda pipelines */
177 struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
178
179 /** @funcs: chip funcs to access to HW */
180 const struct komeda_dev_funcs *funcs;
181 /**
182 * @chip_data:
183 *
184 * chip data will be added by &komeda_dev_funcs.enum_resources() and
185 * destroyed by &komeda_dev_funcs.cleanup()
186 */
187 void *chip_data;
188
189 /** @iommu: iommu domain */
190 struct iommu_domain *iommu;
191
192 /** @debugfs_root: root directory of komeda debugfs */
193 struct dentry *debugfs_root;
194 };
195
196 static inline bool
197 komeda_product_match(struct komeda_dev *mdev, u32 target)
198 {
199 return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
200 }
201
202 const struct komeda_dev_funcs *
203 d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
204
205 struct komeda_dev *komeda_dev_create(struct device *dev);
206 void komeda_dev_destroy(struct komeda_dev *mdev);
207
208 struct komeda_dev *dev_to_mdev(struct device *dev);
209
210 #endif /*_KOMEDA_DEV_H_*/