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24 #ifndef CIK_H
25 #define CIK_H
26
27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
29
30 #define CIK_RB_BITMAP_WIDTH_PER_SH 2
31 #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
32
33
34 #define DIDT_SQ_CTRL0 0x0
35 # define DIDT_CTRL_EN (1 << 0)
36 #define DIDT_DB_CTRL0 0x20
37 #define DIDT_TD_CTRL0 0x40
38 #define DIDT_TCP_CTRL0 0x60
39
40
41 #define DPM_TABLE_475 0x3F768
42 # define SamuBootLevel(x) ((x) << 0)
43 # define SamuBootLevel_MASK 0x000000ff
44 # define SamuBootLevel_SHIFT 0
45 # define AcpBootLevel(x) ((x) << 8)
46 # define AcpBootLevel_MASK 0x0000ff00
47 # define AcpBootLevel_SHIFT 8
48 # define VceBootLevel(x) ((x) << 16)
49 # define VceBootLevel_MASK 0x00ff0000
50 # define VceBootLevel_SHIFT 16
51 # define UvdBootLevel(x) ((x) << 24)
52 # define UvdBootLevel_MASK 0xff000000
53 # define UvdBootLevel_SHIFT 24
54
55 #define FIRMWARE_FLAGS 0x3F800
56 # define INTERRUPTS_ENABLED (1 << 0)
57
58 #define NB_DPM_CONFIG_1 0x3F9E8
59 # define Dpm0PgNbPsLo(x) ((x) << 0)
60 # define Dpm0PgNbPsLo_MASK 0x000000ff
61 # define Dpm0PgNbPsLo_SHIFT 0
62 # define Dpm0PgNbPsHi(x) ((x) << 8)
63 # define Dpm0PgNbPsHi_MASK 0x0000ff00
64 # define Dpm0PgNbPsHi_SHIFT 8
65 # define DpmXNbPsLo(x) ((x) << 16)
66 # define DpmXNbPsLo_MASK 0x00ff0000
67 # define DpmXNbPsLo_SHIFT 16
68 # define DpmXNbPsHi(x) ((x) << 24)
69 # define DpmXNbPsHi_MASK 0xff000000
70 # define DpmXNbPsHi_SHIFT 24
71
72 #define SMC_SYSCON_RESET_CNTL 0x80000000
73 # define RST_REG (1 << 0)
74 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
75 # define CK_DISABLE (1 << 0)
76 # define CKEN (1 << 24)
77
78 #define SMC_SYSCON_MISC_CNTL 0x80000010
79
80 #define SMC_SYSCON_MSG_ARG_0 0x80000068
81
82 #define SMC_PC_C 0x80000370
83
84 #define SMC_SCRATCH9 0x80000424
85
86 #define RCU_UC_EVENTS 0xC0000004
87 # define BOOT_SEQ_DONE (1 << 7)
88
89 #define GENERAL_PWRMGT 0xC0200000
90 # define GLOBAL_PWRMGT_EN (1 << 0)
91 # define STATIC_PM_EN (1 << 1)
92 # define THERMAL_PROTECTION_DIS (1 << 2)
93 # define THERMAL_PROTECTION_TYPE (1 << 3)
94 # define SW_SMIO_INDEX(x) ((x) << 6)
95 # define SW_SMIO_INDEX_MASK (1 << 6)
96 # define SW_SMIO_INDEX_SHIFT 6
97 # define VOLT_PWRMGT_EN (1 << 10)
98 # define GPU_COUNTER_CLK (1 << 15)
99 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
100
101 #define CNB_PWRMGT_CNTL 0xC0200004
102 # define GNB_SLOW_MODE(x) ((x) << 0)
103 # define GNB_SLOW_MODE_MASK (3 << 0)
104 # define GNB_SLOW_MODE_SHIFT 0
105 # define GNB_SLOW (1 << 2)
106 # define FORCE_NB_PS1 (1 << 3)
107 # define DPM_ENABLED (1 << 4)
108
109 #define SCLK_PWRMGT_CNTL 0xC0200008
110 # define SCLK_PWRMGT_OFF (1 << 0)
111 # define RESET_BUSY_CNT (1 << 4)
112 # define RESET_SCLK_CNT (1 << 5)
113 # define DYNAMIC_PM_EN (1 << 21)
114
115 #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014
116 # define CURRENT_STATE_MASK (0xf << 4)
117 # define CURRENT_STATE_SHIFT 4
118 # define CURR_MCLK_INDEX_MASK (0xf << 8)
119 # define CURR_MCLK_INDEX_SHIFT 8
120 # define CURR_SCLK_INDEX_MASK (0x1f << 16)
121 # define CURR_SCLK_INDEX_SHIFT 16
122
123 #define CG_SSP 0xC0200044
124 # define SST(x) ((x) << 0)
125 # define SST_MASK (0xffff << 0)
126 # define SSTU(x) ((x) << 16)
127 # define SSTU_MASK (0xf << 16)
128
129 #define CG_DISPLAY_GAP_CNTL 0xC0200060
130 # define DISP_GAP(x) ((x) << 0)
131 # define DISP_GAP_MASK (3 << 0)
132 # define VBI_TIMER_COUNT(x) ((x) << 4)
133 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
134 # define VBI_TIMER_UNIT(x) ((x) << 20)
135 # define VBI_TIMER_UNIT_MASK (7 << 20)
136 # define DISP_GAP_MCHG(x) ((x) << 24)
137 # define DISP_GAP_MCHG_MASK (3 << 24)
138
139 #define SMU_VOLTAGE_STATUS 0xC0200094
140 # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
141 # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
142
143 #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0
144 # define CURR_PCIE_INDEX_MASK (0xf << 24)
145 # define CURR_PCIE_INDEX_SHIFT 24
146
147 #define CG_ULV_PARAMETER 0xC0200158
148
149 #define CG_FTV_0 0xC02001A8
150 #define CG_FTV_1 0xC02001AC
151 #define CG_FTV_2 0xC02001B0
152 #define CG_FTV_3 0xC02001B4
153 #define CG_FTV_4 0xC02001B8
154 #define CG_FTV_5 0xC02001BC
155 #define CG_FTV_6 0xC02001C0
156 #define CG_FTV_7 0xC02001C4
157
158 #define CG_DISPLAY_GAP_CNTL2 0xC0200230
159
160 #define LCAC_SX0_OVR_SEL 0xC0400D04
161 #define LCAC_SX0_OVR_VAL 0xC0400D08
162
163 #define LCAC_MC0_CNTL 0xC0400D30
164 #define LCAC_MC0_OVR_SEL 0xC0400D34
165 #define LCAC_MC0_OVR_VAL 0xC0400D38
166 #define LCAC_MC1_CNTL 0xC0400D3C
167 #define LCAC_MC1_OVR_SEL 0xC0400D40
168 #define LCAC_MC1_OVR_VAL 0xC0400D44
169
170 #define LCAC_MC2_OVR_SEL 0xC0400D4C
171 #define LCAC_MC2_OVR_VAL 0xC0400D50
172
173 #define LCAC_MC3_OVR_SEL 0xC0400D58
174 #define LCAC_MC3_OVR_VAL 0xC0400D5C
175
176 #define LCAC_CPL_CNTL 0xC0400D80
177 #define LCAC_CPL_OVR_SEL 0xC0400D84
178 #define LCAC_CPL_OVR_VAL 0xC0400D88
179
180
181 #define CG_THERMAL_CTRL 0xC0300004
182 #define DPM_EVENT_SRC(x) ((x) << 0)
183 #define DPM_EVENT_SRC_MASK (7 << 0)
184 #define DIG_THERM_DPM(x) ((x) << 14)
185 #define DIG_THERM_DPM_MASK 0x003FC000
186 #define DIG_THERM_DPM_SHIFT 14
187 #define CG_THERMAL_STATUS 0xC0300008
188 #define FDO_PWM_DUTY(x) ((x) << 9)
189 #define FDO_PWM_DUTY_MASK (0xff << 9)
190 #define FDO_PWM_DUTY_SHIFT 9
191 #define CG_THERMAL_INT 0xC030000C
192 #define CI_DIG_THERM_INTH(x) ((x) << 8)
193 #define CI_DIG_THERM_INTH_MASK 0x0000FF00
194 #define CI_DIG_THERM_INTH_SHIFT 8
195 #define CI_DIG_THERM_INTL(x) ((x) << 16)
196 #define CI_DIG_THERM_INTL_MASK 0x00FF0000
197 #define CI_DIG_THERM_INTL_SHIFT 16
198 #define THERM_INT_MASK_HIGH (1 << 24)
199 #define THERM_INT_MASK_LOW (1 << 25)
200 #define CG_MULT_THERMAL_CTRL 0xC0300010
201 #define TEMP_SEL(x) ((x) << 20)
202 #define TEMP_SEL_MASK (0xff << 20)
203 #define TEMP_SEL_SHIFT 20
204 #define CG_MULT_THERMAL_STATUS 0xC0300014
205 #define ASIC_MAX_TEMP(x) ((x) << 0)
206 #define ASIC_MAX_TEMP_MASK 0x000001ff
207 #define ASIC_MAX_TEMP_SHIFT 0
208 #define CTF_TEMP(x) ((x) << 9)
209 #define CTF_TEMP_MASK 0x0003fe00
210 #define CTF_TEMP_SHIFT 9
211
212 #define CG_FDO_CTRL0 0xC0300064
213 #define FDO_STATIC_DUTY(x) ((x) << 0)
214 #define FDO_STATIC_DUTY_MASK 0x000000FF
215 #define FDO_STATIC_DUTY_SHIFT 0
216 #define CG_FDO_CTRL1 0xC0300068
217 #define FMAX_DUTY100(x) ((x) << 0)
218 #define FMAX_DUTY100_MASK 0x000000FF
219 #define FMAX_DUTY100_SHIFT 0
220 #define CG_FDO_CTRL2 0xC030006C
221 #define TMIN(x) ((x) << 0)
222 #define TMIN_MASK 0x000000FF
223 #define TMIN_SHIFT 0
224 #define FDO_PWM_MODE(x) ((x) << 11)
225 #define FDO_PWM_MODE_MASK (7 << 11)
226 #define FDO_PWM_MODE_SHIFT 11
227 #define TACH_PWM_RESP_RATE(x) ((x) << 25)
228 #define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
229 #define TACH_PWM_RESP_RATE_SHIFT 25
230 #define CG_TACH_CTRL 0xC0300070
231 # define EDGE_PER_REV(x) ((x) << 0)
232 # define EDGE_PER_REV_MASK (0x7 << 0)
233 # define EDGE_PER_REV_SHIFT 0
234 # define TARGET_PERIOD(x) ((x) << 3)
235 # define TARGET_PERIOD_MASK 0xfffffff8
236 # define TARGET_PERIOD_SHIFT 3
237 #define CG_TACH_STATUS 0xC0300074
238 # define TACH_PERIOD(x) ((x) << 0)
239 # define TACH_PERIOD_MASK 0xffffffff
240 # define TACH_PERIOD_SHIFT 0
241
242 #define CG_ECLK_CNTL 0xC05000AC
243 # define ECLK_DIVIDER_MASK 0x7f
244 # define ECLK_DIR_CNTL_EN (1 << 8)
245 #define CG_ECLK_STATUS 0xC05000B0
246 # define ECLK_STATUS (1 << 0)
247
248 #define CG_SPLL_FUNC_CNTL 0xC0500140
249 #define SPLL_RESET (1 << 0)
250 #define SPLL_PWRON (1 << 1)
251 #define SPLL_BYPASS_EN (1 << 3)
252 #define SPLL_REF_DIV(x) ((x) << 5)
253 #define SPLL_REF_DIV_MASK (0x3f << 5)
254 #define SPLL_PDIV_A(x) ((x) << 20)
255 #define SPLL_PDIV_A_MASK (0x7f << 20)
256 #define SPLL_PDIV_A_SHIFT 20
257 #define CG_SPLL_FUNC_CNTL_2 0xC0500144
258 #define SCLK_MUX_SEL(x) ((x) << 0)
259 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
260 #define CG_SPLL_FUNC_CNTL_3 0xC0500148
261 #define SPLL_FB_DIV(x) ((x) << 0)
262 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
263 #define SPLL_FB_DIV_SHIFT 0
264 #define SPLL_DITHEN (1 << 28)
265 #define CG_SPLL_FUNC_CNTL_4 0xC050014C
266
267 #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
268 #define SSEN (1 << 0)
269 #define CLK_S(x) ((x) << 4)
270 #define CLK_S_MASK (0xfff << 4)
271 #define CLK_S_SHIFT 4
272 #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
273 #define CLK_V(x) ((x) << 0)
274 #define CLK_V_MASK (0x3ffffff << 0)
275 #define CLK_V_SHIFT 0
276
277 #define MPLL_BYPASSCLK_SEL 0xC050019C
278 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
279 # define MPLL_CLKOUT_SEL_MASK 0xFF00
280 #define CG_CLKPIN_CNTL 0xC05001A0
281 # define XTALIN_DIVIDE (1 << 1)
282 # define BCLK_AS_XCLK (1 << 2)
283 #define CG_CLKPIN_CNTL_2 0xC05001A4
284 # define FORCE_BIF_REFCLK_EN (1 << 3)
285 # define MUX_TCLK_TO_XCLK (1 << 8)
286 #define THM_CLK_CNTL 0xC05001A8
287 # define CMON_CLK_SEL(x) ((x) << 0)
288 # define CMON_CLK_SEL_MASK 0xFF
289 # define TMON_CLK_SEL(x) ((x) << 8)
290 # define TMON_CLK_SEL_MASK 0xFF00
291 #define MISC_CLK_CTRL 0xC05001AC
292 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
293 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
294 # define ZCLK_SEL(x) ((x) << 8)
295 # define ZCLK_SEL_MASK 0xFF00
296
297
298 #define CG_THERMAL_INT_CTRL 0xC2100028
299 #define DIG_THERM_INTH(x) ((x) << 0)
300 #define DIG_THERM_INTH_MASK 0x000000FF
301 #define DIG_THERM_INTH_SHIFT 0
302 #define DIG_THERM_INTL(x) ((x) << 8)
303 #define DIG_THERM_INTL_MASK 0x0000FF00
304 #define DIG_THERM_INTL_SHIFT 8
305 #define THERM_INTH_MASK (1 << 24)
306 #define THERM_INTL_MASK (1 << 25)
307
308
309 #define PB0_PIF_PWRDOWN_0 0x1100012
310 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
311 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
312 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
313 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
314 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
315 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
316 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
317 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
318 # define PLL_RAMP_UP_TIME_0_SHIFT 24
319 #define PB0_PIF_PWRDOWN_1 0x1100013
320 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
321 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
322 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
323 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
324 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
325 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
326 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
327 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
328 # define PLL_RAMP_UP_TIME_1_SHIFT 24
329
330 #define PCIE_CNTL2 0x1001001c
331 # define SLV_MEM_LS_EN (1 << 16)
332 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
333 # define MST_MEM_LS_EN (1 << 18)
334 # define REPLAY_MEM_LS_EN (1 << 19)
335
336 #define PCIE_LC_STATUS1 0x1400028
337 # define LC_REVERSE_RCVR (1 << 0)
338 # define LC_REVERSE_XMIT (1 << 1)
339 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
340 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
341 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
342 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
343
344 #define PCIE_P_CNTL 0x1400040
345 # define P_IGNORE_EDB_ERR (1 << 6)
346
347 #define PB1_PIF_PWRDOWN_0 0x2100012
348 #define PB1_PIF_PWRDOWN_1 0x2100013
349
350 #define PCIE_LC_CNTL 0x100100A0
351 # define LC_L0S_INACTIVITY(x) ((x) << 8)
352 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
353 # define LC_L0S_INACTIVITY_SHIFT 8
354 # define LC_L1_INACTIVITY(x) ((x) << 12)
355 # define LC_L1_INACTIVITY_MASK (0xf << 12)
356 # define LC_L1_INACTIVITY_SHIFT 12
357 # define LC_PMI_TO_L1_DIS (1 << 16)
358 # define LC_ASPM_TO_L1_DIS (1 << 24)
359
360 #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2
361 # define LC_LINK_WIDTH_SHIFT 0
362 # define LC_LINK_WIDTH_MASK 0x7
363 # define LC_LINK_WIDTH_X0 0
364 # define LC_LINK_WIDTH_X1 1
365 # define LC_LINK_WIDTH_X2 2
366 # define LC_LINK_WIDTH_X4 3
367 # define LC_LINK_WIDTH_X8 4
368 # define LC_LINK_WIDTH_X16 6
369 # define LC_LINK_WIDTH_RD_SHIFT 4
370 # define LC_LINK_WIDTH_RD_MASK 0x70
371 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
372 # define LC_RECONFIG_NOW (1 << 8)
373 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
374 # define LC_RENEGOTIATE_EN (1 << 10)
375 # define LC_SHORT_RECONFIG_EN (1 << 11)
376 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
377 # define LC_UPCONFIGURE_DIS (1 << 13)
378 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
379 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
380 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
381 #define PCIE_LC_N_FTS_CNTL 0x100100a3
382 # define LC_XMIT_N_FTS(x) ((x) << 0)
383 # define LC_XMIT_N_FTS_MASK (0xff << 0)
384 # define LC_XMIT_N_FTS_SHIFT 0
385 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
386 # define LC_N_FTS_MASK (0xff << 24)
387 #define PCIE_LC_SPEED_CNTL 0x100100A4
388 # define LC_GEN2_EN_STRAP (1 << 0)
389 # define LC_GEN3_EN_STRAP (1 << 1)
390 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
391 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
392 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
393 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
394 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
395 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
396 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
397 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
398 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
399 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
400 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13)
401 # define LC_CURRENT_DATA_RATE_SHIFT 13
402 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
403 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
404 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
405 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
406 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
407
408 #define PCIE_LC_CNTL2 0x100100B1
409 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
410 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
411
412 #define PCIE_LC_CNTL3 0x100100B5
413 # define LC_GO_TO_RECOVERY (1 << 30)
414 #define PCIE_LC_CNTL4 0x100100B6
415 # define LC_REDO_EQ (1 << 5)
416 # define LC_SET_QUIESCE (1 << 13)
417
418
419 #define PCIE_INDEX 0x38
420 #define PCIE_DATA 0x3C
421
422 #define SMC_IND_INDEX_0 0x200
423 #define SMC_IND_DATA_0 0x204
424
425 #define SMC_IND_ACCESS_CNTL 0x240
426 #define AUTO_INCREMENT_IND_0 (1 << 0)
427
428 #define SMC_MESSAGE_0 0x250
429 #define SMC_MSG_MASK 0xffff
430 #define SMC_RESP_0 0x254
431 #define SMC_RESP_MASK 0xffff
432
433 #define SMC_MSG_ARG_0 0x290
434
435 #define VGA_HDP_CONTROL 0x328
436 #define VGA_MEMORY_DISABLE (1 << 4)
437
438 #define DMIF_ADDR_CALC 0xC00
439
440 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
441 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
442 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
443
444 #define SRBM_GFX_CNTL 0xE44
445 #define PIPEID(x) ((x) << 0)
446 #define MEID(x) ((x) << 2)
447 #define VMID(x) ((x) << 4)
448 #define QUEUEID(x) ((x) << 8)
449
450 #define SRBM_STATUS2 0xE4C
451 #define SDMA_BUSY (1 << 5)
452 #define SDMA1_BUSY (1 << 6)
453 #define SRBM_STATUS 0xE50
454 #define UVD_RQ_PENDING (1 << 1)
455 #define GRBM_RQ_PENDING (1 << 5)
456 #define VMC_BUSY (1 << 8)
457 #define MCB_BUSY (1 << 9)
458 #define MCB_NON_DISPLAY_BUSY (1 << 10)
459 #define MCC_BUSY (1 << 11)
460 #define MCD_BUSY (1 << 12)
461 #define SEM_BUSY (1 << 14)
462 #define IH_BUSY (1 << 17)
463 #define UVD_BUSY (1 << 19)
464
465 #define SRBM_SOFT_RESET 0xE60
466 #define SOFT_RESET_BIF (1 << 1)
467 #define SOFT_RESET_R0PLL (1 << 4)
468 #define SOFT_RESET_DC (1 << 5)
469 #define SOFT_RESET_SDMA1 (1 << 6)
470 #define SOFT_RESET_GRBM (1 << 8)
471 #define SOFT_RESET_HDP (1 << 9)
472 #define SOFT_RESET_IH (1 << 10)
473 #define SOFT_RESET_MC (1 << 11)
474 #define SOFT_RESET_ROM (1 << 14)
475 #define SOFT_RESET_SEM (1 << 15)
476 #define SOFT_RESET_VMC (1 << 17)
477 #define SOFT_RESET_SDMA (1 << 20)
478 #define SOFT_RESET_TST (1 << 21)
479 #define SOFT_RESET_REGBB (1 << 22)
480 #define SOFT_RESET_ORB (1 << 23)
481 #define SOFT_RESET_VCE (1 << 24)
482
483 #define SRBM_READ_ERROR 0xE98
484 #define SRBM_INT_CNTL 0xEA0
485 #define SRBM_INT_ACK 0xEA8
486
487 #define VM_L2_CNTL 0x1400
488 #define ENABLE_L2_CACHE (1 << 0)
489 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
490 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
491 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
492 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
494 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
495 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
496 #define VM_L2_CNTL2 0x1404
497 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
498 #define INVALIDATE_L2_CACHE (1 << 1)
499 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
500 #define INVALIDATE_PTE_AND_PDE_CACHES 0
501 #define INVALIDATE_ONLY_PTE_CACHES 1
502 #define INVALIDATE_ONLY_PDE_CACHES 2
503 #define VM_L2_CNTL3 0x1408
504 #define BANK_SELECT(x) ((x) << 0)
505 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
506 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
507 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
508 #define VM_L2_STATUS 0x140C
509 #define L2_BUSY (1 << 0)
510 #define VM_CONTEXT0_CNTL 0x1410
511 #define ENABLE_CONTEXT (1 << 0)
512 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
513 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
514 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
515 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
516 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
517 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
518 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
519 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
520 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
521 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
522 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
523 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
524 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
525 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
526 #define VM_CONTEXT1_CNTL 0x1414
527 #define VM_CONTEXT0_CNTL2 0x1430
528 #define VM_CONTEXT1_CNTL2 0x1434
529 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
530 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
531 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
532 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
533 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
534 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
535 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
536 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
537
538 #define VM_INVALIDATE_REQUEST 0x1478
539 #define VM_INVALIDATE_RESPONSE 0x147c
540
541 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
542 #define PROTECTIONS_MASK (0xf << 0)
543 #define PROTECTIONS_SHIFT 0
544
545
546
547
548
549
550 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
551 #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)
552 #define MEMORY_CLIENT_ID_SHIFT 12
553 #define MEMORY_CLIENT_RW_MASK (1 << 24)
554 #define MEMORY_CLIENT_RW_SHIFT 24
555 #define FAULT_VMID_MASK (0xf << 25)
556 #define FAULT_VMID_SHIFT 25
557
558 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
559
560 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
561
562 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
563 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
564
565 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
566 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
567 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
568 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
569 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
570 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
571 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
572 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
573 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
574 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
575
576 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
577 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
578
579 #define VM_L2_CG 0x15c0
580 #define MC_CG_ENABLE (1 << 18)
581 #define MC_LS_ENABLE (1 << 19)
582
583 #define MC_SHARED_CHMAP 0x2004
584 #define NOOFCHAN_SHIFT 12
585 #define NOOFCHAN_MASK 0x0000f000
586 #define MC_SHARED_CHREMAP 0x2008
587
588 #define CHUB_CONTROL 0x1864
589 #define BYPASS_VM (1 << 0)
590
591 #define MC_VM_FB_LOCATION 0x2024
592 #define MC_VM_AGP_TOP 0x2028
593 #define MC_VM_AGP_BOT 0x202C
594 #define MC_VM_AGP_BASE 0x2030
595 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
596 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
597 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
598
599 #define MC_VM_MX_L1_TLB_CNTL 0x2064
600 #define ENABLE_L1_TLB (1 << 0)
601 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
602 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
603 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
604 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
605 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
606 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
607 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
608 #define MC_VM_FB_OFFSET 0x2068
609
610 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
611
612 #define MC_HUB_MISC_HUB_CG 0x20b8
613 #define MC_HUB_MISC_VM_CG 0x20bc
614
615 #define MC_HUB_MISC_SIP_CG 0x20c0
616
617 #define MC_XPB_CLK_GAT 0x2478
618
619 #define MC_CITF_MISC_RD_CG 0x2648
620 #define MC_CITF_MISC_WR_CG 0x264c
621 #define MC_CITF_MISC_VM_CG 0x2650
622
623 #define MC_ARB_RAMCFG 0x2760
624 #define NOOFBANK_SHIFT 0
625 #define NOOFBANK_MASK 0x00000003
626 #define NOOFRANK_SHIFT 2
627 #define NOOFRANK_MASK 0x00000004
628 #define NOOFROWS_SHIFT 3
629 #define NOOFROWS_MASK 0x00000038
630 #define NOOFCOLS_SHIFT 6
631 #define NOOFCOLS_MASK 0x000000C0
632 #define CHANSIZE_SHIFT 8
633 #define CHANSIZE_MASK 0x00000100
634 #define NOOFGROUPS_SHIFT 12
635 #define NOOFGROUPS_MASK 0x00001000
636
637 #define MC_ARB_DRAM_TIMING 0x2774
638 #define MC_ARB_DRAM_TIMING2 0x2778
639
640 #define MC_ARB_BURST_TIME 0x2808
641 #define STATE0(x) ((x) << 0)
642 #define STATE0_MASK (0x1f << 0)
643 #define STATE0_SHIFT 0
644 #define STATE1(x) ((x) << 5)
645 #define STATE1_MASK (0x1f << 5)
646 #define STATE1_SHIFT 5
647 #define STATE2(x) ((x) << 10)
648 #define STATE2_MASK (0x1f << 10)
649 #define STATE2_SHIFT 10
650 #define STATE3(x) ((x) << 15)
651 #define STATE3_MASK (0x1f << 15)
652 #define STATE3_SHIFT 15
653
654 #define MC_SEQ_RAS_TIMING 0x28a0
655 #define MC_SEQ_CAS_TIMING 0x28a4
656 #define MC_SEQ_MISC_TIMING 0x28a8
657 #define MC_SEQ_MISC_TIMING2 0x28ac
658 #define MC_SEQ_PMG_TIMING 0x28b0
659 #define MC_SEQ_RD_CTL_D0 0x28b4
660 #define MC_SEQ_RD_CTL_D1 0x28b8
661 #define MC_SEQ_WR_CTL_D0 0x28bc
662 #define MC_SEQ_WR_CTL_D1 0x28c0
663
664 #define MC_SEQ_SUP_CNTL 0x28c8
665 #define RUN_MASK (1 << 0)
666 #define MC_SEQ_SUP_PGM 0x28cc
667 #define MC_PMG_AUTO_CMD 0x28d0
668
669 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
670 #define TRAIN_DONE_D0 (1 << 30)
671 #define TRAIN_DONE_D1 (1 << 31)
672
673 #define MC_IO_PAD_CNTL_D0 0x29d0
674 #define MEM_FALL_OUT_CMD (1 << 8)
675
676 #define MC_SEQ_MISC0 0x2a00
677 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
678 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
679 #define MC_SEQ_MISC0_VEN_ID_VALUE 3
680 #define MC_SEQ_MISC0_REV_ID_SHIFT 12
681 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
682 #define MC_SEQ_MISC0_REV_ID_VALUE 1
683 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
684 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
685 #define MC_SEQ_MISC0_GDDR5_VALUE 5
686 #define MC_SEQ_MISC1 0x2a04
687 #define MC_SEQ_RESERVE_M 0x2a08
688 #define MC_PMG_CMD_EMRS 0x2a0c
689
690 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
691 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
692
693 #define MC_SEQ_MISC5 0x2a54
694 #define MC_SEQ_MISC6 0x2a58
695
696 #define MC_SEQ_MISC7 0x2a64
697
698 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
699 #define MC_SEQ_CAS_TIMING_LP 0x2a70
700 #define MC_SEQ_MISC_TIMING_LP 0x2a74
701 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
702 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
703 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
704 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
705 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
706
707 #define MC_PMG_CMD_MRS 0x2aac
708
709 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
710 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
711
712 #define MC_PMG_CMD_MRS1 0x2b44
713 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
714 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
715
716 #define MC_SEQ_WR_CTL_2 0x2b54
717 #define MC_SEQ_WR_CTL_2_LP 0x2b58
718 #define MC_PMG_CMD_MRS2 0x2b5c
719 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
720
721 #define MCLK_PWRMGT_CNTL 0x2ba0
722 # define DLL_SPEED(x) ((x) << 0)
723 # define DLL_SPEED_MASK (0x1f << 0)
724 # define DLL_READY (1 << 6)
725 # define MC_INT_CNTL (1 << 7)
726 # define MRDCK0_PDNB (1 << 8)
727 # define MRDCK1_PDNB (1 << 9)
728 # define MRDCK0_RESET (1 << 16)
729 # define MRDCK1_RESET (1 << 17)
730 # define DLL_READY_READ (1 << 24)
731 #define DLL_CNTL 0x2ba4
732 # define MRDCK0_BYPASS (1 << 24)
733 # define MRDCK1_BYPASS (1 << 25)
734
735 #define MPLL_FUNC_CNTL 0x2bb4
736 #define BWCTRL(x) ((x) << 20)
737 #define BWCTRL_MASK (0xff << 20)
738 #define MPLL_FUNC_CNTL_1 0x2bb8
739 #define VCO_MODE(x) ((x) << 0)
740 #define VCO_MODE_MASK (3 << 0)
741 #define CLKFRAC(x) ((x) << 4)
742 #define CLKFRAC_MASK (0xfff << 4)
743 #define CLKF(x) ((x) << 16)
744 #define CLKF_MASK (0xfff << 16)
745 #define MPLL_FUNC_CNTL_2 0x2bbc
746 #define MPLL_AD_FUNC_CNTL 0x2bc0
747 #define YCLK_POST_DIV(x) ((x) << 0)
748 #define YCLK_POST_DIV_MASK (7 << 0)
749 #define MPLL_DQ_FUNC_CNTL 0x2bc4
750 #define YCLK_SEL(x) ((x) << 4)
751 #define YCLK_SEL_MASK (1 << 4)
752
753 #define MPLL_SS1 0x2bcc
754 #define CLKV(x) ((x) << 0)
755 #define CLKV_MASK (0x3ffffff << 0)
756 #define MPLL_SS2 0x2bd0
757 #define CLKS(x) ((x) << 0)
758 #define CLKS_MASK (0xfff << 0)
759
760 #define HDP_HOST_PATH_CNTL 0x2C00
761 #define CLOCK_GATING_DIS (1 << 23)
762 #define HDP_NONSURFACE_BASE 0x2C04
763 #define HDP_NONSURFACE_INFO 0x2C08
764 #define HDP_NONSURFACE_SIZE 0x2C0C
765
766 #define HDP_ADDR_CONFIG 0x2F48
767 #define HDP_MISC_CNTL 0x2F4C
768 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
769 #define HDP_MEM_POWER_LS 0x2F50
770 #define HDP_LS_ENABLE (1 << 0)
771
772 #define ATC_MISC_CG 0x3350
773
774 #define GMCON_RENG_EXECUTE 0x3508
775 #define RENG_EXECUTE_ON_PWR_UP (1 << 0)
776 #define GMCON_MISC 0x350c
777 #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
778 #define STCTRL_STUTTER_EN (1 << 16)
779
780 #define GMCON_PGFSM_CONFIG 0x3538
781 #define GMCON_PGFSM_WRITE 0x353c
782 #define GMCON_PGFSM_READ 0x3540
783 #define GMCON_MISC3 0x3544
784
785 #define MC_SEQ_CNTL_3 0x3600
786 # define CAC_EN (1 << 31)
787 #define MC_SEQ_G5PDX_CTRL 0x3604
788 #define MC_SEQ_G5PDX_CTRL_LP 0x3608
789 #define MC_SEQ_G5PDX_CMD0 0x360c
790 #define MC_SEQ_G5PDX_CMD0_LP 0x3610
791 #define MC_SEQ_G5PDX_CMD1 0x3614
792 #define MC_SEQ_G5PDX_CMD1_LP 0x3618
793
794 #define MC_SEQ_PMG_DVS_CTL 0x3628
795 #define MC_SEQ_PMG_DVS_CTL_LP 0x362c
796 #define MC_SEQ_PMG_DVS_CMD 0x3630
797 #define MC_SEQ_PMG_DVS_CMD_LP 0x3634
798 #define MC_SEQ_DLL_STBY 0x3638
799 #define MC_SEQ_DLL_STBY_LP 0x363c
800
801 #define IH_RB_CNTL 0x3e00
802 # define IH_RB_ENABLE (1 << 0)
803 # define IH_RB_SIZE(x) ((x) << 1)
804 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
805 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
806 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9)
807 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
808 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
809 #define IH_RB_BASE 0x3e04
810 #define IH_RB_RPTR 0x3e08
811 #define IH_RB_WPTR 0x3e0c
812 # define RB_OVERFLOW (1 << 0)
813 # define WPTR_OFFSET_MASK 0x3fffc
814 #define IH_RB_WPTR_ADDR_HI 0x3e10
815 #define IH_RB_WPTR_ADDR_LO 0x3e14
816 #define IH_CNTL 0x3e18
817 # define ENABLE_INTR (1 << 0)
818 # define IH_MC_SWAP(x) ((x) << 1)
819 # define IH_MC_SWAP_NONE 0
820 # define IH_MC_SWAP_16BIT 1
821 # define IH_MC_SWAP_32BIT 2
822 # define IH_MC_SWAP_64BIT 3
823 # define RPTR_REARM (1 << 4)
824 # define MC_WRREQ_CREDIT(x) ((x) << 15)
825 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
826 # define MC_VMID(x) ((x) << 25)
827
828 #define BIF_LNCNT_RESET 0x5220
829 # define RESET_LNCNT_EN (1 << 0)
830
831 #define CONFIG_MEMSIZE 0x5428
832
833 #define INTERRUPT_CNTL 0x5468
834 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
835 # define IH_DUMMY_RD_EN (1 << 1)
836 # define IH_REQ_NONSNOOP_EN (1 << 3)
837 # define GEN_IH_INT_EN (1 << 8)
838 #define INTERRUPT_CNTL2 0x546c
839
840 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
841
842 #define BIF_FB_EN 0x5490
843 #define FB_READ_EN (1 << 0)
844 #define FB_WRITE_EN (1 << 1)
845
846 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
847
848 #define GPU_HDP_FLUSH_REQ 0x54DC
849 #define GPU_HDP_FLUSH_DONE 0x54E0
850 #define CP0 (1 << 0)
851 #define CP1 (1 << 1)
852 #define CP2 (1 << 2)
853 #define CP3 (1 << 3)
854 #define CP4 (1 << 4)
855 #define CP5 (1 << 5)
856 #define CP6 (1 << 6)
857 #define CP7 (1 << 7)
858 #define CP8 (1 << 8)
859 #define CP9 (1 << 9)
860 #define SDMA0 (1 << 10)
861 #define SDMA1 (1 << 11)
862
863
864 #define LB_MEMORY_CTRL 0x6b04
865 #define LB_MEMORY_SIZE(x) ((x) << 0)
866 #define LB_MEMORY_CONFIG(x) ((x) << 20)
867
868 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
869 # define LATENCY_WATERMARK_MASK(x) ((x) << 8)
870 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
871 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
872 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
873
874
875 #define LB_VLINE_STATUS 0x6b24
876 # define VLINE_OCCURRED (1 << 0)
877 # define VLINE_ACK (1 << 4)
878 # define VLINE_STAT (1 << 12)
879 # define VLINE_INTERRUPT (1 << 16)
880 # define VLINE_INTERRUPT_TYPE (1 << 17)
881
882 #define LB_VBLANK_STATUS 0x6b2c
883 # define VBLANK_OCCURRED (1 << 0)
884 # define VBLANK_ACK (1 << 4)
885 # define VBLANK_STAT (1 << 12)
886 # define VBLANK_INTERRUPT (1 << 16)
887 # define VBLANK_INTERRUPT_TYPE (1 << 17)
888
889
890 #define LB_INTERRUPT_MASK 0x6b20
891 # define VBLANK_INTERRUPT_MASK (1 << 0)
892 # define VLINE_INTERRUPT_MASK (1 << 4)
893 # define VLINE2_INTERRUPT_MASK (1 << 8)
894
895 #define DISP_INTERRUPT_STATUS 0x60f4
896 # define LB_D1_VLINE_INTERRUPT (1 << 2)
897 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
898 # define DC_HPD1_INTERRUPT (1 << 17)
899 # define DC_HPD1_RX_INTERRUPT (1 << 18)
900 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
901 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
902 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
903 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
904 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
905 # define LB_D2_VLINE_INTERRUPT (1 << 2)
906 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
907 # define DC_HPD2_INTERRUPT (1 << 17)
908 # define DC_HPD2_RX_INTERRUPT (1 << 18)
909 # define DISP_TIMER_INTERRUPT (1 << 24)
910 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
911 # define LB_D3_VLINE_INTERRUPT (1 << 2)
912 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
913 # define DC_HPD3_INTERRUPT (1 << 17)
914 # define DC_HPD3_RX_INTERRUPT (1 << 18)
915 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
916 # define LB_D4_VLINE_INTERRUPT (1 << 2)
917 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
918 # define DC_HPD4_INTERRUPT (1 << 17)
919 # define DC_HPD4_RX_INTERRUPT (1 << 18)
920 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
921 # define LB_D5_VLINE_INTERRUPT (1 << 2)
922 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
923 # define DC_HPD5_INTERRUPT (1 << 17)
924 # define DC_HPD5_RX_INTERRUPT (1 << 18)
925 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
926 # define LB_D6_VLINE_INTERRUPT (1 << 2)
927 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
928 # define DC_HPD6_INTERRUPT (1 << 17)
929 # define DC_HPD6_RX_INTERRUPT (1 << 18)
930 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
931
932
933 #define GRPH_INT_STATUS 0x6858
934 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
935 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
936
937 #define GRPH_INT_CONTROL 0x685c
938 # define GRPH_PFLIP_INT_MASK (1 << 0)
939 # define GRPH_PFLIP_INT_TYPE (1 << 8)
940
941 #define DAC_AUTODETECT_INT_CONTROL 0x67c8
942
943 #define DC_HPD1_INT_STATUS 0x601c
944 #define DC_HPD2_INT_STATUS 0x6028
945 #define DC_HPD3_INT_STATUS 0x6034
946 #define DC_HPD4_INT_STATUS 0x6040
947 #define DC_HPD5_INT_STATUS 0x604c
948 #define DC_HPD6_INT_STATUS 0x6058
949 # define DC_HPDx_INT_STATUS (1 << 0)
950 # define DC_HPDx_SENSE (1 << 1)
951 # define DC_HPDx_SENSE_DELAYED (1 << 4)
952 # define DC_HPDx_RX_INT_STATUS (1 << 8)
953
954 #define DC_HPD1_INT_CONTROL 0x6020
955 #define DC_HPD2_INT_CONTROL 0x602c
956 #define DC_HPD3_INT_CONTROL 0x6038
957 #define DC_HPD4_INT_CONTROL 0x6044
958 #define DC_HPD5_INT_CONTROL 0x6050
959 #define DC_HPD6_INT_CONTROL 0x605c
960 # define DC_HPDx_INT_ACK (1 << 0)
961 # define DC_HPDx_INT_POLARITY (1 << 8)
962 # define DC_HPDx_INT_EN (1 << 16)
963 # define DC_HPDx_RX_INT_ACK (1 << 20)
964 # define DC_HPDx_RX_INT_EN (1 << 24)
965
966 #define DC_HPD1_CONTROL 0x6024
967 #define DC_HPD2_CONTROL 0x6030
968 #define DC_HPD3_CONTROL 0x603c
969 #define DC_HPD4_CONTROL 0x6048
970 #define DC_HPD5_CONTROL 0x6054
971 #define DC_HPD6_CONTROL 0x6060
972 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
973 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
974 # define DC_HPDx_EN (1 << 28)
975
976 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
977 # define STUTTER_ENABLE (1 << 0)
978
979
980 #define FMT_DYNAMIC_EXP_CNTL 0x6fb4
981 # define FMT_DYNAMIC_EXP_EN (1 << 0)
982 # define FMT_DYNAMIC_EXP_MODE (1 << 4)
983
984 #define FMT_CONTROL 0x6fb8
985 # define FMT_PIXEL_ENCODING (1 << 16)
986
987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8
988 # define FMT_TRUNCATE_EN (1 << 0)
989 # define FMT_TRUNCATE_MODE (1 << 1)
990 # define FMT_TRUNCATE_DEPTH(x) ((x) << 4)
991 # define FMT_SPATIAL_DITHER_EN (1 << 8)
992 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
993 # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11)
994 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
995 # define FMT_RGB_RANDOM_ENABLE (1 << 14)
996 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
997 # define FMT_TEMPORAL_DITHER_EN (1 << 16)
998 # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17)
999 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
1000 # define FMT_TEMPORAL_LEVEL (1 << 24)
1001 # define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1002 # define FMT_25FRC_SEL(x) ((x) << 26)
1003 # define FMT_50FRC_SEL(x) ((x) << 28)
1004 # define FMT_75FRC_SEL(x) ((x) << 30)
1005 #define FMT_CLAMP_CONTROL 0x6fe4
1006 # define FMT_CLAMP_DATA_EN (1 << 0)
1007 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
1008 # define FMT_CLAMP_6BPC 0
1009 # define FMT_CLAMP_8BPC 1
1010 # define FMT_CLAMP_10BPC 2
1011
1012 #define GRBM_CNTL 0x8000
1013 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
1014
1015 #define GRBM_STATUS2 0x8008
1016 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
1017 #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
1018 #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
1019 #define ME1PIPE0_RQ_PENDING (1 << 6)
1020 #define ME1PIPE1_RQ_PENDING (1 << 7)
1021 #define ME1PIPE2_RQ_PENDING (1 << 8)
1022 #define ME1PIPE3_RQ_PENDING (1 << 9)
1023 #define ME2PIPE0_RQ_PENDING (1 << 10)
1024 #define ME2PIPE1_RQ_PENDING (1 << 11)
1025 #define ME2PIPE2_RQ_PENDING (1 << 12)
1026 #define ME2PIPE3_RQ_PENDING (1 << 13)
1027 #define RLC_RQ_PENDING (1 << 14)
1028 #define RLC_BUSY (1 << 24)
1029 #define TC_BUSY (1 << 25)
1030 #define CPF_BUSY (1 << 28)
1031 #define CPC_BUSY (1 << 29)
1032 #define CPG_BUSY (1 << 30)
1033
1034 #define GRBM_STATUS 0x8010
1035 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
1036 #define SRBM_RQ_PENDING (1 << 5)
1037 #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
1038 #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
1039 #define GDS_DMA_RQ_PENDING (1 << 9)
1040 #define DB_CLEAN (1 << 12)
1041 #define CB_CLEAN (1 << 13)
1042 #define TA_BUSY (1 << 14)
1043 #define GDS_BUSY (1 << 15)
1044 #define WD_BUSY_NO_DMA (1 << 16)
1045 #define VGT_BUSY (1 << 17)
1046 #define IA_BUSY_NO_DMA (1 << 18)
1047 #define IA_BUSY (1 << 19)
1048 #define SX_BUSY (1 << 20)
1049 #define WD_BUSY (1 << 21)
1050 #define SPI_BUSY (1 << 22)
1051 #define BCI_BUSY (1 << 23)
1052 #define SC_BUSY (1 << 24)
1053 #define PA_BUSY (1 << 25)
1054 #define DB_BUSY (1 << 26)
1055 #define CP_COHERENCY_BUSY (1 << 28)
1056 #define CP_BUSY (1 << 29)
1057 #define CB_BUSY (1 << 30)
1058 #define GUI_ACTIVE (1 << 31)
1059 #define GRBM_STATUS_SE0 0x8014
1060 #define GRBM_STATUS_SE1 0x8018
1061 #define GRBM_STATUS_SE2 0x8038
1062 #define GRBM_STATUS_SE3 0x803C
1063 #define SE_DB_CLEAN (1 << 1)
1064 #define SE_CB_CLEAN (1 << 2)
1065 #define SE_BCI_BUSY (1 << 22)
1066 #define SE_VGT_BUSY (1 << 23)
1067 #define SE_PA_BUSY (1 << 24)
1068 #define SE_TA_BUSY (1 << 25)
1069 #define SE_SX_BUSY (1 << 26)
1070 #define SE_SPI_BUSY (1 << 27)
1071 #define SE_SC_BUSY (1 << 29)
1072 #define SE_DB_BUSY (1 << 30)
1073 #define SE_CB_BUSY (1 << 31)
1074
1075 #define GRBM_SOFT_RESET 0x8020
1076 #define SOFT_RESET_CP (1 << 0)
1077 #define SOFT_RESET_RLC (1 << 2)
1078 #define SOFT_RESET_GFX (1 << 16)
1079 #define SOFT_RESET_CPF (1 << 17)
1080 #define SOFT_RESET_CPC (1 << 18)
1081 #define SOFT_RESET_CPG (1 << 19)
1082
1083 #define GRBM_INT_CNTL 0x8060
1084 # define RDERR_INT_ENABLE (1 << 0)
1085 # define GUI_IDLE_INT_ENABLE (1 << 19)
1086
1087 #define CP_CPC_STATUS 0x8210
1088 #define CP_CPC_BUSY_STAT 0x8214
1089 #define CP_CPC_STALLED_STAT1 0x8218
1090 #define CP_CPF_STATUS 0x821c
1091 #define CP_CPF_BUSY_STAT 0x8220
1092 #define CP_CPF_STALLED_STAT1 0x8224
1093
1094 #define CP_MEC_CNTL 0x8234
1095 #define MEC_ME2_HALT (1 << 28)
1096 #define MEC_ME1_HALT (1 << 30)
1097
1098 #define CP_MEC_CNTL 0x8234
1099 #define MEC_ME2_HALT (1 << 28)
1100 #define MEC_ME1_HALT (1 << 30)
1101
1102 #define CP_STALLED_STAT3 0x8670
1103 #define CP_STALLED_STAT1 0x8674
1104 #define CP_STALLED_STAT2 0x8678
1105
1106 #define CP_STAT 0x8680
1107
1108 #define CP_ME_CNTL 0x86D8
1109 #define CP_CE_HALT (1 << 24)
1110 #define CP_PFP_HALT (1 << 26)
1111 #define CP_ME_HALT (1 << 28)
1112
1113 #define CP_RB0_RPTR 0x8700
1114 #define CP_RB_WPTR_DELAY 0x8704
1115 #define CP_RB_WPTR_POLL_CNTL 0x8708
1116 #define IDLE_POLL_COUNT(x) ((x) << 16)
1117 #define IDLE_POLL_COUNT_MASK (0xffff << 16)
1118
1119 #define CP_MEQ_THRESHOLDS 0x8764
1120 #define MEQ1_START(x) ((x) << 0)
1121 #define MEQ2_START(x) ((x) << 8)
1122
1123 #define VGT_VTX_VECT_EJECT_REG 0x88B0
1124
1125 #define VGT_CACHE_INVALIDATION 0x88C4
1126 #define CACHE_INVALIDATION(x) ((x) << 0)
1127 #define VC_ONLY 0
1128 #define TC_ONLY 1
1129 #define VC_AND_TC 2
1130 #define AUTO_INVLD_EN(x) ((x) << 6)
1131 #define NO_AUTO 0
1132 #define ES_AUTO 1
1133 #define GS_AUTO 2
1134 #define ES_AND_GS_AUTO 3
1135
1136 #define VGT_GS_VERTEX_REUSE 0x88D4
1137
1138 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1139 #define INACTIVE_CUS_MASK 0xFFFF0000
1140 #define INACTIVE_CUS_SHIFT 16
1141 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1142
1143 #define PA_CL_ENHANCE 0x8A14
1144 #define CLIP_VTX_REORDER_ENA (1 << 0)
1145 #define NUM_CLIP_SEQ(x) ((x) << 1)
1146
1147 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1148 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1149 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1150
1151 #define PA_SC_FIFO_SIZE 0x8BCC
1152 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1153 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1154 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1155 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1156
1157 #define PA_SC_ENHANCE 0x8BF0
1158 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
1159 #define DISABLE_PA_SC_GUIDANCE (1 << 13)
1160
1161 #define SQ_CONFIG 0x8C00
1162
1163 #define SH_MEM_BASES 0x8C28
1164
1165 #define PRIVATE_BASE(x) ((x) << 0)
1166 #define SHARED_BASE(x) ((x) << 16)
1167 #define SH_MEM_APE1_BASE 0x8C2C
1168
1169 #define SH_MEM_APE1_LIMIT 0x8C30
1170
1171 #define SH_MEM_CONFIG 0x8C34
1172 #define PTR32 (1 << 0)
1173 #define ALIGNMENT_MODE(x) ((x) << 2)
1174 #define SH_MEM_ALIGNMENT_MODE_DWORD 0
1175 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
1176 #define SH_MEM_ALIGNMENT_MODE_STRICT 2
1177 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
1178 #define DEFAULT_MTYPE(x) ((x) << 4)
1179 #define APE1_MTYPE(x) ((x) << 7)
1180
1181 #define MTYPE_CACHED 0
1182 #define MTYPE_NONCACHED 3
1183
1184 #define SX_DEBUG_1 0x9060
1185
1186 #define SPI_CONFIG_CNTL 0x9100
1187
1188 #define SPI_CONFIG_CNTL_1 0x913C
1189 #define VTX_DONE_DELAY(x) ((x) << 0)
1190 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1191
1192 #define TA_CNTL_AUX 0x9508
1193
1194 #define DB_DEBUG 0x9830
1195 #define DB_DEBUG2 0x9834
1196 #define DB_DEBUG3 0x9838
1197
1198 #define CC_RB_BACKEND_DISABLE 0x98F4
1199 #define BACKEND_DISABLE(x) ((x) << 16)
1200 #define GB_ADDR_CONFIG 0x98F8
1201 #define NUM_PIPES(x) ((x) << 0)
1202 #define NUM_PIPES_MASK 0x00000007
1203 #define NUM_PIPES_SHIFT 0
1204 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1205 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1206 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
1207 #define NUM_SHADER_ENGINES(x) ((x) << 12)
1208 #define NUM_SHADER_ENGINES_MASK 0x00003000
1209 #define NUM_SHADER_ENGINES_SHIFT 12
1210 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1211 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1212 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1213 #define ROW_SIZE(x) ((x) << 28)
1214 #define ROW_SIZE_MASK 0x30000000
1215 #define ROW_SIZE_SHIFT 28
1216
1217 #define GB_TILE_MODE0 0x9910
1218 # define ARRAY_MODE(x) ((x) << 2)
1219 # define ARRAY_LINEAR_GENERAL 0
1220 # define ARRAY_LINEAR_ALIGNED 1
1221 # define ARRAY_1D_TILED_THIN1 2
1222 # define ARRAY_2D_TILED_THIN1 4
1223 # define ARRAY_PRT_TILED_THIN1 5
1224 # define ARRAY_PRT_2D_TILED_THIN1 6
1225 # define PIPE_CONFIG(x) ((x) << 6)
1226 # define ADDR_SURF_P2 0
1227 # define ADDR_SURF_P4_8x16 4
1228 # define ADDR_SURF_P4_16x16 5
1229 # define ADDR_SURF_P4_16x32 6
1230 # define ADDR_SURF_P4_32x32 7
1231 # define ADDR_SURF_P8_16x16_8x16 8
1232 # define ADDR_SURF_P8_16x32_8x16 9
1233 # define ADDR_SURF_P8_32x32_8x16 10
1234 # define ADDR_SURF_P8_16x32_16x16 11
1235 # define ADDR_SURF_P8_32x32_16x16 12
1236 # define ADDR_SURF_P8_32x32_16x32 13
1237 # define ADDR_SURF_P8_32x64_32x32 14
1238 # define ADDR_SURF_P16_32x32_8x16 16
1239 # define ADDR_SURF_P16_32x32_16x16 17
1240 # define TILE_SPLIT(x) ((x) << 11)
1241 # define ADDR_SURF_TILE_SPLIT_64B 0
1242 # define ADDR_SURF_TILE_SPLIT_128B 1
1243 # define ADDR_SURF_TILE_SPLIT_256B 2
1244 # define ADDR_SURF_TILE_SPLIT_512B 3
1245 # define ADDR_SURF_TILE_SPLIT_1KB 4
1246 # define ADDR_SURF_TILE_SPLIT_2KB 5
1247 # define ADDR_SURF_TILE_SPLIT_4KB 6
1248 # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
1249 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
1250 # define ADDR_SURF_THIN_MICRO_TILING 1
1251 # define ADDR_SURF_DEPTH_MICRO_TILING 2
1252 # define ADDR_SURF_ROTATED_MICRO_TILING 3
1253 # define SAMPLE_SPLIT(x) ((x) << 25)
1254 # define ADDR_SURF_SAMPLE_SPLIT_1 0
1255 # define ADDR_SURF_SAMPLE_SPLIT_2 1
1256 # define ADDR_SURF_SAMPLE_SPLIT_4 2
1257 # define ADDR_SURF_SAMPLE_SPLIT_8 3
1258
1259 #define GB_MACROTILE_MODE0 0x9990
1260 # define BANK_WIDTH(x) ((x) << 0)
1261 # define ADDR_SURF_BANK_WIDTH_1 0
1262 # define ADDR_SURF_BANK_WIDTH_2 1
1263 # define ADDR_SURF_BANK_WIDTH_4 2
1264 # define ADDR_SURF_BANK_WIDTH_8 3
1265 # define BANK_HEIGHT(x) ((x) << 2)
1266 # define ADDR_SURF_BANK_HEIGHT_1 0
1267 # define ADDR_SURF_BANK_HEIGHT_2 1
1268 # define ADDR_SURF_BANK_HEIGHT_4 2
1269 # define ADDR_SURF_BANK_HEIGHT_8 3
1270 # define MACRO_TILE_ASPECT(x) ((x) << 4)
1271 # define ADDR_SURF_MACRO_ASPECT_1 0
1272 # define ADDR_SURF_MACRO_ASPECT_2 1
1273 # define ADDR_SURF_MACRO_ASPECT_4 2
1274 # define ADDR_SURF_MACRO_ASPECT_8 3
1275 # define NUM_BANKS(x) ((x) << 6)
1276 # define ADDR_SURF_2_BANK 0
1277 # define ADDR_SURF_4_BANK 1
1278 # define ADDR_SURF_8_BANK 2
1279 # define ADDR_SURF_16_BANK 3
1280
1281 #define CB_HW_CONTROL 0x9A10
1282
1283 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1284 #define BACKEND_DISABLE_MASK 0x00FF0000
1285 #define BACKEND_DISABLE_SHIFT 16
1286
1287 #define TCP_CHAN_STEER_LO 0xac0c
1288 #define TCP_CHAN_STEER_HI 0xac10
1289
1290 #define TC_CFG_L1_LOAD_POLICY0 0xAC68
1291 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C
1292 #define TC_CFG_L1_STORE_POLICY 0xAC70
1293 #define TC_CFG_L2_LOAD_POLICY0 0xAC74
1294 #define TC_CFG_L2_LOAD_POLICY1 0xAC78
1295 #define TC_CFG_L2_STORE_POLICY0 0xAC7C
1296 #define TC_CFG_L2_STORE_POLICY1 0xAC80
1297 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84
1298 #define TC_CFG_L1_VOLATILE 0xAC88
1299 #define TC_CFG_L2_VOLATILE 0xAC8C
1300
1301 #define CP_RB0_BASE 0xC100
1302 #define CP_RB0_CNTL 0xC104
1303 #define RB_BUFSZ(x) ((x) << 0)
1304 #define RB_BLKSZ(x) ((x) << 8)
1305 #define BUF_SWAP_32BIT (2 << 16)
1306 #define RB_NO_UPDATE (1 << 27)
1307 #define RB_RPTR_WR_ENA (1 << 31)
1308
1309 #define CP_RB0_RPTR_ADDR 0xC10C
1310 #define RB_RPTR_SWAP_32BIT (2 << 0)
1311 #define CP_RB0_RPTR_ADDR_HI 0xC110
1312 #define CP_RB0_WPTR 0xC114
1313
1314 #define CP_DEVICE_ID 0xC12C
1315 #define CP_ENDIAN_SWAP 0xC140
1316 #define CP_RB_VMID 0xC144
1317
1318 #define CP_PFP_UCODE_ADDR 0xC150
1319 #define CP_PFP_UCODE_DATA 0xC154
1320 #define CP_ME_RAM_RADDR 0xC158
1321 #define CP_ME_RAM_WADDR 0xC15C
1322 #define CP_ME_RAM_DATA 0xC160
1323
1324 #define CP_CE_UCODE_ADDR 0xC168
1325 #define CP_CE_UCODE_DATA 0xC16C
1326 #define CP_MEC_ME1_UCODE_ADDR 0xC170
1327 #define CP_MEC_ME1_UCODE_DATA 0xC174
1328 #define CP_MEC_ME2_UCODE_ADDR 0xC178
1329 #define CP_MEC_ME2_UCODE_DATA 0xC17C
1330
1331 #define CP_INT_CNTL_RING0 0xC1A8
1332 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1333 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1334 # define PRIV_INSTR_INT_ENABLE (1 << 22)
1335 # define PRIV_REG_INT_ENABLE (1 << 23)
1336 # define OPCODE_ERROR_INT_ENABLE (1 << 24)
1337 # define TIME_STAMP_INT_ENABLE (1 << 26)
1338 # define CP_RINGID2_INT_ENABLE (1 << 29)
1339 # define CP_RINGID1_INT_ENABLE (1 << 30)
1340 # define CP_RINGID0_INT_ENABLE (1 << 31)
1341
1342 #define CP_INT_STATUS_RING0 0xC1B4
1343 # define PRIV_INSTR_INT_STAT (1 << 22)
1344 # define PRIV_REG_INT_STAT (1 << 23)
1345 # define TIME_STAMP_INT_STAT (1 << 26)
1346 # define CP_RINGID2_INT_STAT (1 << 29)
1347 # define CP_RINGID1_INT_STAT (1 << 30)
1348 # define CP_RINGID0_INT_STAT (1 << 31)
1349
1350 #define CP_MEM_SLP_CNTL 0xC1E4
1351 # define CP_MEM_LS_EN (1 << 0)
1352
1353 #define CP_CPF_DEBUG 0xC200
1354
1355 #define CP_PQ_WPTR_POLL_CNTL 0xC20C
1356 #define WPTR_POLL_EN (1 << 31)
1357
1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214
1359 #define CP_ME1_PIPE1_INT_CNTL 0xC218
1360 #define CP_ME1_PIPE2_INT_CNTL 0xC21C
1361 #define CP_ME1_PIPE3_INT_CNTL 0xC220
1362 #define CP_ME2_PIPE0_INT_CNTL 0xC224
1363 #define CP_ME2_PIPE1_INT_CNTL 0xC228
1364 #define CP_ME2_PIPE2_INT_CNTL 0xC22C
1365 #define CP_ME2_PIPE3_INT_CNTL 0xC230
1366 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
1367 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
1368 # define PRIV_REG_INT_ENABLE (1 << 23)
1369 # define TIME_STAMP_INT_ENABLE (1 << 26)
1370 # define GENERIC2_INT_ENABLE (1 << 29)
1371 # define GENERIC1_INT_ENABLE (1 << 30)
1372 # define GENERIC0_INT_ENABLE (1 << 31)
1373 #define CP_ME1_PIPE0_INT_STATUS 0xC214
1374 #define CP_ME1_PIPE1_INT_STATUS 0xC218
1375 #define CP_ME1_PIPE2_INT_STATUS 0xC21C
1376 #define CP_ME1_PIPE3_INT_STATUS 0xC220
1377 #define CP_ME2_PIPE0_INT_STATUS 0xC224
1378 #define CP_ME2_PIPE1_INT_STATUS 0xC228
1379 #define CP_ME2_PIPE2_INT_STATUS 0xC22C
1380 #define CP_ME2_PIPE3_INT_STATUS 0xC230
1381 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
1382 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
1383 # define PRIV_REG_INT_STATUS (1 << 23)
1384 # define TIME_STAMP_INT_STATUS (1 << 26)
1385 # define GENERIC2_INT_STATUS (1 << 29)
1386 # define GENERIC1_INT_STATUS (1 << 30)
1387 # define GENERIC0_INT_STATUS (1 << 31)
1388
1389 #define CP_MAX_CONTEXT 0xC2B8
1390
1391 #define CP_RB0_BASE_HI 0xC2C4
1392
1393 #define RLC_CNTL 0xC300
1394 # define RLC_ENABLE (1 << 0)
1395
1396 #define RLC_MC_CNTL 0xC30C
1397
1398 #define RLC_MEM_SLP_CNTL 0xC318
1399 # define RLC_MEM_LS_EN (1 << 0)
1400
1401 #define RLC_LB_CNTR_MAX 0xC348
1402
1403 #define RLC_LB_CNTL 0xC364
1404 # define LOAD_BALANCE_ENABLE (1 << 0)
1405
1406 #define RLC_LB_CNTR_INIT 0xC36C
1407
1408 #define RLC_SAVE_AND_RESTORE_BASE 0xC374
1409 #define RLC_DRIVER_DMA_STATUS 0xC378
1410 #define RLC_CP_TABLE_RESTORE 0xC378
1411 #define RLC_PG_DELAY_2 0xC37C
1412
1413 #define RLC_GPM_UCODE_ADDR 0xC388
1414 #define RLC_GPM_UCODE_DATA 0xC38C
1415 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390
1416 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394
1417 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
1418 #define RLC_UCODE_CNTL 0xC39C
1419
1420 #define RLC_GPM_STAT 0xC400
1421 # define RLC_GPM_BUSY (1 << 0)
1422 # define GFX_POWER_STATUS (1 << 1)
1423 # define GFX_CLOCK_STATUS (1 << 2)
1424
1425 #define RLC_PG_CNTL 0xC40C
1426 # define GFX_PG_ENABLE (1 << 0)
1427 # define GFX_PG_SRC (1 << 1)
1428 # define DYN_PER_CU_PG_ENABLE (1 << 2)
1429 # define STATIC_PER_CU_PG_ENABLE (1 << 3)
1430 # define DISABLE_GDS_PG (1 << 13)
1431 # define DISABLE_CP_PG (1 << 15)
1432 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
1433 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
1434
1435 #define RLC_CGTT_MGCG_OVERRIDE 0xC420
1436 #define RLC_CGCG_CGLS_CTRL 0xC424
1437 # define CGCG_EN (1 << 0)
1438 # define CGLS_EN (1 << 1)
1439
1440 #define RLC_PG_DELAY 0xC434
1441
1442 #define RLC_LB_INIT_CU_MASK 0xC43C
1443
1444 #define RLC_LB_PARAMS 0xC444
1445
1446 #define RLC_PG_AO_CU_MASK 0xC44C
1447
1448 #define RLC_MAX_PG_CU 0xC450
1449 # define MAX_PU_CU(x) ((x) << 0)
1450 # define MAX_PU_CU_MASK (0xff << 0)
1451 #define RLC_AUTO_PG_CTRL 0xC454
1452 # define AUTO_PG_EN (1 << 0)
1453 # define GRBM_REG_SGIT(x) ((x) << 3)
1454 # define GRBM_REG_SGIT_MASK (0xffff << 3)
1455
1456 #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
1457 #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
1458 #define RLC_SERDES_WR_CTRL 0xC47C
1459 #define BPM_ADDR(x) ((x) << 0)
1460 #define BPM_ADDR_MASK (0xff << 0)
1461 #define CGLS_ENABLE (1 << 16)
1462 #define CGCG_OVERRIDE_0 (1 << 20)
1463 #define MGCG_OVERRIDE_0 (1 << 22)
1464 #define MGCG_OVERRIDE_1 (1 << 23)
1465
1466 #define RLC_SERDES_CU_MASTER_BUSY 0xC484
1467 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
1468 # define SE_MASTER_BUSY_MASK 0x0000ffff
1469 # define GC_MASTER_BUSY (1 << 16)
1470 # define TC0_MASTER_BUSY (1 << 17)
1471 # define TC1_MASTER_BUSY (1 << 18)
1472
1473 #define RLC_GPM_SCRATCH_ADDR 0xC4B0
1474 #define RLC_GPM_SCRATCH_DATA 0xC4B4
1475
1476 #define RLC_GPR_REG2 0xC4E8
1477 #define REQ 0x00000001
1478 #define MESSAGE(x) ((x) << 1)
1479 #define MESSAGE_MASK 0x0000001e
1480 #define MSG_ENTER_RLC_SAFE_MODE 1
1481 #define MSG_EXIT_RLC_SAFE_MODE 0
1482
1483 #define CP_HPD_EOP_BASE_ADDR 0xC904
1484 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1485 #define CP_HPD_EOP_VMID 0xC90C
1486 #define CP_HPD_EOP_CONTROL 0xC910
1487 #define EOP_SIZE(x) ((x) << 0)
1488 #define EOP_SIZE_MASK (0x3f << 0)
1489 #define CP_MQD_BASE_ADDR 0xC914
1490 #define CP_MQD_BASE_ADDR_HI 0xC918
1491 #define CP_HQD_ACTIVE 0xC91C
1492 #define CP_HQD_VMID 0xC920
1493
1494 #define CP_HQD_PERSISTENT_STATE 0xC924u
1495 #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)
1496
1497 #define CP_HQD_PIPE_PRIORITY 0xC928u
1498 #define CP_HQD_QUEUE_PRIORITY 0xC92Cu
1499 #define CP_HQD_QUANTUM 0xC930u
1500 #define QUANTUM_EN 1U
1501 #define QUANTUM_SCALE_1MS (1U << 4)
1502 #define QUANTUM_DURATION(x) ((x) << 8)
1503
1504 #define CP_HQD_PQ_BASE 0xC934
1505 #define CP_HQD_PQ_BASE_HI 0xC938
1506 #define CP_HQD_PQ_RPTR 0xC93C
1507 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
1508 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
1509 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
1510 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
1511 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
1512 #define DOORBELL_OFFSET(x) ((x) << 2)
1513 #define DOORBELL_OFFSET_MASK (0x1fffff << 2)
1514 #define DOORBELL_SOURCE (1 << 28)
1515 #define DOORBELL_SCHD_HIT (1 << 29)
1516 #define DOORBELL_EN (1 << 30)
1517 #define DOORBELL_HIT (1 << 31)
1518 #define CP_HQD_PQ_WPTR 0xC954
1519 #define CP_HQD_PQ_CONTROL 0xC958
1520 #define QUEUE_SIZE(x) ((x) << 0)
1521 #define QUEUE_SIZE_MASK (0x3f << 0)
1522 #define RPTR_BLOCK_SIZE(x) ((x) << 8)
1523 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
1524 #define PQ_VOLATILE (1 << 26)
1525 #define NO_UPDATE_RPTR (1 << 27)
1526 #define UNORD_DISPATCH (1 << 28)
1527 #define ROQ_PQ_IB_FLIP (1 << 29)
1528 #define PRIV_STATE (1 << 30)
1529 #define KMD_QUEUE (1 << 31)
1530
1531 #define CP_HQD_IB_BASE_ADDR 0xC95Cu
1532 #define CP_HQD_IB_BASE_ADDR_HI 0xC960u
1533 #define CP_HQD_IB_RPTR 0xC964u
1534 #define CP_HQD_IB_CONTROL 0xC968u
1535 #define IB_ATC_EN (1U << 23)
1536 #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
1537
1538 #define CP_HQD_DEQUEUE_REQUEST 0xC974
1539 #define DEQUEUE_REQUEST_DRAIN 1
1540 #define DEQUEUE_REQUEST_RESET 2
1541
1542 #define CP_MQD_CONTROL 0xC99C
1543 #define MQD_VMID(x) ((x) << 0)
1544 #define MQD_VMID_MASK (0xf << 0)
1545
1546 #define CP_HQD_SEMA_CMD 0xC97Cu
1547 #define CP_HQD_MSG_TYPE 0xC980u
1548 #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u
1549 #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u
1550 #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu
1551 #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u
1552 #define CP_HQD_HQ_SCHEDULER0 0xC994u
1553 #define CP_HQD_HQ_SCHEDULER1 0xC998u
1554
1555 #define SH_STATIC_MEM_CONFIG 0x9604u
1556
1557 #define DB_RENDER_CONTROL 0x28000
1558
1559 #define PA_SC_RASTER_CONFIG 0x28350
1560 # define RASTER_CONFIG_RB_MAP_0 0
1561 # define RASTER_CONFIG_RB_MAP_1 1
1562 # define RASTER_CONFIG_RB_MAP_2 2
1563 # define RASTER_CONFIG_RB_MAP_3 3
1564 #define PKR_MAP(x) ((x) << 8)
1565
1566 #define VGT_EVENT_INITIATOR 0x28a90
1567 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1568 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1569 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1570 # define CACHE_FLUSH_TS (4 << 0)
1571 # define CACHE_FLUSH (6 << 0)
1572 # define CS_PARTIAL_FLUSH (7 << 0)
1573 # define VGT_STREAMOUT_RESET (10 << 0)
1574 # define END_OF_PIPE_INCR_DE (11 << 0)
1575 # define END_OF_PIPE_IB_END (12 << 0)
1576 # define RST_PIX_CNT (13 << 0)
1577 # define VS_PARTIAL_FLUSH (15 << 0)
1578 # define PS_PARTIAL_FLUSH (16 << 0)
1579 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1580 # define ZPASS_DONE (21 << 0)
1581 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1582 # define PERFCOUNTER_START (23 << 0)
1583 # define PERFCOUNTER_STOP (24 << 0)
1584 # define PIPELINESTAT_START (25 << 0)
1585 # define PIPELINESTAT_STOP (26 << 0)
1586 # define PERFCOUNTER_SAMPLE (27 << 0)
1587 # define SAMPLE_PIPELINESTAT (30 << 0)
1588 # define SO_VGT_STREAMOUT_FLUSH (31 << 0)
1589 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1590 # define RESET_VTX_CNT (33 << 0)
1591 # define VGT_FLUSH (36 << 0)
1592 # define BOTTOM_OF_PIPE_TS (40 << 0)
1593 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1594 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1595 # define FLUSH_AND_INV_DB_META (44 << 0)
1596 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1597 # define FLUSH_AND_INV_CB_META (46 << 0)
1598 # define CS_DONE (47 << 0)
1599 # define PS_DONE (48 << 0)
1600 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1601 # define THREAD_TRACE_START (51 << 0)
1602 # define THREAD_TRACE_STOP (52 << 0)
1603 # define THREAD_TRACE_FLUSH (54 << 0)
1604 # define THREAD_TRACE_FINISH (55 << 0)
1605 # define PIXEL_PIPE_STAT_CONTROL (56 << 0)
1606 # define PIXEL_PIPE_STAT_DUMP (57 << 0)
1607 # define PIXEL_PIPE_STAT_RESET (58 << 0)
1608
1609 #define SCRATCH_REG0 0x30100
1610 #define SCRATCH_REG1 0x30104
1611 #define SCRATCH_REG2 0x30108
1612 #define SCRATCH_REG3 0x3010C
1613 #define SCRATCH_REG4 0x30110
1614 #define SCRATCH_REG5 0x30114
1615 #define SCRATCH_REG6 0x30118
1616 #define SCRATCH_REG7 0x3011C
1617
1618 #define SCRATCH_UMSK 0x30140
1619 #define SCRATCH_ADDR 0x30144
1620
1621 #define CP_SEM_WAIT_TIMER 0x301BC
1622
1623 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
1624
1625 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
1626
1627 #define GRBM_GFX_INDEX 0x30800
1628 #define INSTANCE_INDEX(x) ((x) << 0)
1629 #define SH_INDEX(x) ((x) << 8)
1630 #define SE_INDEX(x) ((x) << 16)
1631 #define SH_BROADCAST_WRITES (1 << 29)
1632 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1633 #define SE_BROADCAST_WRITES (1 << 31)
1634
1635 #define VGT_ESGS_RING_SIZE 0x30900
1636 #define VGT_GSVS_RING_SIZE 0x30904
1637 #define VGT_PRIMITIVE_TYPE 0x30908
1638 #define VGT_INDEX_TYPE 0x3090C
1639
1640 #define VGT_NUM_INDICES 0x30930
1641 #define VGT_NUM_INSTANCES 0x30934
1642 #define VGT_TF_RING_SIZE 0x30938
1643 #define VGT_HS_OFFCHIP_PARAM 0x3093C
1644 #define VGT_TF_MEMORY_BASE 0x30940
1645
1646 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00
1647 #define PA_SC_LINE_STIPPLE_STATE 0x30a04
1648
1649 #define SQC_CACHES 0x30d20
1650
1651 #define CP_PERFMON_CNTL 0x36020
1652
1653 #define CGTS_SM_CTRL_REG 0x3c000
1654 #define SM_MODE(x) ((x) << 17)
1655 #define SM_MODE_MASK (0x7 << 17)
1656 #define SM_MODE_ENABLE (1 << 20)
1657 #define CGTS_OVERRIDE (1 << 21)
1658 #define CGTS_LS_OVERRIDE (1 << 22)
1659 #define ON_MONITOR_ADD_EN (1 << 23)
1660 #define ON_MONITOR_ADD(x) ((x) << 24)
1661 #define ON_MONITOR_ADD_MASK (0xff << 24)
1662
1663 #define CGTS_TCC_DISABLE 0x3c00c
1664 #define CGTS_USER_TCC_DISABLE 0x3c010
1665 #define TCC_DISABLE_MASK 0xFFFF0000
1666 #define TCC_DISABLE_SHIFT 16
1667
1668 #define CB_CGTT_SCLK_CTRL 0x3c2a0
1669
1670
1671
1672
1673 #define PACKET_TYPE0 0
1674 #define PACKET_TYPE1 1
1675 #define PACKET_TYPE2 2
1676 #define PACKET_TYPE3 3
1677
1678 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1679 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1680 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1681 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1682 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1683 (((reg) >> 2) & 0xFFFF) | \
1684 ((n) & 0x3FFF) << 16)
1685 #define CP_PACKET2 0x80000000
1686 #define PACKET2_PAD_SHIFT 0
1687 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1688
1689 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1690
1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1692 (((op) & 0xFF) << 8) | \
1693 ((n) & 0x3FFF) << 16)
1694
1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1696
1697
1698 #define PACKET3_NOP 0x10
1699 #define PACKET3_SET_BASE 0x11
1700 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1701 #define CE_PARTITION_BASE 3
1702 #define PACKET3_CLEAR_STATE 0x12
1703 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1704 #define PACKET3_DISPATCH_DIRECT 0x15
1705 #define PACKET3_DISPATCH_INDIRECT 0x16
1706 #define PACKET3_ATOMIC_GDS 0x1D
1707 #define PACKET3_ATOMIC_MEM 0x1E
1708 #define PACKET3_OCCLUSION_QUERY 0x1F
1709 #define PACKET3_SET_PREDICATION 0x20
1710 #define PACKET3_REG_RMW 0x21
1711 #define PACKET3_COND_EXEC 0x22
1712 #define PACKET3_PRED_EXEC 0x23
1713 #define PACKET3_DRAW_INDIRECT 0x24
1714 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1715 #define PACKET3_INDEX_BASE 0x26
1716 #define PACKET3_DRAW_INDEX_2 0x27
1717 #define PACKET3_CONTEXT_CONTROL 0x28
1718 #define PACKET3_INDEX_TYPE 0x2A
1719 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1720 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1721 #define PACKET3_NUM_INSTANCES 0x2F
1722 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1723 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
1724 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1725 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1726 #define PACKET3_DRAW_PREAMBLE 0x36
1727 #define PACKET3_WRITE_DATA 0x37
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1729
1730
1731
1732
1733
1734
1735
1736 #define WR_ONE_ADDR (1 << 16)
1737 #define WR_CONFIRM (1 << 20)
1738 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
1739
1740
1741
1742 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1743
1744
1745
1746
1747 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1748 #define PACKET3_MEM_SEMAPHORE 0x39
1749 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
1750 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20)
1751 # define PACKET3_SEM_CLIENT_CODE ((x) << 24)
1752 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1753 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1754 #define PACKET3_COPY_DW 0x3B
1755 #define PACKET3_WAIT_REG_MEM 0x3C
1756 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1757
1758
1759
1760
1761
1762
1763
1764
1765 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1766
1767
1768
1769 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
1770
1771
1772
1773 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1774
1775
1776
1777 #define PACKET3_INDIRECT_BUFFER 0x3F
1778 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1779 #define INDIRECT_BUFFER_VALID (1 << 23)
1780 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
1781
1782
1783
1784
1785 #define PACKET3_COPY_DATA 0x40
1786 #define PACKET3_PFP_SYNC_ME 0x42
1787 #define PACKET3_SURFACE_SYNC 0x43
1788 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1789 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1790 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1791 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1792 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1793 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1794 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1795 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1796 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1797 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1798 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1799 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1800 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16)
1801 # define PACKET3_TC_WB_ACTION_ENA (1 << 18)
1802 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1803 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1804 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1805 # define PACKET3_TC_ACTION_ENA (1 << 23)
1806 # define PACKET3_CB_ACTION_ENA (1 << 25)
1807 # define PACKET3_DB_ACTION_ENA (1 << 26)
1808 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1809 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1810 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1811 #define PACKET3_COND_WRITE 0x45
1812 #define PACKET3_EVENT_WRITE 0x46
1813 #define EVENT_TYPE(x) ((x) << 0)
1814 #define EVENT_INDEX(x) ((x) << 8)
1815
1816
1817
1818
1819
1820
1821
1822
1823 #define PACKET3_EVENT_WRITE_EOP 0x47
1824 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1825 #define EOP_TC_VOL_ACTION_EN (1 << 13)
1826 #define EOP_TC_WB_ACTION_EN (1 << 15)
1827 #define EOP_TCL1_ACTION_EN (1 << 16)
1828 #define EOP_TC_ACTION_EN (1 << 17)
1829 #define EOP_TCL2_VOLATILE (1 << 24)
1830 #define EOP_CACHE_POLICY(x) ((x) << 25)
1831
1832
1833
1834
1835 #define DATA_SEL(x) ((x) << 29)
1836
1837
1838
1839
1840
1841
1842 #define INT_SEL(x) ((x) << 24)
1843
1844
1845
1846
1847 #define DST_SEL(x) ((x) << 16)
1848
1849
1850
1851 #define PACKET3_EVENT_WRITE_EOS 0x48
1852 #define PACKET3_RELEASE_MEM 0x49
1853 #define PACKET3_PREAMBLE_CNTL 0x4A
1854 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1855 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1856 #define PACKET3_DMA_DATA 0x50
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
1867
1868
1869
1870 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
1871
1872
1873
1874
1875 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
1876 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
1877
1878
1879
1880
1881 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
1882
1883
1884
1885
1886 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
1887 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
1888
1889
1890
1891
1892
1893 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
1894
1895 # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
1896 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
1897
1898
1899
1900
1901
1902 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
1903
1904
1905
1906
1907
1908 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
1909
1910
1911
1912 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
1913
1914
1915
1916 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
1917 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
1918 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
1919 #define PACKET3_AQUIRE_MEM 0x58
1920 #define PACKET3_REWIND 0x59
1921 #define PACKET3_LOAD_UCONFIG_REG 0x5E
1922 #define PACKET3_LOAD_SH_REG 0x5F
1923 #define PACKET3_LOAD_CONFIG_REG 0x60
1924 #define PACKET3_LOAD_CONTEXT_REG 0x61
1925 #define PACKET3_SET_CONFIG_REG 0x68
1926 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1927 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1928 #define PACKET3_SET_CONTEXT_REG 0x69
1929 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1930 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1931 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1932 #define PACKET3_SET_SH_REG 0x76
1933 #define PACKET3_SET_SH_REG_START 0x0000b000
1934 #define PACKET3_SET_SH_REG_END 0x0000c000
1935 #define PACKET3_SET_SH_REG_OFFSET 0x77
1936 #define PACKET3_SET_QUEUE_REG 0x78
1937 #define PACKET3_SET_UCONFIG_REG 0x79
1938 #define PACKET3_SET_UCONFIG_REG_START 0x00030000
1939 #define PACKET3_SET_UCONFIG_REG_END 0x00031000
1940 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1941 #define PACKET3_SCRATCH_RAM_READ 0x7E
1942 #define PACKET3_LOAD_CONST_RAM 0x80
1943 #define PACKET3_WRITE_CONST_RAM 0x81
1944 #define PACKET3_DUMP_CONST_RAM 0x83
1945 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1946 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1947 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1948 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1949 #define PACKET3_SWITCH_BUFFER 0x8B
1950
1951
1952 #define SDMA0_REGISTER_OFFSET 0x0
1953 #define SDMA1_REGISTER_OFFSET 0x800
1954
1955 #define SDMA0_UCODE_ADDR 0xD000
1956 #define SDMA0_UCODE_DATA 0xD004
1957 #define SDMA0_POWER_CNTL 0xD008
1958 #define SDMA0_CLK_CTRL 0xD00C
1959
1960 #define SDMA0_CNTL 0xD010
1961 # define TRAP_ENABLE (1 << 0)
1962 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1963 # define SEM_WAIT_INT_ENABLE (1 << 2)
1964 # define DATA_SWAP_ENABLE (1 << 3)
1965 # define FENCE_SWAP_ENABLE (1 << 4)
1966 # define AUTO_CTXSW_ENABLE (1 << 18)
1967 # define CTXEMPTY_INT_ENABLE (1 << 28)
1968
1969 #define SDMA0_TILING_CONFIG 0xD018
1970
1971 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
1972 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
1973
1974 #define SDMA0_STATUS_REG 0xd034
1975 # define SDMA_IDLE (1 << 0)
1976
1977 #define SDMA0_ME_CNTL 0xD048
1978 # define SDMA_HALT (1 << 0)
1979
1980 #define SDMA0_GFX_RB_CNTL 0xD200
1981 # define SDMA_RB_ENABLE (1 << 0)
1982 # define SDMA_RB_SIZE(x) ((x) << 1)
1983 # define SDMA_RB_SWAP_ENABLE (1 << 9)
1984 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1985 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13)
1986 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16)
1987 #define SDMA0_GFX_RB_BASE 0xD204
1988 #define SDMA0_GFX_RB_BASE_HI 0xD208
1989 #define SDMA0_GFX_RB_RPTR 0xD20C
1990 #define SDMA0_GFX_RB_WPTR 0xD210
1991
1992 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
1993 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
1994 #define SDMA0_GFX_IB_CNTL 0xD228
1995 # define SDMA_IB_ENABLE (1 << 0)
1996 # define SDMA_IB_SWAP_ENABLE (1 << 4)
1997 # define SDMA_SWITCH_INSIDE_IB (1 << 8)
1998 # define SDMA_CMD_VMID(x) ((x) << 16)
1999
2000 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
2001 #define SDMA0_GFX_APE1_CNTL 0xD2A0
2002
2003 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
2004 (((sub_op) & 0xFF) << 8) | \
2005 (((op) & 0xFF) << 0))
2006
2007 #define SDMA_OPCODE_NOP 0
2008 #define SDMA_OPCODE_COPY 1
2009 # define SDMA_COPY_SUB_OPCODE_LINEAR 0
2010 # define SDMA_COPY_SUB_OPCODE_TILED 1
2011 # define SDMA_COPY_SUB_OPCODE_SOA 3
2012 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
2013 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
2014 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
2015 #define SDMA_OPCODE_WRITE 2
2016 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
2017 # define SDMA_WRITE_SUB_OPCODE_TILED 1
2018 #define SDMA_OPCODE_INDIRECT_BUFFER 4
2019 #define SDMA_OPCODE_FENCE 5
2020 #define SDMA_OPCODE_TRAP 6
2021 #define SDMA_OPCODE_SEMAPHORE 7
2022 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
2023
2024
2025
2026 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
2027
2028
2029
2030 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
2031
2032 #define SDMA_OPCODE_POLL_REG_MEM 8
2033 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
2034
2035
2036
2037 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
2038
2039
2040
2041
2042
2043
2044
2045
2046 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
2047
2048
2049
2050 #define SDMA_OPCODE_COND_EXEC 9
2051 #define SDMA_OPCODE_CONSTANT_FILL 11
2052 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
2053
2054
2055
2056 #define SDMA_OPCODE_GENERATE_PTE_PDE 12
2057 #define SDMA_OPCODE_TIMESTAMP 13
2058 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
2059 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
2060 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
2061 #define SDMA_OPCODE_SRBM_WRITE 14
2062 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
2063
2064
2065
2066
2067 #define UVD_UDEC_ADDR_CONFIG 0xef4c
2068 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
2069 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
2070 #define UVD_NO_OP 0xeffc
2071
2072 #define UVD_LMI_EXT40_ADDR 0xf498
2073 #define UVD_GP_SCRATCH4 0xf4e0
2074 #define UVD_LMI_ADDR_EXT 0xf594
2075 #define UVD_VCPU_CACHE_OFFSET0 0xf608
2076 #define UVD_VCPU_CACHE_SIZE0 0xf60c
2077 #define UVD_VCPU_CACHE_OFFSET1 0xf610
2078 #define UVD_VCPU_CACHE_SIZE1 0xf614
2079 #define UVD_VCPU_CACHE_OFFSET2 0xf618
2080 #define UVD_VCPU_CACHE_SIZE2 0xf61c
2081
2082 #define UVD_RBC_RB_RPTR 0xf690
2083 #define UVD_RBC_RB_WPTR 0xf694
2084
2085 #define UVD_CGC_CTRL 0xF4B0
2086 # define DCM (1 << 0)
2087 # define CG_DT(x) ((x) << 2)
2088 # define CG_DT_MASK (0xf << 2)
2089 # define CLK_OD(x) ((x) << 6)
2090 # define CLK_OD_MASK (0x1f << 6)
2091
2092 #define UVD_STATUS 0xf6bc
2093
2094
2095
2096 #define CG_DCLK_CNTL 0xC050009C
2097 # define DCLK_DIVIDER_MASK 0x7f
2098 # define DCLK_DIR_CNTL_EN (1 << 8)
2099 #define CG_DCLK_STATUS 0xC05000A0
2100 # define DCLK_STATUS (1 << 0)
2101 #define CG_VCLK_CNTL 0xC05000A4
2102 #define CG_VCLK_STATUS 0xC05000A8
2103
2104
2105 #define UVD_CGC_MEM_CTRL 0xC0
2106
2107
2108
2109 #define VCE_VCPU_CACHE_OFFSET0 0x20024
2110 #define VCE_VCPU_CACHE_SIZE0 0x20028
2111 #define VCE_VCPU_CACHE_OFFSET1 0x2002c
2112 #define VCE_VCPU_CACHE_SIZE1 0x20030
2113 #define VCE_VCPU_CACHE_OFFSET2 0x20034
2114 #define VCE_VCPU_CACHE_SIZE2 0x20038
2115 #define VCE_RB_RPTR2 0x20178
2116 #define VCE_RB_WPTR2 0x2017c
2117 #define VCE_RB_RPTR 0x2018c
2118 #define VCE_RB_WPTR 0x20190
2119 #define VCE_CLOCK_GATING_A 0x202f8
2120 # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0)
2121 # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0)
2122 # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4)
2123 # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4)
2124 # define CGC_UENC_WAIT_AWAKE (1 << 18)
2125 #define VCE_CLOCK_GATING_B 0x202fc
2126 #define VCE_CGTT_CLK_OVERRIDE 0x207a0
2127 #define VCE_UENC_CLOCK_GATING 0x207bc
2128 # define CLOCK_ON_DELAY_MASK (0xf << 0)
2129 # define CLOCK_ON_DELAY(x) ((x) << 0)
2130 # define CLOCK_OFF_DELAY_MASK (0xff << 4)
2131 # define CLOCK_OFF_DELAY(x) ((x) << 4)
2132 #define VCE_UENC_REG_CLOCK_GATING 0x207c0
2133 #define VCE_SYS_INT_EN 0x21300
2134 # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
2135 #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
2136 #define VCE_LMI_CTRL2 0x21474
2137 #define VCE_LMI_CTRL 0x21498
2138 #define VCE_LMI_VM_CTRL 0x214a0
2139 #define VCE_LMI_SWAP_CNTL 0x214b4
2140 #define VCE_LMI_SWAP_CNTL1 0x214b8
2141 #define VCE_LMI_CACHE_CTRL 0x214f4
2142
2143 #define VCE_CMD_NO_OP 0x00000000
2144 #define VCE_CMD_END 0x00000001
2145 #define VCE_CMD_IB 0x00000002
2146 #define VCE_CMD_FENCE 0x00000003
2147 #define VCE_CMD_TRAP 0x00000004
2148 #define VCE_CMD_IB_AUTO 0x00000005
2149 #define VCE_CMD_SEMAPHORE 0x00000006
2150
2151 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u
2152 #define ATC_VMID0_PASID_MAPPING 0x339Cu
2153 #define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF)
2154 #define ATC_VMID_PASID_MAPPING_PASID_SHIFT 0
2155 #define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31)
2156 #define ATC_VMID_PASID_MAPPING_VALID_SHIFT 31
2157
2158 #define ATC_VM_APERTURE0_CNTL 0x3310u
2159 #define ATS_ACCESS_MODE_NEVER 0
2160 #define ATS_ACCESS_MODE_ALWAYS 1
2161
2162 #define ATC_VM_APERTURE0_CNTL2 0x3318u
2163 #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u
2164 #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u
2165 #define ATC_VM_APERTURE1_CNTL 0x3314u
2166 #define ATC_VM_APERTURE1_CNTL2 0x331Cu
2167 #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu
2168 #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u
2169
2170 #define IH_VMID_0_LUT 0x3D40u
2171
2172 #endif