drivers/gpu/drm/radeon/radeon

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   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __RADEON_UCODE_H__
  24 #define __RADEON_UCODE_H__
  25 
  26 /* CP */
  27 #define R600_PFP_UCODE_SIZE          576
  28 #define R600_PM4_UCODE_SIZE          1792
  29 #define R700_PFP_UCODE_SIZE          848
  30 #define R700_PM4_UCODE_SIZE          1360
  31 #define EVERGREEN_PFP_UCODE_SIZE     1120
  32 #define EVERGREEN_PM4_UCODE_SIZE     1376
  33 #define CAYMAN_PFP_UCODE_SIZE        2176
  34 #define CAYMAN_PM4_UCODE_SIZE        2176
  35 #define SI_PFP_UCODE_SIZE            2144
  36 #define SI_PM4_UCODE_SIZE            2144
  37 #define SI_CE_UCODE_SIZE             2144
  38 #define CIK_PFP_UCODE_SIZE           2144
  39 #define CIK_ME_UCODE_SIZE            2144
  40 #define CIK_CE_UCODE_SIZE            2144
  41 
  42 /* MEC */
  43 #define CIK_MEC_UCODE_SIZE           4192
  44 
  45 /* RLC */
  46 #define R600_RLC_UCODE_SIZE          768
  47 #define R700_RLC_UCODE_SIZE          1024
  48 #define EVERGREEN_RLC_UCODE_SIZE     768
  49 #define CAYMAN_RLC_UCODE_SIZE        1024
  50 #define ARUBA_RLC_UCODE_SIZE         1536
  51 #define SI_RLC_UCODE_SIZE            2048
  52 #define BONAIRE_RLC_UCODE_SIZE       2048
  53 #define KB_RLC_UCODE_SIZE            2560
  54 #define KV_RLC_UCODE_SIZE            2560
  55 #define ML_RLC_UCODE_SIZE            2560
  56 
  57 /* MC */
  58 #define BTC_MC_UCODE_SIZE            6024
  59 #define CAYMAN_MC_UCODE_SIZE         6037
  60 #define SI_MC_UCODE_SIZE             7769
  61 #define TAHITI_MC_UCODE_SIZE         7808
  62 #define PITCAIRN_MC_UCODE_SIZE       7775
  63 #define VERDE_MC_UCODE_SIZE          7875
  64 #define OLAND_MC_UCODE_SIZE          7863
  65 #define BONAIRE_MC_UCODE_SIZE        7866
  66 #define BONAIRE_MC2_UCODE_SIZE       7948
  67 #define HAWAII_MC_UCODE_SIZE         7933
  68 #define HAWAII_MC2_UCODE_SIZE        8091
  69 
  70 /* SDMA */
  71 #define CIK_SDMA_UCODE_SIZE          1050
  72 #define CIK_SDMA_UCODE_VERSION       64
  73 
  74 /* SMC */
  75 #define RV770_SMC_UCODE_START        0x0100
  76 #define RV770_SMC_UCODE_SIZE         0x410d
  77 #define RV770_SMC_INT_VECTOR_START   0xffc0
  78 #define RV770_SMC_INT_VECTOR_SIZE    0x0040
  79 
  80 #define RV730_SMC_UCODE_START        0x0100
  81 #define RV730_SMC_UCODE_SIZE         0x412c
  82 #define RV730_SMC_INT_VECTOR_START   0xffc0
  83 #define RV730_SMC_INT_VECTOR_SIZE    0x0040
  84 
  85 #define RV710_SMC_UCODE_START        0x0100
  86 #define RV710_SMC_UCODE_SIZE         0x3f1f
  87 #define RV710_SMC_INT_VECTOR_START   0xffc0
  88 #define RV710_SMC_INT_VECTOR_SIZE    0x0040
  89 
  90 #define RV740_SMC_UCODE_START        0x0100
  91 #define RV740_SMC_UCODE_SIZE         0x41c5
  92 #define RV740_SMC_INT_VECTOR_START   0xffc0
  93 #define RV740_SMC_INT_VECTOR_SIZE    0x0040
  94 
  95 #define CEDAR_SMC_UCODE_START        0x0100
  96 #define CEDAR_SMC_UCODE_SIZE         0x5d50
  97 #define CEDAR_SMC_INT_VECTOR_START   0xffc0
  98 #define CEDAR_SMC_INT_VECTOR_SIZE    0x0040
  99 
 100 #define REDWOOD_SMC_UCODE_START      0x0100
 101 #define REDWOOD_SMC_UCODE_SIZE       0x5f0a
 102 #define REDWOOD_SMC_INT_VECTOR_START 0xffc0
 103 #define REDWOOD_SMC_INT_VECTOR_SIZE  0x0040
 104 
 105 #define JUNIPER_SMC_UCODE_START      0x0100
 106 #define JUNIPER_SMC_UCODE_SIZE       0x5f1f
 107 #define JUNIPER_SMC_INT_VECTOR_START 0xffc0
 108 #define JUNIPER_SMC_INT_VECTOR_SIZE  0x0040
 109 
 110 #define CYPRESS_SMC_UCODE_START      0x0100
 111 #define CYPRESS_SMC_UCODE_SIZE       0x61f7
 112 #define CYPRESS_SMC_INT_VECTOR_START 0xffc0
 113 #define CYPRESS_SMC_INT_VECTOR_SIZE  0x0040
 114 
 115 #define BARTS_SMC_UCODE_START        0x0100
 116 #define BARTS_SMC_UCODE_SIZE         0x6107
 117 #define BARTS_SMC_INT_VECTOR_START   0xffc0
 118 #define BARTS_SMC_INT_VECTOR_SIZE    0x0040
 119 
 120 #define TURKS_SMC_UCODE_START        0x0100
 121 #define TURKS_SMC_UCODE_SIZE         0x605b
 122 #define TURKS_SMC_INT_VECTOR_START   0xffc0
 123 #define TURKS_SMC_INT_VECTOR_SIZE    0x0040
 124 
 125 #define CAICOS_SMC_UCODE_START       0x0100
 126 #define CAICOS_SMC_UCODE_SIZE        0x5fbd
 127 #define CAICOS_SMC_INT_VECTOR_START  0xffc0
 128 #define CAICOS_SMC_INT_VECTOR_SIZE   0x0040
 129 
 130 #define CAYMAN_SMC_UCODE_START       0x0100
 131 #define CAYMAN_SMC_UCODE_SIZE        0x79ec
 132 #define CAYMAN_SMC_INT_VECTOR_START  0xffc0
 133 #define CAYMAN_SMC_INT_VECTOR_SIZE   0x0040
 134 
 135 #define TAHITI_SMC_UCODE_START       0x10000
 136 #define TAHITI_SMC_UCODE_SIZE        0xf458
 137 
 138 #define PITCAIRN_SMC_UCODE_START     0x10000
 139 #define PITCAIRN_SMC_UCODE_SIZE      0xe9f4
 140 
 141 #define VERDE_SMC_UCODE_START        0x10000
 142 #define VERDE_SMC_UCODE_SIZE         0xebe4
 143 
 144 #define OLAND_SMC_UCODE_START        0x10000
 145 #define OLAND_SMC_UCODE_SIZE         0xe7b4
 146 
 147 #define HAINAN_SMC_UCODE_START       0x10000
 148 #define HAINAN_SMC_UCODE_SIZE        0xe67C
 149 
 150 #define BONAIRE_SMC_UCODE_START      0x20000
 151 #define BONAIRE_SMC_UCODE_SIZE       0x1FDEC
 152 
 153 #define HAWAII_SMC_UCODE_START       0x20000
 154 #define HAWAII_SMC_UCODE_SIZE        0x1FDEC
 155 
 156 struct common_firmware_header {
 157         uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
 158         uint32_t header_size_bytes; /* size of just the header in bytes */
 159         uint16_t header_version_major; /* header version */
 160         uint16_t header_version_minor; /* header version */
 161         uint16_t ip_version_major; /* IP version */
 162         uint16_t ip_version_minor; /* IP version */
 163         uint32_t ucode_version;
 164         uint32_t ucode_size_bytes; /* size of ucode in bytes */
 165         uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
 166         uint32_t crc32;  /* crc32 checksum of the payload */
 167 };
 168 
 169 /* version_major=1, version_minor=0 */
 170 struct mc_firmware_header_v1_0 {
 171         struct common_firmware_header header;
 172         uint32_t io_debug_size_bytes; /* size of debug array in dwords */
 173         uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
 174 };
 175 
 176 /* version_major=1, version_minor=0 */
 177 struct smc_firmware_header_v1_0 {
 178         struct common_firmware_header header;
 179         uint32_t ucode_start_addr;
 180 };
 181 
 182 /* version_major=1, version_minor=0 */
 183 struct gfx_firmware_header_v1_0 {
 184         struct common_firmware_header header;
 185         uint32_t ucode_feature_version;
 186         uint32_t jt_offset; /* jt location */
 187         uint32_t jt_size;  /* size of jt */
 188 };
 189 
 190 /* version_major=1, version_minor=0 */
 191 struct rlc_firmware_header_v1_0 {
 192         struct common_firmware_header header;
 193         uint32_t ucode_feature_version;
 194         uint32_t save_and_restore_offset;
 195         uint32_t clear_state_descriptor_offset;
 196         uint32_t avail_scratch_ram_locations;
 197         uint32_t master_pkt_description_offset;
 198 };
 199 
 200 /* version_major=1, version_minor=0 */
 201 struct sdma_firmware_header_v1_0 {
 202         struct common_firmware_header header;
 203         uint32_t ucode_feature_version;
 204         uint32_t ucode_change_version;
 205         uint32_t jt_offset; /* jt location */
 206         uint32_t jt_size; /* size of jt */
 207 };
 208 
 209 /* header is fixed size */
 210 union radeon_firmware_header {
 211         struct common_firmware_header common;
 212         struct mc_firmware_header_v1_0 mc;
 213         struct smc_firmware_header_v1_0 smc;
 214         struct gfx_firmware_header_v1_0 gfx;
 215         struct rlc_firmware_header_v1_0 rlc;
 216         struct sdma_firmware_header_v1_0 sdma;
 217         uint8_t raw[0x100];
 218 };
 219 
 220 void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 221 void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 222 void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 223 void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 224 void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 225 int radeon_ucode_validate(const struct firmware *fw);
 226 
 227 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/radeon/radeon_ucode.h

INCLUDED FROM
