drivers/gpu/drm/radeon/r600.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
r600_rcu_rreg
r600_rcu_wreg
r600_uvd_ctx_rreg
r600_uvd_ctx_wreg
r600_get_allowed_info_register
r600_get_xclk
r600_set_uvd_clocks
dce3_program_fmt
rv6xx_get_temp
r600_pm_get_dynpm_state
rs780_pm_init_profile
r600_pm_init_profile
r600_pm_misc
r600_gui_idle
r600_hpd_sense
r600_hpd_set_polarity
r600_hpd_init
r600_hpd_fini
r600_pcie_gart_tlb_flush
r600_pcie_gart_init
r600_pcie_gart_enable
r600_pcie_gart_disable
r600_pcie_gart_fini
r600_agp_enable
r600_mc_wait_for_idle
rs780_mc_rreg
rs780_mc_wreg
r600_mc_program
r600_vram_gtt_location
r600_mc_init
r600_vram_scratch_init
r600_vram_scratch_fini
r600_set_bios_scratch_engine_hung
r600_print_gpu_status_regs
r600_is_display_hung
r600_gpu_check_soft_reset
r600_gpu_soft_reset
r600_gpu_pci_config_reset
r600_asic_reset
r600_gfx_is_lockup
r6xx_remap_render_backend
r600_count_pipe_bits
r600_gpu_init
r600_pciep_rreg
r600_pciep_wreg
r600_cp_stop
r600_init_microcode
r600_gfx_get_rptr
r600_gfx_get_wptr
r600_gfx_set_wptr
r600_cp_load_microcode
r600_cp_start
r600_cp_resume
r600_ring_init
r600_cp_fini
r600_scratch_init
r600_ring_test
r600_fence_ring_emit
r600_semaphore_ring_emit
r600_copy_cpdma
r600_set_surface_reg
r600_clear_surface_reg
r600_uvd_init
r600_uvd_start
r600_uvd_resume
r600_startup
r600_vga_set_state
r600_resume
r600_suspend
r600_init
r600_fini
r600_ring_ib_execute
r600_ib_test
r600_ih_ring_init
r600_ih_ring_alloc
r600_ih_ring_fini
r600_rlc_stop
r600_rlc_start
r600_rlc_resume
r600_enable_interrupts
r600_disable_interrupts
r600_disable_interrupt_state
r600_irq_init
r600_irq_suspend
r600_irq_fini
r600_irq_set
r600_irq_ack
r600_irq_disable
r600_get_ih_wptr
r600_irq_process
r600_debugfs_mc_info
r600_debugfs_mc_info_init
r600_mmio_hdp_flush
r600_set_pcie_lanes
r600_get_pcie_lanes
r600_pcie_gen2_enable
r600_get_gpu_clock_counter
   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 
  29 #include <linux/slab.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 
  34 #include <drm/drm_debugfs.h>
  35 #include <drm/drm_device.h>
  36 #include <drm/drm_pci.h>
  37 #include <drm/drm_vblank.h>
  38 #include <drm/radeon_drm.h>
  39 
  40 #include "atom.h"
  41 #include "avivod.h"
  42 #include "r600d.h"
  43 #include "radeon.h"
  44 #include "radeon_asic.h"
  45 #include "radeon_audio.h"
  46 #include "radeon_mode.h"
  47 #include "radeon_ucode.h"
  48 
  49 /* Firmware Names */
  50 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  51 MODULE_FIRMWARE("radeon/R600_me.bin");
  52 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  53 MODULE_FIRMWARE("radeon/RV610_me.bin");
  54 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV630_me.bin");
  56 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV620_me.bin");
  58 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV635_me.bin");
  60 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV670_me.bin");
  62 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RS780_me.bin");
  64 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV770_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_smc.bin");
  67 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RV730_me.bin");
  69 MODULE_FIRMWARE("radeon/RV730_smc.bin");
  70 MODULE_FIRMWARE("radeon/RV740_smc.bin");
  71 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV710_me.bin");
  73 MODULE_FIRMWARE("radeon/RV710_smc.bin");
  74 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  75 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  79 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  83 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  85 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  86 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  87 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
  88 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  89 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  90 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  91 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
  92 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  93 MODULE_FIRMWARE("radeon/PALM_me.bin");
  94 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  95 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  96 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  97 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  98 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  99 
 100 static const u32 crtc_offsets[2] =
 101 {
 102         0,
 103         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
 104 };
 105 
 106 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 107 
 108 /* r600,rv610,rv630,rv620,rv635,rv670 */
 109 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 110 static void r600_gpu_init(struct radeon_device *rdev);
 111 void r600_fini(struct radeon_device *rdev);
 112 void r600_irq_disable(struct radeon_device *rdev);
 113 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 114 extern int evergreen_rlc_resume(struct radeon_device *rdev);
 115 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 116 
 117 /*
 118  * Indirect registers accessor
 119  */
 120 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
 121 {
 122         unsigned long flags;
 123         u32 r;
 124 
 125         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
 126         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
 127         r = RREG32(R600_RCU_DATA);
 128         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
 129         return r;
 130 }
 131 
 132 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 133 {
 134         unsigned long flags;
 135 
 136         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
 137         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
 138         WREG32(R600_RCU_DATA, (v));
 139         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
 140 }
 141 
 142 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
 143 {
 144         unsigned long flags;
 145         u32 r;
 146 
 147         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 148         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 149         r = RREG32(R600_UVD_CTX_DATA);
 150         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 151         return r;
 152 }
 153 
 154 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 155 {
 156         unsigned long flags;
 157 
 158         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 159         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 160         WREG32(R600_UVD_CTX_DATA, (v));
 161         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 162 }
 163 
 164 /**
 165  * r600_get_allowed_info_register - fetch the register for the info ioctl
 166  *
 167  * @rdev: radeon_device pointer
 168  * @reg: register offset in bytes
 169  * @val: register value
 170  *
 171  * Returns 0 for success or -EINVAL for an invalid register
 172  *
 173  */
 174 int r600_get_allowed_info_register(struct radeon_device *rdev,
 175                                    u32 reg, u32 *val)
 176 {
 177         switch (reg) {
 178         case GRBM_STATUS:
 179         case GRBM_STATUS2:
 180         case R_000E50_SRBM_STATUS:
 181         case DMA_STATUS_REG:
 182         case UVD_STATUS:
 183                 *val = RREG32(reg);
 184                 return 0;
 185         default:
 186                 return -EINVAL;
 187         }
 188 }
 189 
 190 /**
 191  * r600_get_xclk - get the xclk
 192  *
 193  * @rdev: radeon_device pointer
 194  *
 195  * Returns the reference clock used by the gfx engine
 196  * (r6xx, IGPs, APUs).
 197  */
 198 u32 r600_get_xclk(struct radeon_device *rdev)
 199 {
 200         return rdev->clock.spll.reference_freq;
 201 }
 202 
 203 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 204 {
 205         unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
 206         int r;
 207 
 208         /* bypass vclk and dclk with bclk */
 209         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 210                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
 211                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 212 
 213         /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
 214         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
 215                  UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
 216 
 217         if (rdev->family >= CHIP_RS780)
 218                 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
 219                          ~UPLL_BYPASS_CNTL);
 220 
 221         if (!vclk || !dclk) {
 222                 /* keep the Bypass mode, put PLL to sleep */
 223                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
 224                 return 0;
 225         }
 226 
 227         if (rdev->clock.spll.reference_freq == 10000)
 228                 ref_div = 34;
 229         else
 230                 ref_div = 4;
 231 
 232         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
 233                                           ref_div + 1, 0xFFF, 2, 30, ~0,
 234                                           &fb_div, &vclk_div, &dclk_div);
 235         if (r)
 236                 return r;
 237 
 238         if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
 239                 fb_div >>= 1;
 240         else
 241                 fb_div |= 1;
 242 
 243         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 244         if (r)
 245                 return r;
 246 
 247         /* assert PLL_RESET */
 248         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
 249 
 250         /* For RS780 we have to choose ref clk */
 251         if (rdev->family >= CHIP_RS780)
 252                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
 253                          ~UPLL_REFCLK_SRC_SEL_MASK);
 254 
 255         /* set the required fb, ref and post divder values */
 256         WREG32_P(CG_UPLL_FUNC_CNTL,
 257                  UPLL_FB_DIV(fb_div) |
 258                  UPLL_REF_DIV(ref_div),
 259                  ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
 260         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 261                  UPLL_SW_HILEN(vclk_div >> 1) |
 262                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
 263                  UPLL_SW_HILEN2(dclk_div >> 1) |
 264                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
 265                  UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
 266                  ~UPLL_SW_MASK);
 267 
 268         /* give the PLL some time to settle */
 269         mdelay(15);
 270 
 271         /* deassert PLL_RESET */
 272         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 273 
 274         mdelay(15);
 275 
 276         /* deassert BYPASS EN */
 277         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 278 
 279         if (rdev->family >= CHIP_RS780)
 280                 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
 281 
 282         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 283         if (r)
 284                 return r;
 285 
 286         /* switch VCLK and DCLK selection */
 287         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 288                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 289                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 290 
 291         mdelay(100);
 292 
 293         return 0;
 294 }
 295 
 296 void dce3_program_fmt(struct drm_encoder *encoder)
 297 {
 298         struct drm_device *dev = encoder->dev;
 299         struct radeon_device *rdev = dev->dev_private;
 300         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 301         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 302         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 303         int bpc = 0;
 304         u32 tmp = 0;
 305         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 306 
 307         if (connector) {
 308                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 309                 bpc = radeon_get_monitor_bpc(connector);
 310                 dither = radeon_connector->dither;
 311         }
 312 
 313         /* LVDS FMT is set up by atom */
 314         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 315                 return;
 316 
 317         /* not needed for analog */
 318         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 319             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 320                 return;
 321 
 322         if (bpc == 0)
 323                 return;
 324 
 325         switch (bpc) {
 326         case 6:
 327                 if (dither == RADEON_FMT_DITHER_ENABLE)
 328                         /* XXX sort out optimal dither settings */
 329                         tmp |= FMT_SPATIAL_DITHER_EN;
 330                 else
 331                         tmp |= FMT_TRUNCATE_EN;
 332                 break;
 333         case 8:
 334                 if (dither == RADEON_FMT_DITHER_ENABLE)
 335                         /* XXX sort out optimal dither settings */
 336                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 337                 else
 338                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 339                 break;
 340         case 10:
 341         default:
 342                 /* not needed */
 343                 break;
 344         }
 345 
 346         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 347 }
 348 
 349 /* get temperature in millidegrees */
 350 int rv6xx_get_temp(struct radeon_device *rdev)
 351 {
 352         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 353                 ASIC_T_SHIFT;
 354         int actual_temp = temp & 0xff;
 355 
 356         if (temp & 0x100)
 357                 actual_temp -= 256;
 358 
 359         return actual_temp * 1000;
 360 }
 361 
 362 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 363 {
 364         int i;
 365 
 366         rdev->pm.dynpm_can_upclock = true;
 367         rdev->pm.dynpm_can_downclock = true;
 368 
 369         /* power state array is low to high, default is first */
 370         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 371                 int min_power_state_index = 0;
 372 
 373                 if (rdev->pm.num_power_states > 2)
 374                         min_power_state_index = 1;
 375 
 376                 switch (rdev->pm.dynpm_planned_action) {
 377                 case DYNPM_ACTION_MINIMUM:
 378                         rdev->pm.requested_power_state_index = min_power_state_index;
 379                         rdev->pm.requested_clock_mode_index = 0;
 380                         rdev->pm.dynpm_can_downclock = false;
 381                         break;
 382                 case DYNPM_ACTION_DOWNCLOCK:
 383                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 384                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 385                                 rdev->pm.dynpm_can_downclock = false;
 386                         } else {
 387                                 if (rdev->pm.active_crtc_count > 1) {
 388                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 389                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 390                                                         continue;
 391                                                 else if (i >= rdev->pm.current_power_state_index) {
 392                                                         rdev->pm.requested_power_state_index =
 393                                                                 rdev->pm.current_power_state_index;
 394                                                         break;
 395                                                 } else {
 396                                                         rdev->pm.requested_power_state_index = i;
 397                                                         break;
 398                                                 }
 399                                         }
 400                                 } else {
 401                                         if (rdev->pm.current_power_state_index == 0)
 402                                                 rdev->pm.requested_power_state_index =
 403                                                         rdev->pm.num_power_states - 1;
 404                                         else
 405                                                 rdev->pm.requested_power_state_index =
 406                                                         rdev->pm.current_power_state_index - 1;
 407                                 }
 408                         }
 409                         rdev->pm.requested_clock_mode_index = 0;
 410                         /* don't use the power state if crtcs are active and no display flag is set */
 411                         if ((rdev->pm.active_crtc_count > 0) &&
 412                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 413                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 414                              RADEON_PM_MODE_NO_DISPLAY)) {
 415                                 rdev->pm.requested_power_state_index++;
 416                         }
 417                         break;
 418                 case DYNPM_ACTION_UPCLOCK:
 419                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 420                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 421                                 rdev->pm.dynpm_can_upclock = false;
 422                         } else {
 423                                 if (rdev->pm.active_crtc_count > 1) {
 424                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 425                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 426                                                         continue;
 427                                                 else if (i <= rdev->pm.current_power_state_index) {
 428                                                         rdev->pm.requested_power_state_index =
 429                                                                 rdev->pm.current_power_state_index;
 430                                                         break;
 431                                                 } else {
 432                                                         rdev->pm.requested_power_state_index = i;
 433                                                         break;
 434                                                 }
 435                                         }
 436                                 } else
 437                                         rdev->pm.requested_power_state_index =
 438                                                 rdev->pm.current_power_state_index + 1;
 439                         }
 440                         rdev->pm.requested_clock_mode_index = 0;
 441                         break;
 442                 case DYNPM_ACTION_DEFAULT:
 443                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 444                         rdev->pm.requested_clock_mode_index = 0;
 445                         rdev->pm.dynpm_can_upclock = false;
 446                         break;
 447                 case DYNPM_ACTION_NONE:
 448                 default:
 449                         DRM_ERROR("Requested mode for not defined action\n");
 450                         return;
 451                 }
 452         } else {
 453                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 454                 /* for now just select the first power state and switch between clock modes */
 455                 /* power state array is low to high, default is first (0) */
 456                 if (rdev->pm.active_crtc_count > 1) {
 457                         rdev->pm.requested_power_state_index = -1;
 458                         /* start at 1 as we don't want the default mode */
 459                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 460                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 461                                         continue;
 462                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 463                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 464                                         rdev->pm.requested_power_state_index = i;
 465                                         break;
 466                                 }
 467                         }
 468                         /* if nothing selected, grab the default state. */
 469                         if (rdev->pm.requested_power_state_index == -1)
 470                                 rdev->pm.requested_power_state_index = 0;
 471                 } else
 472                         rdev->pm.requested_power_state_index = 1;
 473 
 474                 switch (rdev->pm.dynpm_planned_action) {
 475                 case DYNPM_ACTION_MINIMUM:
 476                         rdev->pm.requested_clock_mode_index = 0;
 477                         rdev->pm.dynpm_can_downclock = false;
 478                         break;
 479                 case DYNPM_ACTION_DOWNCLOCK:
 480                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 481                                 if (rdev->pm.current_clock_mode_index == 0) {
 482                                         rdev->pm.requested_clock_mode_index = 0;
 483                                         rdev->pm.dynpm_can_downclock = false;
 484                                 } else
 485                                         rdev->pm.requested_clock_mode_index =
 486                                                 rdev->pm.current_clock_mode_index - 1;
 487                         } else {
 488                                 rdev->pm.requested_clock_mode_index = 0;
 489                                 rdev->pm.dynpm_can_downclock = false;
 490                         }
 491                         /* don't use the power state if crtcs are active and no display flag is set */
 492                         if ((rdev->pm.active_crtc_count > 0) &&
 493                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 494                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 495                              RADEON_PM_MODE_NO_DISPLAY)) {
 496                                 rdev->pm.requested_clock_mode_index++;
 497                         }
 498                         break;
 499                 case DYNPM_ACTION_UPCLOCK:
 500                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 501                                 if (rdev->pm.current_clock_mode_index ==
 502                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 503                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 504                                         rdev->pm.dynpm_can_upclock = false;
 505                                 } else
 506                                         rdev->pm.requested_clock_mode_index =
 507                                                 rdev->pm.current_clock_mode_index + 1;
 508                         } else {
 509                                 rdev->pm.requested_clock_mode_index =
 510                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 511                                 rdev->pm.dynpm_can_upclock = false;
 512                         }
 513                         break;
 514                 case DYNPM_ACTION_DEFAULT:
 515                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 516                         rdev->pm.requested_clock_mode_index = 0;
 517                         rdev->pm.dynpm_can_upclock = false;
 518                         break;
 519                 case DYNPM_ACTION_NONE:
 520                 default:
 521                         DRM_ERROR("Requested mode for not defined action\n");
 522                         return;
 523                 }
 524         }
 525 
 526         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 527                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 528                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 529                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 530                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 531                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 532                   pcie_lanes);
 533 }
 534 
 535 void rs780_pm_init_profile(struct radeon_device *rdev)
 536 {
 537         if (rdev->pm.num_power_states == 2) {
 538                 /* default */
 539                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 540                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 541                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 542                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 543                 /* low sh */
 544                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 545                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 546                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 547                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 548                 /* mid sh */
 549                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 550                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 551                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 552                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 553                 /* high sh */
 554                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 555                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 556                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 557                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 558                 /* low mh */
 559                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 560                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 561                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 562                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 563                 /* mid mh */
 564                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 565                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 566                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 567                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 568                 /* high mh */
 569                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 570                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 571                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 572                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 573         } else if (rdev->pm.num_power_states == 3) {
 574                 /* default */
 575                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 576                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 577                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 578                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 579                 /* low sh */
 580                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 581                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 582                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 583                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 584                 /* mid sh */
 585                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 586                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 587                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 588                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 589                 /* high sh */
 590                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 591                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 592                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 593                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 594                 /* low mh */
 595                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 596                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 597                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 598                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 599                 /* mid mh */
 600                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 601                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 602                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 603                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 604                 /* high mh */
 605                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 606                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 607                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 608                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 609         } else {
 610                 /* default */
 611                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 612                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 613                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 614                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 615                 /* low sh */
 616                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 617                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 618                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 619                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 620                 /* mid sh */
 621                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 622                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 623                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 624                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 625                 /* high sh */
 626                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 627                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 628                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 629                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 630                 /* low mh */
 631                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 632                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 633                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 634                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 635                 /* mid mh */
 636                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 637                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 638                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 639                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 640                 /* high mh */
 641                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 642                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 643                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 644                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 645         }
 646 }
 647 
 648 void r600_pm_init_profile(struct radeon_device *rdev)
 649 {
 650         int idx;
 651 
 652         if (rdev->family == CHIP_R600) {
 653                 /* XXX */
 654                 /* default */
 655                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 656                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 657                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 658                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 659                 /* low sh */
 660                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 661                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 662                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 663                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 664                 /* mid sh */
 665                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 666                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 667                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 668                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 669                 /* high sh */
 670                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 671                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 672                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 673                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 674                 /* low mh */
 675                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 676                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 677                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 678                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 679                 /* mid mh */
 680                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 681                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 682                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 683                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 684                 /* high mh */
 685                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 686                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 687                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 688                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 689         } else {
 690                 if (rdev->pm.num_power_states < 4) {
 691                         /* default */
 692                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 693                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 694                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 695                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 696                         /* low sh */
 697                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 698                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 699                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 700                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 701                         /* mid sh */
 702                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 703                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 704                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 705                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 706                         /* high sh */
 707                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 708                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 709                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 710                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 711                         /* low mh */
 712                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 713                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 714                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 715                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 716                         /* low mh */
 717                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 718                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 719                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 720                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 721                         /* high mh */
 722                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 723                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 724                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 725                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 726                 } else {
 727                         /* default */
 728                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 729                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 730                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 731                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 732                         /* low sh */
 733                         if (rdev->flags & RADEON_IS_MOBILITY)
 734                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 735                         else
 736                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 737                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 738                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 739                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 740                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 741                         /* mid sh */
 742                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 743                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 744                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 745                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 746                         /* high sh */
 747                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 748                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 749                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 750                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 751                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 752                         /* low mh */
 753                         if (rdev->flags & RADEON_IS_MOBILITY)
 754                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 755                         else
 756                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 757                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 758                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 759                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 760                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 761                         /* mid mh */
 762                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 763                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 764                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 765                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 766                         /* high mh */
 767                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 768                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 769                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 770                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 771                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 772                 }
 773         }
 774 }
 775 
 776 void r600_pm_misc(struct radeon_device *rdev)
 777 {
 778         int req_ps_idx = rdev->pm.requested_power_state_index;
 779         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 780         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 781         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 782 
 783         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 784                 /* 0xff01 is a flag rather then an actual voltage */
 785                 if (voltage->voltage == 0xff01)
 786                         return;
 787                 if (voltage->voltage != rdev->pm.current_vddc) {
 788                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 789                         rdev->pm.current_vddc = voltage->voltage;
 790                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 791                 }
 792         }
 793 }
 794 
 795 bool r600_gui_idle(struct radeon_device *rdev)
 796 {
 797         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 798                 return false;
 799         else
 800                 return true;
 801 }
 802 
 803 /* hpd for digital panel detect/disconnect */
 804 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 805 {
 806         bool connected = false;
 807 
 808         if (ASIC_IS_DCE3(rdev)) {
 809                 switch (hpd) {
 810                 case RADEON_HPD_1:
 811                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 812                                 connected = true;
 813                         break;
 814                 case RADEON_HPD_2:
 815                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 816                                 connected = true;
 817                         break;
 818                 case RADEON_HPD_3:
 819                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 820                                 connected = true;
 821                         break;
 822                 case RADEON_HPD_4:
 823                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 824                                 connected = true;
 825                         break;
 826                         /* DCE 3.2 */
 827                 case RADEON_HPD_5:
 828                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 829                                 connected = true;
 830                         break;
 831                 case RADEON_HPD_6:
 832                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 833                                 connected = true;
 834                         break;
 835                 default:
 836                         break;
 837                 }
 838         } else {
 839                 switch (hpd) {
 840                 case RADEON_HPD_1:
 841                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 842                                 connected = true;
 843                         break;
 844                 case RADEON_HPD_2:
 845                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 846                                 connected = true;
 847                         break;
 848                 case RADEON_HPD_3:
 849                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 850                                 connected = true;
 851                         break;
 852                 default:
 853                         break;
 854                 }
 855         }
 856         return connected;
 857 }
 858 
 859 void r600_hpd_set_polarity(struct radeon_device *rdev,
 860                            enum radeon_hpd_id hpd)
 861 {
 862         u32 tmp;
 863         bool connected = r600_hpd_sense(rdev, hpd);
 864 
 865         if (ASIC_IS_DCE3(rdev)) {
 866                 switch (hpd) {
 867                 case RADEON_HPD_1:
 868                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 869                         if (connected)
 870                                 tmp &= ~DC_HPDx_INT_POLARITY;
 871                         else
 872                                 tmp |= DC_HPDx_INT_POLARITY;
 873                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 874                         break;
 875                 case RADEON_HPD_2:
 876                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 877                         if (connected)
 878                                 tmp &= ~DC_HPDx_INT_POLARITY;
 879                         else
 880                                 tmp |= DC_HPDx_INT_POLARITY;
 881                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 882                         break;
 883                 case RADEON_HPD_3:
 884                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 885                         if (connected)
 886                                 tmp &= ~DC_HPDx_INT_POLARITY;
 887                         else
 888                                 tmp |= DC_HPDx_INT_POLARITY;
 889                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 890                         break;
 891                 case RADEON_HPD_4:
 892                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 893                         if (connected)
 894                                 tmp &= ~DC_HPDx_INT_POLARITY;
 895                         else
 896                                 tmp |= DC_HPDx_INT_POLARITY;
 897                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 898                         break;
 899                 case RADEON_HPD_5:
 900                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 901                         if (connected)
 902                                 tmp &= ~DC_HPDx_INT_POLARITY;
 903                         else
 904                                 tmp |= DC_HPDx_INT_POLARITY;
 905                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 906                         break;
 907                         /* DCE 3.2 */
 908                 case RADEON_HPD_6:
 909                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 910                         if (connected)
 911                                 tmp &= ~DC_HPDx_INT_POLARITY;
 912                         else
 913                                 tmp |= DC_HPDx_INT_POLARITY;
 914                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 915                         break;
 916                 default:
 917                         break;
 918                 }
 919         } else {
 920                 switch (hpd) {
 921                 case RADEON_HPD_1:
 922                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 923                         if (connected)
 924                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 925                         else
 926                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 927                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 928                         break;
 929                 case RADEON_HPD_2:
 930                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 931                         if (connected)
 932                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 933                         else
 934                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 935                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 936                         break;
 937                 case RADEON_HPD_3:
 938                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 939                         if (connected)
 940                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 941                         else
 942                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 943                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 944                         break;
 945                 default:
 946                         break;
 947                 }
 948         }
 949 }
 950 
 951 void r600_hpd_init(struct radeon_device *rdev)
 952 {
 953         struct drm_device *dev = rdev->ddev;
 954         struct drm_connector *connector;
 955         unsigned enable = 0;
 956 
 957         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 958                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 959 
 960                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 961                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 962                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 963                          * aux dp channel on imac and help (but not completely fix)
 964                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 965                          */
 966                         continue;
 967                 }
 968                 if (ASIC_IS_DCE3(rdev)) {
 969                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 970                         if (ASIC_IS_DCE32(rdev))
 971                                 tmp |= DC_HPDx_EN;
 972 
 973                         switch (radeon_connector->hpd.hpd) {
 974                         case RADEON_HPD_1:
 975                                 WREG32(DC_HPD1_CONTROL, tmp);
 976                                 break;
 977                         case RADEON_HPD_2:
 978                                 WREG32(DC_HPD2_CONTROL, tmp);
 979                                 break;
 980                         case RADEON_HPD_3:
 981                                 WREG32(DC_HPD3_CONTROL, tmp);
 982                                 break;
 983                         case RADEON_HPD_4:
 984                                 WREG32(DC_HPD4_CONTROL, tmp);
 985                                 break;
 986                                 /* DCE 3.2 */
 987                         case RADEON_HPD_5:
 988                                 WREG32(DC_HPD5_CONTROL, tmp);
 989                                 break;
 990                         case RADEON_HPD_6:
 991                                 WREG32(DC_HPD6_CONTROL, tmp);
 992                                 break;
 993                         default:
 994                                 break;
 995                         }
 996                 } else {
 997                         switch (radeon_connector->hpd.hpd) {
 998                         case RADEON_HPD_1:
 999                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1000                                 break;
1001                         case RADEON_HPD_2:
1002                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1003                                 break;
1004                         case RADEON_HPD_3:
1005                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1006                                 break;
1007                         default:
1008                                 break;
1009                         }
1010                 }
1011                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1012                         enable |= 1 << radeon_connector->hpd.hpd;
1013                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1014         }
1015         radeon_irq_kms_enable_hpd(rdev, enable);
1016 }
1017 
1018 void r600_hpd_fini(struct radeon_device *rdev)
1019 {
1020         struct drm_device *dev = rdev->ddev;
1021         struct drm_connector *connector;
1022         unsigned disable = 0;
1023 
1024         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1025                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1026                 if (ASIC_IS_DCE3(rdev)) {
1027                         switch (radeon_connector->hpd.hpd) {
1028                         case RADEON_HPD_1:
1029                                 WREG32(DC_HPD1_CONTROL, 0);
1030                                 break;
1031                         case RADEON_HPD_2:
1032                                 WREG32(DC_HPD2_CONTROL, 0);
1033                                 break;
1034                         case RADEON_HPD_3:
1035                                 WREG32(DC_HPD3_CONTROL, 0);
1036                                 break;
1037                         case RADEON_HPD_4:
1038                                 WREG32(DC_HPD4_CONTROL, 0);
1039                                 break;
1040                                 /* DCE 3.2 */
1041                         case RADEON_HPD_5:
1042                                 WREG32(DC_HPD5_CONTROL, 0);
1043                                 break;
1044                         case RADEON_HPD_6:
1045                                 WREG32(DC_HPD6_CONTROL, 0);
1046                                 break;
1047                         default:
1048                                 break;
1049                         }
1050                 } else {
1051                         switch (radeon_connector->hpd.hpd) {
1052                         case RADEON_HPD_1:
1053                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1054                                 break;
1055                         case RADEON_HPD_2:
1056                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1057                                 break;
1058                         case RADEON_HPD_3:
1059                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1060                                 break;
1061                         default:
1062                                 break;
1063                         }
1064                 }
1065                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1066                         disable |= 1 << radeon_connector->hpd.hpd;
1067         }
1068         radeon_irq_kms_disable_hpd(rdev, disable);
1069 }
1070 
1071 /*
1072  * R600 PCIE GART
1073  */
1074 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1075 {
1076         unsigned i;
1077         u32 tmp;
1078 
1079         /* flush hdp cache so updates hit vram */
1080         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1081             !(rdev->flags & RADEON_IS_AGP)) {
1082                 void __iomem *ptr = (void *)rdev->gart.ptr;
1083                 u32 tmp;
1084 
1085                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
1086                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1087                  * This seems to cause problems on some AGP cards. Just use the old
1088                  * method for them.
1089                  */
1090                 WREG32(HDP_DEBUG1, 0);
1091                 tmp = readl((void __iomem *)ptr);
1092         } else
1093                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1094 
1095         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1096         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1097         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1098         for (i = 0; i < rdev->usec_timeout; i++) {
1099                 /* read MC_STATUS */
1100                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1101                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1102                 if (tmp == 2) {
1103                         pr_warn("[drm] r600 flush TLB failed\n");
1104                         return;
1105                 }
1106                 if (tmp) {
1107                         return;
1108                 }
1109                 udelay(1);
1110         }
1111 }
1112 
1113 int r600_pcie_gart_init(struct radeon_device *rdev)
1114 {
1115         int r;
1116 
1117         if (rdev->gart.robj) {
1118                 WARN(1, "R600 PCIE GART already initialized\n");
1119                 return 0;
1120         }
1121         /* Initialize common gart structure */
1122         r = radeon_gart_init(rdev);
1123         if (r)
1124                 return r;
1125         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1126         return radeon_gart_table_vram_alloc(rdev);
1127 }
1128 
1129 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1130 {
1131         u32 tmp;
1132         int r, i;
1133 
1134         if (rdev->gart.robj == NULL) {
1135                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1136                 return -EINVAL;
1137         }
1138         r = radeon_gart_table_vram_pin(rdev);
1139         if (r)
1140                 return r;
1141 
1142         /* Setup L2 cache */
1143         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1144                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1145                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1146         WREG32(VM_L2_CNTL2, 0);
1147         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1148         /* Setup TLB control */
1149         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1150                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1151                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1152                 ENABLE_WAIT_L2_QUERY;
1153         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1154         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1155         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1156         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1157         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1158         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1159         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1160         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1161         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1162         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1163         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1164         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1165         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1166         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1167         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1168         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1169         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1170         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1171         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1172         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1173                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1174         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1175                         (u32)(rdev->dummy_page.addr >> 12));
1176         for (i = 1; i < 7; i++)
1177                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1178 
1179         r600_pcie_gart_tlb_flush(rdev);
1180         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1181                  (unsigned)(rdev->mc.gtt_size >> 20),
1182                  (unsigned long long)rdev->gart.table_addr);
1183         rdev->gart.ready = true;
1184         return 0;
1185 }
1186 
1187 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1188 {
1189         u32 tmp;
1190         int i;
1191 
1192         /* Disable all tables */
1193         for (i = 0; i < 7; i++)
1194                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1195 
1196         /* Disable L2 cache */
1197         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1198                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1199         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1200         /* Setup L1 TLB control */
1201         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1202                 ENABLE_WAIT_L2_QUERY;
1203         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1204         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1205         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1206         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1207         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1208         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1209         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1210         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1211         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1212         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1213         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1214         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1215         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1216         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1217         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1218         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1219         radeon_gart_table_vram_unpin(rdev);
1220 }
1221 
1222 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1223 {
1224         radeon_gart_fini(rdev);
1225         r600_pcie_gart_disable(rdev);
1226         radeon_gart_table_vram_free(rdev);
1227 }
1228 
1229 static void r600_agp_enable(struct radeon_device *rdev)
1230 {
1231         u32 tmp;
1232         int i;
1233 
1234         /* Setup L2 cache */
1235         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1236                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1237                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1238         WREG32(VM_L2_CNTL2, 0);
1239         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1240         /* Setup TLB control */
1241         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1242                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1243                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1244                 ENABLE_WAIT_L2_QUERY;
1245         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1246         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1247         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1248         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1249         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1250         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1251         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1252         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1253         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1254         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1255         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1256         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1257         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1258         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1259         for (i = 0; i < 7; i++)
1260                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1261 }
1262 
1263 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1264 {
1265         unsigned i;
1266         u32 tmp;
1267 
1268         for (i = 0; i < rdev->usec_timeout; i++) {
1269                 /* read MC_STATUS */
1270                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1271                 if (!tmp)
1272                         return 0;
1273                 udelay(1);
1274         }
1275         return -1;
1276 }
1277 
1278 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1279 {
1280         unsigned long flags;
1281         uint32_t r;
1282 
1283         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1284         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1285         r = RREG32(R_0028FC_MC_DATA);
1286         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1287         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1288         return r;
1289 }
1290 
1291 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1292 {
1293         unsigned long flags;
1294 
1295         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1296         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1297                 S_0028F8_MC_IND_WR_EN(1));
1298         WREG32(R_0028FC_MC_DATA, v);
1299         WREG32(R_0028F8_MC_INDEX, 0x7F);
1300         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1301 }
1302 
1303 static void r600_mc_program(struct radeon_device *rdev)
1304 {
1305         struct rv515_mc_save save;
1306         u32 tmp;
1307         int i, j;
1308 
1309         /* Initialize HDP */
1310         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1311                 WREG32((0x2c14 + j), 0x00000000);
1312                 WREG32((0x2c18 + j), 0x00000000);
1313                 WREG32((0x2c1c + j), 0x00000000);
1314                 WREG32((0x2c20 + j), 0x00000000);
1315                 WREG32((0x2c24 + j), 0x00000000);
1316         }
1317         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1318 
1319         rv515_mc_stop(rdev, &save);
1320         if (r600_mc_wait_for_idle(rdev)) {
1321                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1322         }
1323         /* Lockout access through VGA aperture (doesn't exist before R600) */
1324         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1325         /* Update configuration */
1326         if (rdev->flags & RADEON_IS_AGP) {
1327                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1328                         /* VRAM before AGP */
1329                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1330                                 rdev->mc.vram_start >> 12);
1331                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1332                                 rdev->mc.gtt_end >> 12);
1333                 } else {
1334                         /* VRAM after AGP */
1335                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1336                                 rdev->mc.gtt_start >> 12);
1337                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1338                                 rdev->mc.vram_end >> 12);
1339                 }
1340         } else {
1341                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1342                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1343         }
1344         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1345         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1346         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1347         WREG32(MC_VM_FB_LOCATION, tmp);
1348         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1349         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1350         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1351         if (rdev->flags & RADEON_IS_AGP) {
1352                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1353                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1354                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1355         } else {
1356                 WREG32(MC_VM_AGP_BASE, 0);
1357                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1358                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1359         }
1360         if (r600_mc_wait_for_idle(rdev)) {
1361                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1362         }
1363         rv515_mc_resume(rdev, &save);
1364         /* we need to own VRAM, so turn off the VGA renderer here
1365          * to stop it overwriting our objects */
1366         rv515_vga_render_disable(rdev);
1367 }
1368 
1369 /**
1370  * r600_vram_gtt_location - try to find VRAM & GTT location
1371  * @rdev: radeon device structure holding all necessary informations
1372  * @mc: memory controller structure holding memory informations
1373  *
1374  * Function will place try to place VRAM at same place as in CPU (PCI)
1375  * address space as some GPU seems to have issue when we reprogram at
1376  * different address space.
1377  *
1378  * If there is not enough space to fit the unvisible VRAM after the
1379  * aperture then we limit the VRAM size to the aperture.
1380  *
1381  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1382  * them to be in one from GPU point of view so that we can program GPU to
1383  * catch access outside them (weird GPU policy see ??).
1384  *
1385  * This function will never fails, worst case are limiting VRAM or GTT.
1386  *
1387  * Note: GTT start, end, size should be initialized before calling this
1388  * function on AGP platform.
1389  */
1390 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1391 {
1392         u64 size_bf, size_af;
1393 
1394         if (mc->mc_vram_size > 0xE0000000) {
1395                 /* leave room for at least 512M GTT */
1396                 dev_warn(rdev->dev, "limiting VRAM\n");
1397                 mc->real_vram_size = 0xE0000000;
1398                 mc->mc_vram_size = 0xE0000000;
1399         }
1400         if (rdev->flags & RADEON_IS_AGP) {
1401                 size_bf = mc->gtt_start;
1402                 size_af = mc->mc_mask - mc->gtt_end;
1403                 if (size_bf > size_af) {
1404                         if (mc->mc_vram_size > size_bf) {
1405                                 dev_warn(rdev->dev, "limiting VRAM\n");
1406                                 mc->real_vram_size = size_bf;
1407                                 mc->mc_vram_size = size_bf;
1408                         }
1409                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1410                 } else {
1411                         if (mc->mc_vram_size > size_af) {
1412                                 dev_warn(rdev->dev, "limiting VRAM\n");
1413                                 mc->real_vram_size = size_af;
1414                                 mc->mc_vram_size = size_af;
1415                         }
1416                         mc->vram_start = mc->gtt_end + 1;
1417                 }
1418                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1419                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1420                                 mc->mc_vram_size >> 20, mc->vram_start,
1421                                 mc->vram_end, mc->real_vram_size >> 20);
1422         } else {
1423                 u64 base = 0;
1424                 if (rdev->flags & RADEON_IS_IGP) {
1425                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1426                         base <<= 24;
1427                 }
1428                 radeon_vram_location(rdev, &rdev->mc, base);
1429                 rdev->mc.gtt_base_align = 0;
1430                 radeon_gtt_location(rdev, mc);
1431         }
1432 }
1433 
1434 static int r600_mc_init(struct radeon_device *rdev)
1435 {
1436         u32 tmp;
1437         int chansize, numchan;
1438         uint32_t h_addr, l_addr;
1439         unsigned long long k8_addr;
1440 
1441         /* Get VRAM informations */
1442         rdev->mc.vram_is_ddr = true;
1443         tmp = RREG32(RAMCFG);
1444         if (tmp & CHANSIZE_OVERRIDE) {
1445                 chansize = 16;
1446         } else if (tmp & CHANSIZE_MASK) {
1447                 chansize = 64;
1448         } else {
1449                 chansize = 32;
1450         }
1451         tmp = RREG32(CHMAP);
1452         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1453         case 0:
1454         default:
1455                 numchan = 1;
1456                 break;
1457         case 1:
1458                 numchan = 2;
1459                 break;
1460         case 2:
1461                 numchan = 4;
1462                 break;
1463         case 3:
1464                 numchan = 8;
1465                 break;
1466         }
1467         rdev->mc.vram_width = numchan * chansize;
1468         /* Could aper size report 0 ? */
1469         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1470         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1471         /* Setup GPU memory space */
1472         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1473         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1474         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1475         r600_vram_gtt_location(rdev, &rdev->mc);
1476 
1477         if (rdev->flags & RADEON_IS_IGP) {
1478                 rs690_pm_info(rdev);
1479                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1480 
1481                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1482                         /* Use K8 direct mapping for fast fb access. */
1483                         rdev->fastfb_working = false;
1484                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1485                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1486                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1487 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1488                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1489 #endif
1490                         {
1491                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1492                                 * memory is present.
1493                                 */
1494                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1495                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1496                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1497                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1498                                         rdev->fastfb_working = true;
1499                                 }
1500                         }
1501                 }
1502         }
1503 
1504         radeon_update_bandwidth_info(rdev);
1505         return 0;
1506 }
1507 
1508 int r600_vram_scratch_init(struct radeon_device *rdev)
1509 {
1510         int r;
1511 
1512         if (rdev->vram_scratch.robj == NULL) {
1513                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1514                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1515                                      0, NULL, NULL, &rdev->vram_scratch.robj);
1516                 if (r) {
1517                         return r;
1518                 }
1519         }
1520 
1521         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1522         if (unlikely(r != 0))
1523                 return r;
1524         r = radeon_bo_pin(rdev->vram_scratch.robj,
1525                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1526         if (r) {
1527                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1528                 return r;
1529         }
1530         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1531                                 (void **)&rdev->vram_scratch.ptr);
1532         if (r)
1533                 radeon_bo_unpin(rdev->vram_scratch.robj);
1534         radeon_bo_unreserve(rdev->vram_scratch.robj);
1535 
1536         return r;
1537 }
1538 
1539 void r600_vram_scratch_fini(struct radeon_device *rdev)
1540 {
1541         int r;
1542 
1543         if (rdev->vram_scratch.robj == NULL) {
1544                 return;
1545         }
1546         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1547         if (likely(r == 0)) {
1548                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1549                 radeon_bo_unpin(rdev->vram_scratch.robj);
1550                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1551         }
1552         radeon_bo_unref(&rdev->vram_scratch.robj);
1553 }
1554 
1555 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1556 {
1557         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1558 
1559         if (hung)
1560                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1561         else
1562                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1563 
1564         WREG32(R600_BIOS_3_SCRATCH, tmp);
1565 }
1566 
1567 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1568 {
1569         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1570                  RREG32(R_008010_GRBM_STATUS));
1571         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1572                  RREG32(R_008014_GRBM_STATUS2));
1573         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1574                  RREG32(R_000E50_SRBM_STATUS));
1575         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1576                  RREG32(CP_STALLED_STAT1));
1577         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1578                  RREG32(CP_STALLED_STAT2));
1579         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1580                  RREG32(CP_BUSY_STAT));
1581         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1582                  RREG32(CP_STAT));
1583         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1584                 RREG32(DMA_STATUS_REG));
1585 }
1586 
1587 static bool r600_is_display_hung(struct radeon_device *rdev)
1588 {
1589         u32 crtc_hung = 0;
1590         u32 crtc_status[2];
1591         u32 i, j, tmp;
1592 
1593         for (i = 0; i < rdev->num_crtc; i++) {
1594                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1595                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1596                         crtc_hung |= (1 << i);
1597                 }
1598         }
1599 
1600         for (j = 0; j < 10; j++) {
1601                 for (i = 0; i < rdev->num_crtc; i++) {
1602                         if (crtc_hung & (1 << i)) {
1603                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1604                                 if (tmp != crtc_status[i])
1605                                         crtc_hung &= ~(1 << i);
1606                         }
1607                 }
1608                 if (crtc_hung == 0)
1609                         return false;
1610                 udelay(100);
1611         }
1612 
1613         return true;
1614 }
1615 
1616 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1617 {
1618         u32 reset_mask = 0;
1619         u32 tmp;
1620 
1621         /* GRBM_STATUS */
1622         tmp = RREG32(R_008010_GRBM_STATUS);
1623         if (rdev->family >= CHIP_RV770) {
1624                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1625                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1626                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1627                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1628                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1629                         reset_mask |= RADEON_RESET_GFX;
1630         } else {
1631                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1632                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1633                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1634                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1635                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1636                         reset_mask |= RADEON_RESET_GFX;
1637         }
1638 
1639         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1640             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1641                 reset_mask |= RADEON_RESET_CP;
1642 
1643         if (G_008010_GRBM_EE_BUSY(tmp))
1644                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1645 
1646         /* DMA_STATUS_REG */
1647         tmp = RREG32(DMA_STATUS_REG);
1648         if (!(tmp & DMA_IDLE))
1649                 reset_mask |= RADEON_RESET_DMA;
1650 
1651         /* SRBM_STATUS */
1652         tmp = RREG32(R_000E50_SRBM_STATUS);
1653         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1654                 reset_mask |= RADEON_RESET_RLC;
1655 
1656         if (G_000E50_IH_BUSY(tmp))
1657                 reset_mask |= RADEON_RESET_IH;
1658 
1659         if (G_000E50_SEM_BUSY(tmp))
1660                 reset_mask |= RADEON_RESET_SEM;
1661 
1662         if (G_000E50_GRBM_RQ_PENDING(tmp))
1663                 reset_mask |= RADEON_RESET_GRBM;
1664 
1665         if (G_000E50_VMC_BUSY(tmp))
1666                 reset_mask |= RADEON_RESET_VMC;
1667 
1668         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1669             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1670             G_000E50_MCDW_BUSY(tmp))
1671                 reset_mask |= RADEON_RESET_MC;
1672 
1673         if (r600_is_display_hung(rdev))
1674                 reset_mask |= RADEON_RESET_DISPLAY;
1675 
1676         /* Skip MC reset as it's mostly likely not hung, just busy */
1677         if (reset_mask & RADEON_RESET_MC) {
1678                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1679                 reset_mask &= ~RADEON_RESET_MC;
1680         }
1681 
1682         return reset_mask;
1683 }
1684 
1685 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1686 {
1687         struct rv515_mc_save save;
1688         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1689         u32 tmp;
1690 
1691         if (reset_mask == 0)
1692                 return;
1693 
1694         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1695 
1696         r600_print_gpu_status_regs(rdev);
1697 
1698         /* Disable CP parsing/prefetching */
1699         if (rdev->family >= CHIP_RV770)
1700                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1701         else
1702                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1703 
1704         /* disable the RLC */
1705         WREG32(RLC_CNTL, 0);
1706 
1707         if (reset_mask & RADEON_RESET_DMA) {
1708                 /* Disable DMA */
1709                 tmp = RREG32(DMA_RB_CNTL);
1710                 tmp &= ~DMA_RB_ENABLE;
1711                 WREG32(DMA_RB_CNTL, tmp);
1712         }
1713 
1714         mdelay(50);
1715 
1716         rv515_mc_stop(rdev, &save);
1717         if (r600_mc_wait_for_idle(rdev)) {
1718                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1719         }
1720 
1721         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1722                 if (rdev->family >= CHIP_RV770)
1723                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1724                                 S_008020_SOFT_RESET_CB(1) |
1725                                 S_008020_SOFT_RESET_PA(1) |
1726                                 S_008020_SOFT_RESET_SC(1) |
1727                                 S_008020_SOFT_RESET_SPI(1) |
1728                                 S_008020_SOFT_RESET_SX(1) |
1729                                 S_008020_SOFT_RESET_SH(1) |
1730                                 S_008020_SOFT_RESET_TC(1) |
1731                                 S_008020_SOFT_RESET_TA(1) |
1732                                 S_008020_SOFT_RESET_VC(1) |
1733                                 S_008020_SOFT_RESET_VGT(1);
1734                 else
1735                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1736                                 S_008020_SOFT_RESET_DB(1) |
1737                                 S_008020_SOFT_RESET_CB(1) |
1738                                 S_008020_SOFT_RESET_PA(1) |
1739                                 S_008020_SOFT_RESET_SC(1) |
1740                                 S_008020_SOFT_RESET_SMX(1) |
1741                                 S_008020_SOFT_RESET_SPI(1) |
1742                                 S_008020_SOFT_RESET_SX(1) |
1743                                 S_008020_SOFT_RESET_SH(1) |
1744                                 S_008020_SOFT_RESET_TC(1) |
1745                                 S_008020_SOFT_RESET_TA(1) |
1746                                 S_008020_SOFT_RESET_VC(1) |
1747                                 S_008020_SOFT_RESET_VGT(1);
1748         }
1749 
1750         if (reset_mask & RADEON_RESET_CP) {
1751                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1752                         S_008020_SOFT_RESET_VGT(1);
1753 
1754                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1755         }
1756 
1757         if (reset_mask & RADEON_RESET_DMA) {
1758                 if (rdev->family >= CHIP_RV770)
1759                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1760                 else
1761                         srbm_soft_reset |= SOFT_RESET_DMA;
1762         }
1763 
1764         if (reset_mask & RADEON_RESET_RLC)
1765                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1766 
1767         if (reset_mask & RADEON_RESET_SEM)
1768                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1769 
1770         if (reset_mask & RADEON_RESET_IH)
1771                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1772 
1773         if (reset_mask & RADEON_RESET_GRBM)
1774                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1775 
1776         if (!(rdev->flags & RADEON_IS_IGP)) {
1777                 if (reset_mask & RADEON_RESET_MC)
1778                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1779         }
1780 
1781         if (reset_mask & RADEON_RESET_VMC)
1782                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1783 
1784         if (grbm_soft_reset) {
1785                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1786                 tmp |= grbm_soft_reset;
1787                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1788                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1789                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1790 
1791                 udelay(50);
1792 
1793                 tmp &= ~grbm_soft_reset;
1794                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1795                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1796         }
1797 
1798         if (srbm_soft_reset) {
1799                 tmp = RREG32(SRBM_SOFT_RESET);
1800                 tmp |= srbm_soft_reset;
1801                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1802                 WREG32(SRBM_SOFT_RESET, tmp);
1803                 tmp = RREG32(SRBM_SOFT_RESET);
1804 
1805                 udelay(50);
1806 
1807                 tmp &= ~srbm_soft_reset;
1808                 WREG32(SRBM_SOFT_RESET, tmp);
1809                 tmp = RREG32(SRBM_SOFT_RESET);
1810         }
1811 
1812         /* Wait a little for things to settle down */
1813         mdelay(1);
1814 
1815         rv515_mc_resume(rdev, &save);
1816         udelay(50);
1817 
1818         r600_print_gpu_status_regs(rdev);
1819 }
1820 
1821 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1822 {
1823         struct rv515_mc_save save;
1824         u32 tmp, i;
1825 
1826         dev_info(rdev->dev, "GPU pci config reset\n");
1827 
1828         /* disable dpm? */
1829 
1830         /* Disable CP parsing/prefetching */
1831         if (rdev->family >= CHIP_RV770)
1832                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1833         else
1834                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1835 
1836         /* disable the RLC */
1837         WREG32(RLC_CNTL, 0);
1838 
1839         /* Disable DMA */
1840         tmp = RREG32(DMA_RB_CNTL);
1841         tmp &= ~DMA_RB_ENABLE;
1842         WREG32(DMA_RB_CNTL, tmp);
1843 
1844         mdelay(50);
1845 
1846         /* set mclk/sclk to bypass */
1847         if (rdev->family >= CHIP_RV770)
1848                 rv770_set_clk_bypass_mode(rdev);
1849         /* disable BM */
1850         pci_clear_master(rdev->pdev);
1851         /* disable mem access */
1852         rv515_mc_stop(rdev, &save);
1853         if (r600_mc_wait_for_idle(rdev)) {
1854                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1855         }
1856 
1857         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1858         tmp = RREG32(BUS_CNTL);
1859         tmp |= VGA_COHE_SPEC_TIMER_DIS;
1860         WREG32(BUS_CNTL, tmp);
1861 
1862         tmp = RREG32(BIF_SCRATCH0);
1863 
1864         /* reset */
1865         radeon_pci_config_reset(rdev);
1866         mdelay(1);
1867 
1868         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1869         tmp = SOFT_RESET_BIF;
1870         WREG32(SRBM_SOFT_RESET, tmp);
1871         mdelay(1);
1872         WREG32(SRBM_SOFT_RESET, 0);
1873 
1874         /* wait for asic to come out of reset */
1875         for (i = 0; i < rdev->usec_timeout; i++) {
1876                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1877                         break;
1878                 udelay(1);
1879         }
1880 }
1881 
1882 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1883 {
1884         u32 reset_mask;
1885 
1886         if (hard) {
1887                 r600_gpu_pci_config_reset(rdev);
1888                 return 0;
1889         }
1890 
1891         reset_mask = r600_gpu_check_soft_reset(rdev);
1892 
1893         if (reset_mask)
1894                 r600_set_bios_scratch_engine_hung(rdev, true);
1895 
1896         /* try soft reset */
1897         r600_gpu_soft_reset(rdev, reset_mask);
1898 
1899         reset_mask = r600_gpu_check_soft_reset(rdev);
1900 
1901         /* try pci config reset */
1902         if (reset_mask && radeon_hard_reset)
1903                 r600_gpu_pci_config_reset(rdev);
1904 
1905         reset_mask = r600_gpu_check_soft_reset(rdev);
1906 
1907         if (!reset_mask)
1908                 r600_set_bios_scratch_engine_hung(rdev, false);
1909 
1910         return 0;
1911 }
1912 
1913 /**
1914  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1915  *
1916  * @rdev: radeon_device pointer
1917  * @ring: radeon_ring structure holding ring information
1918  *
1919  * Check if the GFX engine is locked up.
1920  * Returns true if the engine appears to be locked up, false if not.
1921  */
1922 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1923 {
1924         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1925 
1926         if (!(reset_mask & (RADEON_RESET_GFX |
1927                             RADEON_RESET_COMPUTE |
1928                             RADEON_RESET_CP))) {
1929                 radeon_ring_lockup_update(rdev, ring);
1930                 return false;
1931         }
1932         return radeon_ring_test_lockup(rdev, ring);
1933 }
1934 
1935 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1936                               u32 tiling_pipe_num,
1937                               u32 max_rb_num,
1938                               u32 total_max_rb_num,
1939                               u32 disabled_rb_mask)
1940 {
1941         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1942         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1943         u32 data = 0, mask = 1 << (max_rb_num - 1);
1944         unsigned i, j;
1945 
1946         /* mask out the RBs that don't exist on that asic */
1947         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1948         /* make sure at least one RB is available */
1949         if ((tmp & 0xff) != 0xff)
1950                 disabled_rb_mask = tmp;
1951 
1952         rendering_pipe_num = 1 << tiling_pipe_num;
1953         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1954         BUG_ON(rendering_pipe_num < req_rb_num);
1955 
1956         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1957         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1958 
1959         if (rdev->family <= CHIP_RV740) {
1960                 /* r6xx/r7xx */
1961                 rb_num_width = 2;
1962         } else {
1963                 /* eg+ */
1964                 rb_num_width = 4;
1965         }
1966 
1967         for (i = 0; i < max_rb_num; i++) {
1968                 if (!(mask & disabled_rb_mask)) {
1969                         for (j = 0; j < pipe_rb_ratio; j++) {
1970                                 data <<= rb_num_width;
1971                                 data |= max_rb_num - i - 1;
1972                         }
1973                         if (pipe_rb_remain) {
1974                                 data <<= rb_num_width;
1975                                 data |= max_rb_num - i - 1;
1976                                 pipe_rb_remain--;
1977                         }
1978                 }
1979                 mask >>= 1;
1980         }
1981 
1982         return data;
1983 }
1984 
1985 int r600_count_pipe_bits(uint32_t val)
1986 {
1987         return hweight32(val);
1988 }
1989 
1990 static void r600_gpu_init(struct radeon_device *rdev)
1991 {
1992         u32 tiling_config;
1993         u32 ramcfg;
1994         u32 cc_gc_shader_pipe_config;
1995         u32 tmp;
1996         int i, j;
1997         u32 sq_config;
1998         u32 sq_gpr_resource_mgmt_1 = 0;
1999         u32 sq_gpr_resource_mgmt_2 = 0;
2000         u32 sq_thread_resource_mgmt = 0;
2001         u32 sq_stack_resource_mgmt_1 = 0;
2002         u32 sq_stack_resource_mgmt_2 = 0;
2003         u32 disabled_rb_mask;
2004 
2005         rdev->config.r600.tiling_group_size = 256;
2006         switch (rdev->family) {
2007         case CHIP_R600:
2008                 rdev->config.r600.max_pipes = 4;
2009                 rdev->config.r600.max_tile_pipes = 8;
2010                 rdev->config.r600.max_simds = 4;
2011                 rdev->config.r600.max_backends = 4;
2012                 rdev->config.r600.max_gprs = 256;
2013                 rdev->config.r600.max_threads = 192;
2014                 rdev->config.r600.max_stack_entries = 256;
2015                 rdev->config.r600.max_hw_contexts = 8;
2016                 rdev->config.r600.max_gs_threads = 16;
2017                 rdev->config.r600.sx_max_export_size = 128;
2018                 rdev->config.r600.sx_max_export_pos_size = 16;
2019                 rdev->config.r600.sx_max_export_smx_size = 128;
2020                 rdev->config.r600.sq_num_cf_insts = 2;
2021                 break;
2022         case CHIP_RV630:
2023         case CHIP_RV635:
2024                 rdev->config.r600.max_pipes = 2;
2025                 rdev->config.r600.max_tile_pipes = 2;
2026                 rdev->config.r600.max_simds = 3;
2027                 rdev->config.r600.max_backends = 1;
2028                 rdev->config.r600.max_gprs = 128;
2029                 rdev->config.r600.max_threads = 192;
2030                 rdev->config.r600.max_stack_entries = 128;
2031                 rdev->config.r600.max_hw_contexts = 8;
2032                 rdev->config.r600.max_gs_threads = 4;
2033                 rdev->config.r600.sx_max_export_size = 128;
2034                 rdev->config.r600.sx_max_export_pos_size = 16;
2035                 rdev->config.r600.sx_max_export_smx_size = 128;
2036                 rdev->config.r600.sq_num_cf_insts = 2;
2037                 break;
2038         case CHIP_RV610:
2039         case CHIP_RV620:
2040         case CHIP_RS780:
2041         case CHIP_RS880:
2042                 rdev->config.r600.max_pipes = 1;
2043                 rdev->config.r600.max_tile_pipes = 1;
2044                 rdev->config.r600.max_simds = 2;
2045                 rdev->config.r600.max_backends = 1;
2046                 rdev->config.r600.max_gprs = 128;
2047                 rdev->config.r600.max_threads = 192;
2048                 rdev->config.r600.max_stack_entries = 128;
2049                 rdev->config.r600.max_hw_contexts = 4;
2050                 rdev->config.r600.max_gs_threads = 4;
2051                 rdev->config.r600.sx_max_export_size = 128;
2052                 rdev->config.r600.sx_max_export_pos_size = 16;
2053                 rdev->config.r600.sx_max_export_smx_size = 128;
2054                 rdev->config.r600.sq_num_cf_insts = 1;
2055                 break;
2056         case CHIP_RV670:
2057                 rdev->config.r600.max_pipes = 4;
2058                 rdev->config.r600.max_tile_pipes = 4;
2059                 rdev->config.r600.max_simds = 4;
2060                 rdev->config.r600.max_backends = 4;
2061                 rdev->config.r600.max_gprs = 192;
2062                 rdev->config.r600.max_threads = 192;
2063                 rdev->config.r600.max_stack_entries = 256;
2064                 rdev->config.r600.max_hw_contexts = 8;
2065                 rdev->config.r600.max_gs_threads = 16;
2066                 rdev->config.r600.sx_max_export_size = 128;
2067                 rdev->config.r600.sx_max_export_pos_size = 16;
2068                 rdev->config.r600.sx_max_export_smx_size = 128;
2069                 rdev->config.r600.sq_num_cf_insts = 2;
2070                 break;
2071         default:
2072                 break;
2073         }
2074 
2075         /* Initialize HDP */
2076         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2077                 WREG32((0x2c14 + j), 0x00000000);
2078                 WREG32((0x2c18 + j), 0x00000000);
2079                 WREG32((0x2c1c + j), 0x00000000);
2080                 WREG32((0x2c20 + j), 0x00000000);
2081                 WREG32((0x2c24 + j), 0x00000000);
2082         }
2083 
2084         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2085 
2086         /* Setup tiling */
2087         tiling_config = 0;
2088         ramcfg = RREG32(RAMCFG);
2089         switch (rdev->config.r600.max_tile_pipes) {
2090         case 1:
2091                 tiling_config |= PIPE_TILING(0);
2092                 break;
2093         case 2:
2094                 tiling_config |= PIPE_TILING(1);
2095                 break;
2096         case 4:
2097                 tiling_config |= PIPE_TILING(2);
2098                 break;
2099         case 8:
2100                 tiling_config |= PIPE_TILING(3);
2101                 break;
2102         default:
2103                 break;
2104         }
2105         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2106         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2107         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2108         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2109 
2110         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2111         if (tmp > 3) {
2112                 tiling_config |= ROW_TILING(3);
2113                 tiling_config |= SAMPLE_SPLIT(3);
2114         } else {
2115                 tiling_config |= ROW_TILING(tmp);
2116                 tiling_config |= SAMPLE_SPLIT(tmp);
2117         }
2118         tiling_config |= BANK_SWAPS(1);
2119 
2120         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2121         tmp = rdev->config.r600.max_simds -
2122                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2123         rdev->config.r600.active_simds = tmp;
2124 
2125         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2126         tmp = 0;
2127         for (i = 0; i < rdev->config.r600.max_backends; i++)
2128                 tmp |= (1 << i);
2129         /* if all the backends are disabled, fix it up here */
2130         if ((disabled_rb_mask & tmp) == tmp) {
2131                 for (i = 0; i < rdev->config.r600.max_backends; i++)
2132                         disabled_rb_mask &= ~(1 << i);
2133         }
2134         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2135         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2136                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
2137         tiling_config |= tmp << 16;
2138         rdev->config.r600.backend_map = tmp;
2139 
2140         rdev->config.r600.tile_config = tiling_config;
2141         WREG32(GB_TILING_CONFIG, tiling_config);
2142         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2143         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2144         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2145 
2146         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2147         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2148         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2149 
2150         /* Setup some CP states */
2151         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2152         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2153 
2154         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2155                              SYNC_WALKER | SYNC_ALIGNER));
2156         /* Setup various GPU states */
2157         if (rdev->family == CHIP_RV670)
2158                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2159 
2160         tmp = RREG32(SX_DEBUG_1);
2161         tmp |= SMX_EVENT_RELEASE;
2162         if ((rdev->family > CHIP_R600))
2163                 tmp |= ENABLE_NEW_SMX_ADDRESS;
2164         WREG32(SX_DEBUG_1, tmp);
2165 
2166         if (((rdev->family) == CHIP_R600) ||
2167             ((rdev->family) == CHIP_RV630) ||
2168             ((rdev->family) == CHIP_RV610) ||
2169             ((rdev->family) == CHIP_RV620) ||
2170             ((rdev->family) == CHIP_RS780) ||
2171             ((rdev->family) == CHIP_RS880)) {
2172                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2173         } else {
2174                 WREG32(DB_DEBUG, 0);
2175         }
2176         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2177                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2178 
2179         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2180         WREG32(VGT_NUM_INSTANCES, 0);
2181 
2182         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2183         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2184 
2185         tmp = RREG32(SQ_MS_FIFO_SIZES);
2186         if (((rdev->family) == CHIP_RV610) ||
2187             ((rdev->family) == CHIP_RV620) ||
2188             ((rdev->family) == CHIP_RS780) ||
2189             ((rdev->family) == CHIP_RS880)) {
2190                 tmp = (CACHE_FIFO_SIZE(0xa) |
2191                        FETCH_FIFO_HIWATER(0xa) |
2192                        DONE_FIFO_HIWATER(0xe0) |
2193                        ALU_UPDATE_FIFO_HIWATER(0x8));
2194         } else if (((rdev->family) == CHIP_R600) ||
2195                    ((rdev->family) == CHIP_RV630)) {
2196                 tmp &= ~DONE_FIFO_HIWATER(0xff);
2197                 tmp |= DONE_FIFO_HIWATER(0x4);
2198         }
2199         WREG32(SQ_MS_FIFO_SIZES, tmp);
2200 
2201         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2202          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
2203          */
2204         sq_config = RREG32(SQ_CONFIG);
2205         sq_config &= ~(PS_PRIO(3) |
2206                        VS_PRIO(3) |
2207                        GS_PRIO(3) |
2208                        ES_PRIO(3));
2209         sq_config |= (DX9_CONSTS |
2210                       VC_ENABLE |
2211                       PS_PRIO(0) |
2212                       VS_PRIO(1) |
2213                       GS_PRIO(2) |
2214                       ES_PRIO(3));
2215 
2216         if ((rdev->family) == CHIP_R600) {
2217                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2218                                           NUM_VS_GPRS(124) |
2219                                           NUM_CLAUSE_TEMP_GPRS(4));
2220                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2221                                           NUM_ES_GPRS(0));
2222                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2223                                            NUM_VS_THREADS(48) |
2224                                            NUM_GS_THREADS(4) |
2225                                            NUM_ES_THREADS(4));
2226                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2227                                             NUM_VS_STACK_ENTRIES(128));
2228                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2229                                             NUM_ES_STACK_ENTRIES(0));
2230         } else if (((rdev->family) == CHIP_RV610) ||
2231                    ((rdev->family) == CHIP_RV620) ||
2232                    ((rdev->family) == CHIP_RS780) ||
2233                    ((rdev->family) == CHIP_RS880)) {
2234                 /* no vertex cache */
2235                 sq_config &= ~VC_ENABLE;
2236 
2237                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2238                                           NUM_VS_GPRS(44) |
2239                                           NUM_CLAUSE_TEMP_GPRS(2));
2240                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2241                                           NUM_ES_GPRS(17));
2242                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2243                                            NUM_VS_THREADS(78) |
2244                                            NUM_GS_THREADS(4) |
2245                                            NUM_ES_THREADS(31));
2246                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2247                                             NUM_VS_STACK_ENTRIES(40));
2248                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2249                                             NUM_ES_STACK_ENTRIES(16));
2250         } else if (((rdev->family) == CHIP_RV630) ||
2251                    ((rdev->family) == CHIP_RV635)) {
2252                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2253                                           NUM_VS_GPRS(44) |
2254                                           NUM_CLAUSE_TEMP_GPRS(2));
2255                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2256                                           NUM_ES_GPRS(18));
2257                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2258                                            NUM_VS_THREADS(78) |
2259                                            NUM_GS_THREADS(4) |
2260                                            NUM_ES_THREADS(31));
2261                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2262                                             NUM_VS_STACK_ENTRIES(40));
2263                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2264                                             NUM_ES_STACK_ENTRIES(16));
2265         } else if ((rdev->family) == CHIP_RV670) {
2266                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2267                                           NUM_VS_GPRS(44) |
2268                                           NUM_CLAUSE_TEMP_GPRS(2));
2269                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2270                                           NUM_ES_GPRS(17));
2271                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2272                                            NUM_VS_THREADS(78) |
2273                                            NUM_GS_THREADS(4) |
2274                                            NUM_ES_THREADS(31));
2275                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2276                                             NUM_VS_STACK_ENTRIES(64));
2277                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2278                                             NUM_ES_STACK_ENTRIES(64));
2279         }
2280 
2281         WREG32(SQ_CONFIG, sq_config);
2282         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2283         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2284         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2285         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2286         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2287 
2288         if (((rdev->family) == CHIP_RV610) ||
2289             ((rdev->family) == CHIP_RV620) ||
2290             ((rdev->family) == CHIP_RS780) ||
2291             ((rdev->family) == CHIP_RS880)) {
2292                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2293         } else {
2294                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2295         }
2296 
2297         /* More default values. 2D/3D driver should adjust as needed */
2298         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2299                                          S1_X(0x4) | S1_Y(0xc)));
2300         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2301                                          S1_X(0x2) | S1_Y(0x2) |
2302                                          S2_X(0xa) | S2_Y(0x6) |
2303                                          S3_X(0x6) | S3_Y(0xa)));
2304         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2305                                              S1_X(0x4) | S1_Y(0xc) |
2306                                              S2_X(0x1) | S2_Y(0x6) |
2307                                              S3_X(0xa) | S3_Y(0xe)));
2308         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2309                                              S5_X(0x0) | S5_Y(0x0) |
2310                                              S6_X(0xb) | S6_Y(0x4) |
2311                                              S7_X(0x7) | S7_Y(0x8)));
2312 
2313         WREG32(VGT_STRMOUT_EN, 0);
2314         tmp = rdev->config.r600.max_pipes * 16;
2315         switch (rdev->family) {
2316         case CHIP_RV610:
2317         case CHIP_RV620:
2318         case CHIP_RS780:
2319         case CHIP_RS880:
2320                 tmp += 32;
2321                 break;
2322         case CHIP_RV670:
2323                 tmp += 128;
2324                 break;
2325         default:
2326                 break;
2327         }
2328         if (tmp > 256) {
2329                 tmp = 256;
2330         }
2331         WREG32(VGT_ES_PER_GS, 128);
2332         WREG32(VGT_GS_PER_ES, tmp);
2333         WREG32(VGT_GS_PER_VS, 2);
2334         WREG32(VGT_GS_VERTEX_REUSE, 16);
2335 
2336         /* more default values. 2D/3D driver should adjust as needed */
2337         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2338         WREG32(VGT_STRMOUT_EN, 0);
2339         WREG32(SX_MISC, 0);
2340         WREG32(PA_SC_MODE_CNTL, 0);
2341         WREG32(PA_SC_AA_CONFIG, 0);
2342         WREG32(PA_SC_LINE_STIPPLE, 0);
2343         WREG32(SPI_INPUT_Z, 0);
2344         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2345         WREG32(CB_COLOR7_FRAG, 0);
2346 
2347         /* Clear render buffer base addresses */
2348         WREG32(CB_COLOR0_BASE, 0);
2349         WREG32(CB_COLOR1_BASE, 0);
2350         WREG32(CB_COLOR2_BASE, 0);
2351         WREG32(CB_COLOR3_BASE, 0);
2352         WREG32(CB_COLOR4_BASE, 0);
2353         WREG32(CB_COLOR5_BASE, 0);
2354         WREG32(CB_COLOR6_BASE, 0);
2355         WREG32(CB_COLOR7_BASE, 0);
2356         WREG32(CB_COLOR7_FRAG, 0);
2357 
2358         switch (rdev->family) {
2359         case CHIP_RV610:
2360         case CHIP_RV620:
2361         case CHIP_RS780:
2362         case CHIP_RS880:
2363                 tmp = TC_L2_SIZE(8);
2364                 break;
2365         case CHIP_RV630:
2366         case CHIP_RV635:
2367                 tmp = TC_L2_SIZE(4);
2368                 break;
2369         case CHIP_R600:
2370                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2371                 break;
2372         default:
2373                 tmp = TC_L2_SIZE(0);
2374                 break;
2375         }
2376         WREG32(TC_CNTL, tmp);
2377 
2378         tmp = RREG32(HDP_HOST_PATH_CNTL);
2379         WREG32(HDP_HOST_PATH_CNTL, tmp);
2380 
2381         tmp = RREG32(ARB_POP);
2382         tmp |= ENABLE_TC128;
2383         WREG32(ARB_POP, tmp);
2384 
2385         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2386         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2387                                NUM_CLIP_SEQ(3)));
2388         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2389         WREG32(VC_ENHANCE, 0);
2390 }
2391 
2392 
2393 /*
2394  * Indirect registers accessor
2395  */
2396 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2397 {
2398         unsigned long flags;
2399         u32 r;
2400 
2401         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2402         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2403         (void)RREG32(PCIE_PORT_INDEX);
2404         r = RREG32(PCIE_PORT_DATA);
2405         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2406         return r;
2407 }
2408 
2409 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2410 {
2411         unsigned long flags;
2412 
2413         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2414         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2415         (void)RREG32(PCIE_PORT_INDEX);
2416         WREG32(PCIE_PORT_DATA, (v));
2417         (void)RREG32(PCIE_PORT_DATA);
2418         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2419 }
2420 
2421 /*
2422  * CP & Ring
2423  */
2424 void r600_cp_stop(struct radeon_device *rdev)
2425 {
2426         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2427                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2428         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2429         WREG32(SCRATCH_UMSK, 0);
2430         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2431 }
2432 
2433 int r600_init_microcode(struct radeon_device *rdev)
2434 {
2435         const char *chip_name;
2436         const char *rlc_chip_name;
2437         const char *smc_chip_name = "RV770";
2438         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2439         char fw_name[30];
2440         int err;
2441 
2442         DRM_DEBUG("\n");
2443 
2444         switch (rdev->family) {
2445         case CHIP_R600:
2446                 chip_name = "R600";
2447                 rlc_chip_name = "R600";
2448                 break;
2449         case CHIP_RV610:
2450                 chip_name = "RV610";
2451                 rlc_chip_name = "R600";
2452                 break;
2453         case CHIP_RV630:
2454                 chip_name = "RV630";
2455                 rlc_chip_name = "R600";
2456                 break;
2457         case CHIP_RV620:
2458                 chip_name = "RV620";
2459                 rlc_chip_name = "R600";
2460                 break;
2461         case CHIP_RV635:
2462                 chip_name = "RV635";
2463                 rlc_chip_name = "R600";
2464                 break;
2465         case CHIP_RV670:
2466                 chip_name = "RV670";
2467                 rlc_chip_name = "R600";
2468                 break;
2469         case CHIP_RS780:
2470         case CHIP_RS880:
2471                 chip_name = "RS780";
2472                 rlc_chip_name = "R600";
2473                 break;
2474         case CHIP_RV770:
2475                 chip_name = "RV770";
2476                 rlc_chip_name = "R700";
2477                 smc_chip_name = "RV770";
2478                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2479                 break;
2480         case CHIP_RV730:
2481                 chip_name = "RV730";
2482                 rlc_chip_name = "R700";
2483                 smc_chip_name = "RV730";
2484                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2485                 break;
2486         case CHIP_RV710:
2487                 chip_name = "RV710";
2488                 rlc_chip_name = "R700";
2489                 smc_chip_name = "RV710";
2490                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2491                 break;
2492         case CHIP_RV740:
2493                 chip_name = "RV730";
2494                 rlc_chip_name = "R700";
2495                 smc_chip_name = "RV740";
2496                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2497                 break;
2498         case CHIP_CEDAR:
2499                 chip_name = "CEDAR";
2500                 rlc_chip_name = "CEDAR";
2501                 smc_chip_name = "CEDAR";
2502                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2503                 break;
2504         case CHIP_REDWOOD:
2505                 chip_name = "REDWOOD";
2506                 rlc_chip_name = "REDWOOD";
2507                 smc_chip_name = "REDWOOD";
2508                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2509                 break;
2510         case CHIP_JUNIPER:
2511                 chip_name = "JUNIPER";
2512                 rlc_chip_name = "JUNIPER";
2513                 smc_chip_name = "JUNIPER";
2514                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2515                 break;
2516         case CHIP_CYPRESS:
2517         case CHIP_HEMLOCK:
2518                 chip_name = "CYPRESS";
2519                 rlc_chip_name = "CYPRESS";
2520                 smc_chip_name = "CYPRESS";
2521                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2522                 break;
2523         case CHIP_PALM:
2524                 chip_name = "PALM";
2525                 rlc_chip_name = "SUMO";
2526                 break;
2527         case CHIP_SUMO:
2528                 chip_name = "SUMO";
2529                 rlc_chip_name = "SUMO";
2530                 break;
2531         case CHIP_SUMO2:
2532                 chip_name = "SUMO2";
2533                 rlc_chip_name = "SUMO";
2534                 break;
2535         default: BUG();
2536         }
2537 
2538         if (rdev->family >= CHIP_CEDAR) {
2539                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2540                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2541                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2542         } else if (rdev->family >= CHIP_RV770) {
2543                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2544                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2545                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2546         } else {
2547                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2548                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2549                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2550         }
2551 
2552         DRM_INFO("Loading %s Microcode\n", chip_name);
2553 
2554         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2555         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2556         if (err)
2557                 goto out;
2558         if (rdev->pfp_fw->size != pfp_req_size) {
2559                 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2560                        rdev->pfp_fw->size, fw_name);
2561                 err = -EINVAL;
2562                 goto out;
2563         }
2564 
2565         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2566         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2567         if (err)
2568                 goto out;
2569         if (rdev->me_fw->size != me_req_size) {
2570                 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2571                        rdev->me_fw->size, fw_name);
2572                 err = -EINVAL;
2573         }
2574 
2575         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2576         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2577         if (err)
2578                 goto out;
2579         if (rdev->rlc_fw->size != rlc_req_size) {
2580                 pr_err("r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2581                        rdev->rlc_fw->size, fw_name);
2582                 err = -EINVAL;
2583         }
2584 
2585         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2586                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
2587                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2588                 if (err) {
2589                         pr_err("smc: error loading firmware \"%s\"\n", fw_name);
2590                         release_firmware(rdev->smc_fw);
2591                         rdev->smc_fw = NULL;
2592                         err = 0;
2593                 } else if (rdev->smc_fw->size != smc_req_size) {
2594                         pr_err("smc: Bogus length %zu in firmware \"%s\"\n",
2595                                rdev->smc_fw->size, fw_name);
2596                         err = -EINVAL;
2597                 }
2598         }
2599 
2600 out:
2601         if (err) {
2602                 if (err != -EINVAL)
2603                         pr_err("r600_cp: Failed to load firmware \"%s\"\n",
2604                                fw_name);
2605                 release_firmware(rdev->pfp_fw);
2606                 rdev->pfp_fw = NULL;
2607                 release_firmware(rdev->me_fw);
2608                 rdev->me_fw = NULL;
2609                 release_firmware(rdev->rlc_fw);
2610                 rdev->rlc_fw = NULL;
2611                 release_firmware(rdev->smc_fw);
2612                 rdev->smc_fw = NULL;
2613         }
2614         return err;
2615 }
2616 
2617 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2618                       struct radeon_ring *ring)
2619 {
2620         u32 rptr;
2621 
2622         if (rdev->wb.enabled)
2623                 rptr = rdev->wb.wb[ring->rptr_offs/4];
2624         else
2625                 rptr = RREG32(R600_CP_RB_RPTR);
2626 
2627         return rptr;
2628 }
2629 
2630 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2631                       struct radeon_ring *ring)
2632 {
2633         return RREG32(R600_CP_RB_WPTR);
2634 }
2635 
2636 void r600_gfx_set_wptr(struct radeon_device *rdev,
2637                        struct radeon_ring *ring)
2638 {
2639         WREG32(R600_CP_RB_WPTR, ring->wptr);
2640         (void)RREG32(R600_CP_RB_WPTR);
2641 }
2642 
2643 static int r600_cp_load_microcode(struct radeon_device *rdev)
2644 {
2645         const __be32 *fw_data;
2646         int i;
2647 
2648         if (!rdev->me_fw || !rdev->pfp_fw)
2649                 return -EINVAL;
2650 
2651         r600_cp_stop(rdev);
2652 
2653         WREG32(CP_RB_CNTL,
2654 #ifdef __BIG_ENDIAN
2655                BUF_SWAP_32BIT |
2656 #endif
2657                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2658 
2659         /* Reset cp */
2660         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2661         RREG32(GRBM_SOFT_RESET);
2662         mdelay(15);
2663         WREG32(GRBM_SOFT_RESET, 0);
2664 
2665         WREG32(CP_ME_RAM_WADDR, 0);
2666 
2667         fw_data = (const __be32 *)rdev->me_fw->data;
2668         WREG32(CP_ME_RAM_WADDR, 0);
2669         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2670                 WREG32(CP_ME_RAM_DATA,
2671                        be32_to_cpup(fw_data++));
2672 
2673         fw_data = (const __be32 *)rdev->pfp_fw->data;
2674         WREG32(CP_PFP_UCODE_ADDR, 0);
2675         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2676                 WREG32(CP_PFP_UCODE_DATA,
2677                        be32_to_cpup(fw_data++));
2678 
2679         WREG32(CP_PFP_UCODE_ADDR, 0);
2680         WREG32(CP_ME_RAM_WADDR, 0);
2681         WREG32(CP_ME_RAM_RADDR, 0);
2682         return 0;
2683 }
2684 
2685 int r600_cp_start(struct radeon_device *rdev)
2686 {
2687         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2688         int r;
2689         uint32_t cp_me;
2690 
2691         r = radeon_ring_lock(rdev, ring, 7);
2692         if (r) {
2693                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2694                 return r;
2695         }
2696         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2697         radeon_ring_write(ring, 0x1);
2698         if (rdev->family >= CHIP_RV770) {
2699                 radeon_ring_write(ring, 0x0);
2700                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2701         } else {
2702                 radeon_ring_write(ring, 0x3);
2703                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2704         }
2705         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2706         radeon_ring_write(ring, 0);
2707         radeon_ring_write(ring, 0);
2708         radeon_ring_unlock_commit(rdev, ring, false);
2709 
2710         cp_me = 0xff;
2711         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2712         return 0;
2713 }
2714 
2715 int r600_cp_resume(struct radeon_device *rdev)
2716 {
2717         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2718         u32 tmp;
2719         u32 rb_bufsz;
2720         int r;
2721 
2722         /* Reset cp */
2723         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2724         RREG32(GRBM_SOFT_RESET);
2725         mdelay(15);
2726         WREG32(GRBM_SOFT_RESET, 0);
2727 
2728         /* Set ring buffer size */
2729         rb_bufsz = order_base_2(ring->ring_size / 8);
2730         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2731 #ifdef __BIG_ENDIAN
2732         tmp |= BUF_SWAP_32BIT;
2733 #endif
2734         WREG32(CP_RB_CNTL, tmp);
2735         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2736 
2737         /* Set the write pointer delay */
2738         WREG32(CP_RB_WPTR_DELAY, 0);
2739 
2740         /* Initialize the ring buffer's read and write pointers */
2741         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2742         WREG32(CP_RB_RPTR_WR, 0);
2743         ring->wptr = 0;
2744         WREG32(CP_RB_WPTR, ring->wptr);
2745 
2746         /* set the wb address whether it's enabled or not */
2747         WREG32(CP_RB_RPTR_ADDR,
2748                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2749         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2750         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2751 
2752         if (rdev->wb.enabled)
2753                 WREG32(SCRATCH_UMSK, 0xff);
2754         else {
2755                 tmp |= RB_NO_UPDATE;
2756                 WREG32(SCRATCH_UMSK, 0);
2757         }
2758 
2759         mdelay(1);
2760         WREG32(CP_RB_CNTL, tmp);
2761 
2762         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2763         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2764 
2765         r600_cp_start(rdev);
2766         ring->ready = true;
2767         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2768         if (r) {
2769                 ring->ready = false;
2770                 return r;
2771         }
2772 
2773         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2774                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2775 
2776         return 0;
2777 }
2778 
2779 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2780 {
2781         u32 rb_bufsz;
2782         int r;
2783 
2784         /* Align ring size */
2785         rb_bufsz = order_base_2(ring_size / 8);
2786         ring_size = (1 << (rb_bufsz + 1)) * 4;
2787         ring->ring_size = ring_size;
2788         ring->align_mask = 16 - 1;
2789 
2790         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2791                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2792                 if (r) {
2793                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2794                         ring->rptr_save_reg = 0;
2795                 }
2796         }
2797 }
2798 
2799 void r600_cp_fini(struct radeon_device *rdev)
2800 {
2801         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2802         r600_cp_stop(rdev);
2803         radeon_ring_fini(rdev, ring);
2804         radeon_scratch_free(rdev, ring->rptr_save_reg);
2805 }
2806 
2807 /*
2808  * GPU scratch registers helpers function.
2809  */
2810 void r600_scratch_init(struct radeon_device *rdev)
2811 {
2812         int i;
2813 
2814         rdev->scratch.num_reg = 7;
2815         rdev->scratch.reg_base = SCRATCH_REG0;
2816         for (i = 0; i < rdev->scratch.num_reg; i++) {
2817                 rdev->scratch.free[i] = true;
2818                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2819         }
2820 }
2821 
2822 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2823 {
2824         uint32_t scratch;
2825         uint32_t tmp = 0;
2826         unsigned i;
2827         int r;
2828 
2829         r = radeon_scratch_get(rdev, &scratch);
2830         if (r) {
2831                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2832                 return r;
2833         }
2834         WREG32(scratch, 0xCAFEDEAD);
2835         r = radeon_ring_lock(rdev, ring, 3);
2836         if (r) {
2837                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2838                 radeon_scratch_free(rdev, scratch);
2839                 return r;
2840         }
2841         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2842         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2843         radeon_ring_write(ring, 0xDEADBEEF);
2844         radeon_ring_unlock_commit(rdev, ring, false);
2845         for (i = 0; i < rdev->usec_timeout; i++) {
2846                 tmp = RREG32(scratch);
2847                 if (tmp == 0xDEADBEEF)
2848                         break;
2849                 udelay(1);
2850         }
2851         if (i < rdev->usec_timeout) {
2852                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2853         } else {
2854                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2855                           ring->idx, scratch, tmp);
2856                 r = -EINVAL;
2857         }
2858         radeon_scratch_free(rdev, scratch);
2859         return r;
2860 }
2861 
2862 /*
2863  * CP fences/semaphores
2864  */
2865 
2866 void r600_fence_ring_emit(struct radeon_device *rdev,
2867                           struct radeon_fence *fence)
2868 {
2869         struct radeon_ring *ring = &rdev->ring[fence->ring];
2870         u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2871                 PACKET3_SH_ACTION_ENA;
2872 
2873         if (rdev->family >= CHIP_RV770)
2874                 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2875 
2876         if (rdev->wb.use_event) {
2877                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2878                 /* flush read cache over gart */
2879                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2880                 radeon_ring_write(ring, cp_coher_cntl);
2881                 radeon_ring_write(ring, 0xFFFFFFFF);
2882                 radeon_ring_write(ring, 0);
2883                 radeon_ring_write(ring, 10); /* poll interval */
2884                 /* EVENT_WRITE_EOP - flush caches, send int */
2885                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2886                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2887                 radeon_ring_write(ring, lower_32_bits(addr));
2888                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2889                 radeon_ring_write(ring, fence->seq);
2890                 radeon_ring_write(ring, 0);
2891         } else {
2892                 /* flush read cache over gart */
2893                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2894                 radeon_ring_write(ring, cp_coher_cntl);
2895                 radeon_ring_write(ring, 0xFFFFFFFF);
2896                 radeon_ring_write(ring, 0);
2897                 radeon_ring_write(ring, 10); /* poll interval */
2898                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2899                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2900                 /* wait for 3D idle clean */
2901                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2902                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2903                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2904                 /* Emit fence sequence & fire IRQ */
2905                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2906                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2907                 radeon_ring_write(ring, fence->seq);
2908                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2909                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2910                 radeon_ring_write(ring, RB_INT_STAT);
2911         }
2912 }
2913 
2914 /**
2915  * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2916  *
2917  * @rdev: radeon_device pointer
2918  * @ring: radeon ring buffer object
2919  * @semaphore: radeon semaphore object
2920  * @emit_wait: Is this a sempahore wait?
2921  *
2922  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2923  * from running ahead of semaphore waits.
2924  */
2925 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2926                               struct radeon_ring *ring,
2927                               struct radeon_semaphore *semaphore,
2928                               bool emit_wait)
2929 {
2930         uint64_t addr = semaphore->gpu_addr;
2931         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2932 
2933         if (rdev->family < CHIP_CAYMAN)
2934                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2935 
2936         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2937         radeon_ring_write(ring, lower_32_bits(addr));
2938         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2939 
2940         /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2941         if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2942                 /* Prevent the PFP from running ahead of the semaphore wait */
2943                 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2944                 radeon_ring_write(ring, 0x0);
2945         }
2946 
2947         return true;
2948 }
2949 
2950 /**
2951  * r600_copy_cpdma - copy pages using the CP DMA engine
2952  *
2953  * @rdev: radeon_device pointer
2954  * @src_offset: src GPU address
2955  * @dst_offset: dst GPU address
2956  * @num_gpu_pages: number of GPU pages to xfer
2957  * @fence: radeon fence object
2958  *
2959  * Copy GPU paging using the CP DMA engine (r6xx+).
2960  * Used by the radeon ttm implementation to move pages if
2961  * registered as the asic copy callback.
2962  */
2963 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2964                                      uint64_t src_offset, uint64_t dst_offset,
2965                                      unsigned num_gpu_pages,
2966                                      struct dma_resv *resv)
2967 {
2968         struct radeon_fence *fence;
2969         struct radeon_sync sync;
2970         int ring_index = rdev->asic->copy.blit_ring_index;
2971         struct radeon_ring *ring = &rdev->ring[ring_index];
2972         u32 size_in_bytes, cur_size_in_bytes, tmp;
2973         int i, num_loops;
2974         int r = 0;
2975 
2976         radeon_sync_create(&sync);
2977 
2978         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2979         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2980         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2981         if (r) {
2982                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2983                 radeon_sync_free(rdev, &sync, NULL);
2984                 return ERR_PTR(r);
2985         }
2986 
2987         radeon_sync_resv(rdev, &sync, resv, false);
2988         radeon_sync_rings(rdev, &sync, ring->idx);
2989 
2990         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2991         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2992         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2993         for (i = 0; i < num_loops; i++) {
2994                 cur_size_in_bytes = size_in_bytes;
2995                 if (cur_size_in_bytes > 0x1fffff)
2996                         cur_size_in_bytes = 0x1fffff;
2997                 size_in_bytes -= cur_size_in_bytes;
2998                 tmp = upper_32_bits(src_offset) & 0xff;
2999                 if (size_in_bytes == 0)
3000                         tmp |= PACKET3_CP_DMA_CP_SYNC;
3001                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
3002                 radeon_ring_write(ring, lower_32_bits(src_offset));
3003                 radeon_ring_write(ring, tmp);
3004                 radeon_ring_write(ring, lower_32_bits(dst_offset));
3005                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3006                 radeon_ring_write(ring, cur_size_in_bytes);
3007                 src_offset += cur_size_in_bytes;
3008                 dst_offset += cur_size_in_bytes;
3009         }
3010         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3011         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3012         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
3013 
3014         r = radeon_fence_emit(rdev, &fence, ring->idx);
3015         if (r) {
3016                 radeon_ring_unlock_undo(rdev, ring);
3017                 radeon_sync_free(rdev, &sync, NULL);
3018                 return ERR_PTR(r);
3019         }
3020 
3021         radeon_ring_unlock_commit(rdev, ring, false);
3022         radeon_sync_free(rdev, &sync, fence);
3023 
3024         return fence;
3025 }
3026 
3027 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3028                          uint32_t tiling_flags, uint32_t pitch,
3029                          uint32_t offset, uint32_t obj_size)
3030 {
3031         /* FIXME: implement */
3032         return 0;
3033 }
3034 
3035 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3036 {
3037         /* FIXME: implement */
3038 }
3039 
3040 static void r600_uvd_init(struct radeon_device *rdev)
3041 {
3042         int r;
3043 
3044         if (!rdev->has_uvd)
3045                 return;
3046 
3047         r = radeon_uvd_init(rdev);
3048         if (r) {
3049                 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3050                 /*
3051                  * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3052                  * to early fails uvd_v1_0_resume() and thus nothing happens
3053                  * there. So it is pointless to try to go through that code
3054                  * hence why we disable uvd here.
3055                  */
3056                 rdev->has_uvd = 0;
3057                 return;
3058         }
3059         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3060         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3061 }
3062 
3063 static void r600_uvd_start(struct radeon_device *rdev)
3064 {
3065         int r;
3066 
3067         if (!rdev->has_uvd)
3068                 return;
3069 
3070         r = uvd_v1_0_resume(rdev);
3071         if (r) {
3072                 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3073                 goto error;
3074         }
3075         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3076         if (r) {
3077                 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3078                 goto error;
3079         }
3080         return;
3081 
3082 error:
3083         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3084 }
3085 
3086 static void r600_uvd_resume(struct radeon_device *rdev)
3087 {
3088         struct radeon_ring *ring;
3089         int r;
3090 
3091         if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3092                 return;
3093 
3094         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3095         r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
3096         if (r) {
3097                 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3098                 return;
3099         }
3100         r = uvd_v1_0_init(rdev);
3101         if (r) {
3102                 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3103                 return;
3104         }
3105 }
3106 
3107 static int r600_startup(struct radeon_device *rdev)
3108 {
3109         struct radeon_ring *ring;
3110         int r;
3111 
3112         /* enable pcie gen2 link */
3113         r600_pcie_gen2_enable(rdev);
3114 
3115         /* scratch needs to be initialized before MC */
3116         r = r600_vram_scratch_init(rdev);
3117         if (r)
3118                 return r;
3119 
3120         r600_mc_program(rdev);
3121 
3122         if (rdev->flags & RADEON_IS_AGP) {
3123                 r600_agp_enable(rdev);
3124         } else {
3125                 r = r600_pcie_gart_enable(rdev);
3126                 if (r)
3127                         return r;
3128         }
3129         r600_gpu_init(rdev);
3130 
3131         /* allocate wb buffer */
3132         r = radeon_wb_init(rdev);
3133         if (r)
3134                 return r;
3135 
3136         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3137         if (r) {
3138                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3139                 return r;
3140         }
3141 
3142         r600_uvd_start(rdev);
3143 
3144         /* Enable IRQ */
3145         if (!rdev->irq.installed) {
3146                 r = radeon_irq_kms_init(rdev);
3147                 if (r)
3148                         return r;
3149         }
3150 
3151         r = r600_irq_init(rdev);
3152         if (r) {
3153                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3154                 radeon_irq_kms_fini(rdev);
3155                 return r;
3156         }
3157         r600_irq_set(rdev);
3158 
3159         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3160         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3161                              RADEON_CP_PACKET2);
3162         if (r)
3163                 return r;
3164 
3165         r = r600_cp_load_microcode(rdev);
3166         if (r)
3167                 return r;
3168         r = r600_cp_resume(rdev);
3169         if (r)
3170                 return r;
3171 
3172         r600_uvd_resume(rdev);
3173 
3174         r = radeon_ib_pool_init(rdev);
3175         if (r) {
3176                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3177                 return r;
3178         }
3179 
3180         r = radeon_audio_init(rdev);
3181         if (r) {
3182                 DRM_ERROR("radeon: audio init failed\n");
3183                 return r;
3184         }
3185 
3186         return 0;
3187 }
3188 
3189 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3190 {
3191         uint32_t temp;
3192 
3193         temp = RREG32(CONFIG_CNTL);
3194         if (state == false) {
3195                 temp &= ~(1<<0);
3196                 temp |= (1<<1);
3197         } else {
3198                 temp &= ~(1<<1);
3199         }
3200         WREG32(CONFIG_CNTL, temp);
3201 }
3202 
3203 int r600_resume(struct radeon_device *rdev)
3204 {
3205         int r;
3206 
3207         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3208          * posting will perform necessary task to bring back GPU into good
3209          * shape.
3210          */
3211         /* post card */
3212         atom_asic_init(rdev->mode_info.atom_context);
3213 
3214         if (rdev->pm.pm_method == PM_METHOD_DPM)
3215                 radeon_pm_resume(rdev);
3216 
3217         rdev->accel_working = true;
3218         r = r600_startup(rdev);
3219         if (r) {
3220                 DRM_ERROR("r600 startup failed on resume\n");
3221                 rdev->accel_working = false;
3222                 return r;
3223         }
3224 
3225         return r;
3226 }
3227 
3228 int r600_suspend(struct radeon_device *rdev)
3229 {
3230         radeon_pm_suspend(rdev);
3231         radeon_audio_fini(rdev);
3232         r600_cp_stop(rdev);
3233         if (rdev->has_uvd) {
3234                 uvd_v1_0_fini(rdev);
3235                 radeon_uvd_suspend(rdev);
3236         }
3237         r600_irq_suspend(rdev);
3238         radeon_wb_disable(rdev);
3239         r600_pcie_gart_disable(rdev);
3240 
3241         return 0;
3242 }
3243 
3244 /* Plan is to move initialization in that function and use
3245  * helper function so that radeon_device_init pretty much
3246  * do nothing more than calling asic specific function. This
3247  * should also allow to remove a bunch of callback function
3248  * like vram_info.
3249  */
3250 int r600_init(struct radeon_device *rdev)
3251 {
3252         int r;
3253 
3254         if (r600_debugfs_mc_info_init(rdev)) {
3255                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3256         }
3257         /* Read BIOS */
3258         if (!radeon_get_bios(rdev)) {
3259                 if (ASIC_IS_AVIVO(rdev))
3260                         return -EINVAL;
3261         }
3262         /* Must be an ATOMBIOS */
3263         if (!rdev->is_atom_bios) {
3264                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3265                 return -EINVAL;
3266         }
3267         r = radeon_atombios_init(rdev);
3268         if (r)
3269                 return r;
3270         /* Post card if necessary */
3271         if (!radeon_card_posted(rdev)) {
3272                 if (!rdev->bios) {
3273                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3274                         return -EINVAL;
3275                 }
3276                 DRM_INFO("GPU not posted. posting now...\n");
3277                 atom_asic_init(rdev->mode_info.atom_context);
3278         }
3279         /* Initialize scratch registers */
3280         r600_scratch_init(rdev);
3281         /* Initialize surface registers */
3282         radeon_surface_init(rdev);
3283         /* Initialize clocks */
3284         radeon_get_clock_info(rdev->ddev);
3285         /* Fence driver */
3286         r = radeon_fence_driver_init(rdev);
3287         if (r)
3288                 return r;
3289         if (rdev->flags & RADEON_IS_AGP) {
3290                 r = radeon_agp_init(rdev);
3291                 if (r)
3292                         radeon_agp_disable(rdev);
3293         }
3294         r = r600_mc_init(rdev);
3295         if (r)
3296                 return r;
3297         /* Memory manager */
3298         r = radeon_bo_init(rdev);
3299         if (r)
3300                 return r;
3301 
3302         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3303                 r = r600_init_microcode(rdev);
3304                 if (r) {
3305                         DRM_ERROR("Failed to load firmware!\n");
3306                         return r;
3307                 }
3308         }
3309 
3310         /* Initialize power management */
3311         radeon_pm_init(rdev);
3312 
3313         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3314         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3315 
3316         r600_uvd_init(rdev);
3317 
3318         rdev->ih.ring_obj = NULL;
3319         r600_ih_ring_init(rdev, 64 * 1024);
3320 
3321         r = r600_pcie_gart_init(rdev);
3322         if (r)
3323                 return r;
3324 
3325         rdev->accel_working = true;
3326         r = r600_startup(rdev);
3327         if (r) {
3328                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3329                 r600_cp_fini(rdev);
3330                 r600_irq_fini(rdev);
3331                 radeon_wb_fini(rdev);
3332                 radeon_ib_pool_fini(rdev);
3333                 radeon_irq_kms_fini(rdev);
3334                 r600_pcie_gart_fini(rdev);
3335                 rdev->accel_working = false;
3336         }
3337 
3338         return 0;
3339 }
3340 
3341 void r600_fini(struct radeon_device *rdev)
3342 {
3343         radeon_pm_fini(rdev);
3344         radeon_audio_fini(rdev);
3345         r600_cp_fini(rdev);
3346         r600_irq_fini(rdev);
3347         if (rdev->has_uvd) {
3348                 uvd_v1_0_fini(rdev);
3349                 radeon_uvd_fini(rdev);
3350         }
3351         radeon_wb_fini(rdev);
3352         radeon_ib_pool_fini(rdev);
3353         radeon_irq_kms_fini(rdev);
3354         r600_pcie_gart_fini(rdev);
3355         r600_vram_scratch_fini(rdev);
3356         radeon_agp_fini(rdev);
3357         radeon_gem_fini(rdev);
3358         radeon_fence_driver_fini(rdev);
3359         radeon_bo_fini(rdev);
3360         radeon_atombios_fini(rdev);
3361         kfree(rdev->bios);
3362         rdev->bios = NULL;
3363 }
3364 
3365 
3366 /*
3367  * CS stuff
3368  */
3369 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3370 {
3371         struct radeon_ring *ring = &rdev->ring[ib->ring];
3372         u32 next_rptr;
3373 
3374         if (ring->rptr_save_reg) {
3375                 next_rptr = ring->wptr + 3 + 4;
3376                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3377                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3378                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3379                 radeon_ring_write(ring, next_rptr);
3380         } else if (rdev->wb.enabled) {
3381                 next_rptr = ring->wptr + 5 + 4;
3382                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3383                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3384                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3385                 radeon_ring_write(ring, next_rptr);
3386                 radeon_ring_write(ring, 0);
3387         }
3388 
3389         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3390         radeon_ring_write(ring,
3391 #ifdef __BIG_ENDIAN
3392                           (2 << 0) |
3393 #endif
3394                           (ib->gpu_addr & 0xFFFFFFFC));
3395         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3396         radeon_ring_write(ring, ib->length_dw);
3397 }
3398 
3399 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3400 {
3401         struct radeon_ib ib;
3402         uint32_t scratch;
3403         uint32_t tmp = 0;
3404         unsigned i;
3405         int r;
3406 
3407         r = radeon_scratch_get(rdev, &scratch);
3408         if (r) {
3409                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3410                 return r;
3411         }
3412         WREG32(scratch, 0xCAFEDEAD);
3413         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3414         if (r) {
3415                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3416                 goto free_scratch;
3417         }
3418         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3419         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3420         ib.ptr[2] = 0xDEADBEEF;
3421         ib.length_dw = 3;
3422         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3423         if (r) {
3424                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3425                 goto free_ib;
3426         }
3427         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3428                 RADEON_USEC_IB_TEST_TIMEOUT));
3429         if (r < 0) {
3430                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3431                 goto free_ib;
3432         } else if (r == 0) {
3433                 DRM_ERROR("radeon: fence wait timed out.\n");
3434                 r = -ETIMEDOUT;
3435                 goto free_ib;
3436         }
3437         r = 0;
3438         for (i = 0; i < rdev->usec_timeout; i++) {
3439                 tmp = RREG32(scratch);
3440                 if (tmp == 0xDEADBEEF)
3441                         break;
3442                 udelay(1);
3443         }
3444         if (i < rdev->usec_timeout) {
3445                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3446         } else {
3447                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3448                           scratch, tmp);
3449                 r = -EINVAL;
3450         }
3451 free_ib:
3452         radeon_ib_free(rdev, &ib);
3453 free_scratch:
3454         radeon_scratch_free(rdev, scratch);
3455         return r;
3456 }
3457 
3458 /*
3459  * Interrupts
3460  *
3461  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3462  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3463  * writing to the ring and the GPU consuming, the GPU writes to the ring
3464  * and host consumes.  As the host irq handler processes interrupts, it
3465  * increments the rptr.  When the rptr catches up with the wptr, all the
3466  * current interrupts have been processed.
3467  */
3468 
3469 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3470 {
3471         u32 rb_bufsz;
3472 
3473         /* Align ring size */
3474         rb_bufsz = order_base_2(ring_size / 4);
3475         ring_size = (1 << rb_bufsz) * 4;
3476         rdev->ih.ring_size = ring_size;
3477         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3478         rdev->ih.rptr = 0;
3479 }
3480 
3481 int r600_ih_ring_alloc(struct radeon_device *rdev)
3482 {
3483         int r;
3484 
3485         /* Allocate ring buffer */
3486         if (rdev->ih.ring_obj == NULL) {
3487                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3488                                      PAGE_SIZE, true,
3489                                      RADEON_GEM_DOMAIN_GTT, 0,
3490                                      NULL, NULL, &rdev->ih.ring_obj);
3491                 if (r) {
3492                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3493                         return r;
3494                 }
3495                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3496                 if (unlikely(r != 0))
3497                         return r;
3498                 r = radeon_bo_pin(rdev->ih.ring_obj,
3499                                   RADEON_GEM_DOMAIN_GTT,
3500                                   &rdev->ih.gpu_addr);
3501                 if (r) {
3502                         radeon_bo_unreserve(rdev->ih.ring_obj);
3503                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3504                         return r;
3505                 }
3506                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3507                                    (void **)&rdev->ih.ring);
3508                 radeon_bo_unreserve(rdev->ih.ring_obj);
3509                 if (r) {
3510                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3511                         return r;
3512                 }
3513         }
3514         return 0;
3515 }
3516 
3517 void r600_ih_ring_fini(struct radeon_device *rdev)
3518 {
3519         int r;
3520         if (rdev->ih.ring_obj) {
3521                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3522                 if (likely(r == 0)) {
3523                         radeon_bo_kunmap(rdev->ih.ring_obj);
3524                         radeon_bo_unpin(rdev->ih.ring_obj);
3525                         radeon_bo_unreserve(rdev->ih.ring_obj);
3526                 }
3527                 radeon_bo_unref(&rdev->ih.ring_obj);
3528                 rdev->ih.ring = NULL;
3529                 rdev->ih.ring_obj = NULL;
3530         }
3531 }
3532 
3533 void r600_rlc_stop(struct radeon_device *rdev)
3534 {
3535 
3536         if ((rdev->family >= CHIP_RV770) &&
3537             (rdev->family <= CHIP_RV740)) {
3538                 /* r7xx asics need to soft reset RLC before halting */
3539                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3540                 RREG32(SRBM_SOFT_RESET);
3541                 mdelay(15);
3542                 WREG32(SRBM_SOFT_RESET, 0);
3543                 RREG32(SRBM_SOFT_RESET);
3544         }
3545 
3546         WREG32(RLC_CNTL, 0);
3547 }
3548 
3549 static void r600_rlc_start(struct radeon_device *rdev)
3550 {
3551         WREG32(RLC_CNTL, RLC_ENABLE);
3552 }
3553 
3554 static int r600_rlc_resume(struct radeon_device *rdev)
3555 {
3556         u32 i;
3557         const __be32 *fw_data;
3558 
3559         if (!rdev->rlc_fw)
3560                 return -EINVAL;
3561 
3562         r600_rlc_stop(rdev);
3563 
3564         WREG32(RLC_HB_CNTL, 0);
3565 
3566         WREG32(RLC_HB_BASE, 0);
3567         WREG32(RLC_HB_RPTR, 0);
3568         WREG32(RLC_HB_WPTR, 0);
3569         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3570         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3571         WREG32(RLC_MC_CNTL, 0);
3572         WREG32(RLC_UCODE_CNTL, 0);
3573 
3574         fw_data = (const __be32 *)rdev->rlc_fw->data;
3575         if (rdev->family >= CHIP_RV770) {
3576                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3577                         WREG32(RLC_UCODE_ADDR, i);
3578                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3579                 }
3580         } else {
3581                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3582                         WREG32(RLC_UCODE_ADDR, i);
3583                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3584                 }
3585         }
3586         WREG32(RLC_UCODE_ADDR, 0);
3587 
3588         r600_rlc_start(rdev);
3589 
3590         return 0;
3591 }
3592 
3593 static void r600_enable_interrupts(struct radeon_device *rdev)
3594 {
3595         u32 ih_cntl = RREG32(IH_CNTL);
3596         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3597 
3598         ih_cntl |= ENABLE_INTR;
3599         ih_rb_cntl |= IH_RB_ENABLE;
3600         WREG32(IH_CNTL, ih_cntl);
3601         WREG32(IH_RB_CNTL, ih_rb_cntl);
3602         rdev->ih.enabled = true;
3603 }
3604 
3605 void r600_disable_interrupts(struct radeon_device *rdev)
3606 {
3607         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3608         u32 ih_cntl = RREG32(IH_CNTL);
3609 
3610         ih_rb_cntl &= ~IH_RB_ENABLE;
3611         ih_cntl &= ~ENABLE_INTR;
3612         WREG32(IH_RB_CNTL, ih_rb_cntl);
3613         WREG32(IH_CNTL, ih_cntl);
3614         /* set rptr, wptr to 0 */
3615         WREG32(IH_RB_RPTR, 0);
3616         WREG32(IH_RB_WPTR, 0);
3617         rdev->ih.enabled = false;
3618         rdev->ih.rptr = 0;
3619 }
3620 
3621 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3622 {
3623         u32 tmp;
3624 
3625         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3626         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3627         WREG32(DMA_CNTL, tmp);
3628         WREG32(GRBM_INT_CNTL, 0);
3629         WREG32(DxMODE_INT_MASK, 0);
3630         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3631         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3632         if (ASIC_IS_DCE3(rdev)) {
3633                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3634                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3635                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3636                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3637                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3638                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3639                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3640                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3641                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3642                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3643                 if (ASIC_IS_DCE32(rdev)) {
3644                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3645                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3646                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3647                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3648                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3649                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3650                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3651                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3652                 } else {
3653                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3654                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3655                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3656                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3657                 }
3658         } else {
3659                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3660                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3661                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3662                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3663                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3664                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3665                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3666                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3667                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3668                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3669                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3670                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3671         }
3672 }
3673 
3674 int r600_irq_init(struct radeon_device *rdev)
3675 {
3676         int ret = 0;
3677         int rb_bufsz;
3678         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3679 
3680         /* allocate ring */
3681         ret = r600_ih_ring_alloc(rdev);
3682         if (ret)
3683                 return ret;
3684 
3685         /* disable irqs */
3686         r600_disable_interrupts(rdev);
3687 
3688         /* init rlc */
3689         if (rdev->family >= CHIP_CEDAR)
3690                 ret = evergreen_rlc_resume(rdev);
3691         else
3692                 ret = r600_rlc_resume(rdev);
3693         if (ret) {
3694                 r600_ih_ring_fini(rdev);
3695                 return ret;
3696         }
3697 
3698         /* setup interrupt control */
3699         /* set dummy read address to dummy page address */
3700         WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3701         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3702         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3703          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3704          */
3705         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3706         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3707         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3708         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3709 
3710         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3711         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3712 
3713         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3714                       IH_WPTR_OVERFLOW_CLEAR |
3715                       (rb_bufsz << 1));
3716 
3717         if (rdev->wb.enabled)
3718                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3719 
3720         /* set the writeback address whether it's enabled or not */
3721         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3722         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3723 
3724         WREG32(IH_RB_CNTL, ih_rb_cntl);
3725 
3726         /* set rptr, wptr to 0 */
3727         WREG32(IH_RB_RPTR, 0);
3728         WREG32(IH_RB_WPTR, 0);
3729 
3730         /* Default settings for IH_CNTL (disabled at first) */
3731         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3732         /* RPTR_REARM only works if msi's are enabled */
3733         if (rdev->msi_enabled)
3734                 ih_cntl |= RPTR_REARM;
3735         WREG32(IH_CNTL, ih_cntl);
3736 
3737         /* force the active interrupt state to all disabled */
3738         if (rdev->family >= CHIP_CEDAR)
3739                 evergreen_disable_interrupt_state(rdev);
3740         else
3741                 r600_disable_interrupt_state(rdev);
3742 
3743         /* at this point everything should be setup correctly to enable master */
3744         pci_set_master(rdev->pdev);
3745 
3746         /* enable irqs */
3747         r600_enable_interrupts(rdev);
3748 
3749         return ret;
3750 }
3751 
3752 void r600_irq_suspend(struct radeon_device *rdev)
3753 {
3754         r600_irq_disable(rdev);
3755         r600_rlc_stop(rdev);
3756 }
3757 
3758 void r600_irq_fini(struct radeon_device *rdev)
3759 {
3760         r600_irq_suspend(rdev);
3761         r600_ih_ring_fini(rdev);
3762 }
3763 
3764 int r600_irq_set(struct radeon_device *rdev)
3765 {
3766         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3767         u32 mode_int = 0;
3768         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3769         u32 grbm_int_cntl = 0;
3770         u32 hdmi0, hdmi1;
3771         u32 dma_cntl;
3772         u32 thermal_int = 0;
3773 
3774         if (!rdev->irq.installed) {
3775                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3776                 return -EINVAL;
3777         }
3778         /* don't enable anything if the ih is disabled */
3779         if (!rdev->ih.enabled) {
3780                 r600_disable_interrupts(rdev);
3781                 /* force the active interrupt state to all disabled */
3782                 r600_disable_interrupt_state(rdev);
3783                 return 0;
3784         }
3785 
3786         if (ASIC_IS_DCE3(rdev)) {
3787                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3788                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3789                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3790                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3791                 if (ASIC_IS_DCE32(rdev)) {
3792                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3793                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3794                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3795                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3796                 } else {
3797                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3798                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3799                 }
3800         } else {
3801                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3802                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3803                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3804                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3805                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3806         }
3807 
3808         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3809 
3810         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3811                 thermal_int = RREG32(CG_THERMAL_INT) &
3812                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3813         } else if (rdev->family >= CHIP_RV770) {
3814                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3815                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3816         }
3817         if (rdev->irq.dpm_thermal) {
3818                 DRM_DEBUG("dpm thermal\n");
3819                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3820         }
3821 
3822         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3823                 DRM_DEBUG("r600_irq_set: sw int\n");
3824                 cp_int_cntl |= RB_INT_ENABLE;
3825                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3826         }
3827 
3828         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3829                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3830                 dma_cntl |= TRAP_ENABLE;
3831         }
3832 
3833         if (rdev->irq.crtc_vblank_int[0] ||
3834             atomic_read(&rdev->irq.pflip[0])) {
3835                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3836                 mode_int |= D1MODE_VBLANK_INT_MASK;
3837         }
3838         if (rdev->irq.crtc_vblank_int[1] ||
3839             atomic_read(&rdev->irq.pflip[1])) {
3840                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3841                 mode_int |= D2MODE_VBLANK_INT_MASK;
3842         }
3843         if (rdev->irq.hpd[0]) {
3844                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3845                 hpd1 |= DC_HPDx_INT_EN;
3846         }
3847         if (rdev->irq.hpd[1]) {
3848                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3849                 hpd2 |= DC_HPDx_INT_EN;
3850         }
3851         if (rdev->irq.hpd[2]) {
3852                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3853                 hpd3 |= DC_HPDx_INT_EN;
3854         }
3855         if (rdev->irq.hpd[3]) {
3856                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3857                 hpd4 |= DC_HPDx_INT_EN;
3858         }
3859         if (rdev->irq.hpd[4]) {
3860                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3861                 hpd5 |= DC_HPDx_INT_EN;
3862         }
3863         if (rdev->irq.hpd[5]) {
3864                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3865                 hpd6 |= DC_HPDx_INT_EN;
3866         }
3867         if (rdev->irq.afmt[0]) {
3868                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3869                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3870         }
3871         if (rdev->irq.afmt[1]) {
3872                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3873                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3874         }
3875 
3876         WREG32(CP_INT_CNTL, cp_int_cntl);
3877         WREG32(DMA_CNTL, dma_cntl);
3878         WREG32(DxMODE_INT_MASK, mode_int);
3879         WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3880         WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3881         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3882         if (ASIC_IS_DCE3(rdev)) {
3883                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3884                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3885                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3886                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3887                 if (ASIC_IS_DCE32(rdev)) {
3888                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3889                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3890                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3891                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3892                 } else {
3893                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3894                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3895                 }
3896         } else {
3897                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3898                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3899                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3900                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3901                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3902         }
3903         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3904                 WREG32(CG_THERMAL_INT, thermal_int);
3905         } else if (rdev->family >= CHIP_RV770) {
3906                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3907         }
3908 
3909         /* posting read */
3910         RREG32(R_000E50_SRBM_STATUS);
3911 
3912         return 0;
3913 }
3914 
3915 static void r600_irq_ack(struct radeon_device *rdev)
3916 {
3917         u32 tmp;
3918 
3919         if (ASIC_IS_DCE3(rdev)) {
3920                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3921                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3922                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3923                 if (ASIC_IS_DCE32(rdev)) {
3924                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3925                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3926                 } else {
3927                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3928                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3929                 }
3930         } else {
3931                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3932                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3933                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3934                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3935                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3936         }
3937         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3938         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3939 
3940         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3941                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3942         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3943                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3944         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3945                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3946         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3947                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3948         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3949                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3950         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3951                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3952         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3953                 if (ASIC_IS_DCE3(rdev)) {
3954                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3955                         tmp |= DC_HPDx_INT_ACK;
3956                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3957                 } else {
3958                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3959                         tmp |= DC_HPDx_INT_ACK;
3960                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3961                 }
3962         }
3963         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3964                 if (ASIC_IS_DCE3(rdev)) {
3965                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3966                         tmp |= DC_HPDx_INT_ACK;
3967                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3968                 } else {
3969                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3970                         tmp |= DC_HPDx_INT_ACK;
3971                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3972                 }
3973         }
3974         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3975                 if (ASIC_IS_DCE3(rdev)) {
3976                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3977                         tmp |= DC_HPDx_INT_ACK;
3978                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3979                 } else {
3980                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3981                         tmp |= DC_HPDx_INT_ACK;
3982                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3983                 }
3984         }
3985         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3986                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3987                 tmp |= DC_HPDx_INT_ACK;
3988                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3989         }
3990         if (ASIC_IS_DCE32(rdev)) {
3991                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3992                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3993                         tmp |= DC_HPDx_INT_ACK;
3994                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3995                 }
3996                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3997                         tmp = RREG32(DC_HPD6_INT_CONTROL);
3998                         tmp |= DC_HPDx_INT_ACK;
3999                         WREG32(DC_HPD6_INT_CONTROL, tmp);
4000                 }
4001                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4002                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
4003                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4004                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4005                 }
4006                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4007                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
4008                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4009                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4010                 }
4011         } else {
4012                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4013                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4014                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4015                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4016                 }
4017                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4018                         if (ASIC_IS_DCE3(rdev)) {
4019                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4020                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4021                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4022                         } else {
4023                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4024                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4025                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4026                         }
4027                 }
4028         }
4029 }
4030 
4031 void r600_irq_disable(struct radeon_device *rdev)
4032 {
4033         r600_disable_interrupts(rdev);
4034         /* Wait and acknowledge irq */
4035         mdelay(1);
4036         r600_irq_ack(rdev);
4037         r600_disable_interrupt_state(rdev);
4038 }
4039 
4040 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4041 {
4042         u32 wptr, tmp;
4043 
4044         if (rdev->wb.enabled)
4045                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4046         else
4047                 wptr = RREG32(IH_RB_WPTR);
4048 
4049         if (wptr & RB_OVERFLOW) {
4050                 wptr &= ~RB_OVERFLOW;
4051                 /* When a ring buffer overflow happen start parsing interrupt
4052                  * from the last not overwritten vector (wptr + 16). Hopefully
4053                  * this should allow us to catchup.
4054                  */
4055                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4056                          wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4057                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4058                 tmp = RREG32(IH_RB_CNTL);
4059                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4060                 WREG32(IH_RB_CNTL, tmp);
4061         }
4062         return (wptr & rdev->ih.ptr_mask);
4063 }
4064 
4065 /*        r600 IV Ring
4066  * Each IV ring entry is 128 bits:
4067  * [7:0]    - interrupt source id
4068  * [31:8]   - reserved
4069  * [59:32]  - interrupt source data
4070  * [127:60]  - reserved
4071  *
4072  * The basic interrupt vector entries
4073  * are decoded as follows:
4074  * src_id  src_data  description
4075  *      1         0  D1 Vblank
4076  *      1         1  D1 Vline
4077  *      5         0  D2 Vblank
4078  *      5         1  D2 Vline
4079  *     19         0  FP Hot plug detection A
4080  *     19         1  FP Hot plug detection B
4081  *     19         2  DAC A auto-detection
4082  *     19         3  DAC B auto-detection
4083  *     21         4  HDMI block A
4084  *     21         5  HDMI block B
4085  *    176         -  CP_INT RB
4086  *    177         -  CP_INT IB1
4087  *    178         -  CP_INT IB2
4088  *    181         -  EOP Interrupt
4089  *    233         -  GUI Idle
4090  *
4091  * Note, these are based on r600 and may need to be
4092  * adjusted or added to on newer asics
4093  */
4094 
4095 int r600_irq_process(struct radeon_device *rdev)
4096 {
4097         u32 wptr;
4098         u32 rptr;
4099         u32 src_id, src_data;
4100         u32 ring_index;
4101         bool queue_hotplug = false;
4102         bool queue_hdmi = false;
4103         bool queue_thermal = false;
4104 
4105         if (!rdev->ih.enabled || rdev->shutdown)
4106                 return IRQ_NONE;
4107 
4108         /* No MSIs, need a dummy read to flush PCI DMAs */
4109         if (!rdev->msi_enabled)
4110                 RREG32(IH_RB_WPTR);
4111 
4112         wptr = r600_get_ih_wptr(rdev);
4113 
4114 restart_ih:
4115         /* is somebody else already processing irqs? */
4116         if (atomic_xchg(&rdev->ih.lock, 1))
4117                 return IRQ_NONE;
4118 
4119         rptr = rdev->ih.rptr;
4120         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4121 
4122         /* Order reading of wptr vs. reading of IH ring data */
4123         rmb();
4124 
4125         /* display interrupts */
4126         r600_irq_ack(rdev);
4127 
4128         while (rptr != wptr) {
4129                 /* wptr/rptr are in bytes! */
4130                 ring_index = rptr / 4;
4131                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4132                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4133 
4134                 switch (src_id) {
4135                 case 1: /* D1 vblank/vline */
4136                         switch (src_data) {
4137                         case 0: /* D1 vblank */
4138                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4139                                         DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4140 
4141                                 if (rdev->irq.crtc_vblank_int[0]) {
4142                                         drm_handle_vblank(rdev->ddev, 0);
4143                                         rdev->pm.vblank_sync = true;
4144                                         wake_up(&rdev->irq.vblank_queue);
4145                                 }
4146                                 if (atomic_read(&rdev->irq.pflip[0]))
4147                                         radeon_crtc_handle_vblank(rdev, 0);
4148                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4149                                 DRM_DEBUG("IH: D1 vblank\n");
4150 
4151                                 break;
4152                         case 1: /* D1 vline */
4153                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4154                                     DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4155 
4156                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4157                                 DRM_DEBUG("IH: D1 vline\n");
4158 
4159                                 break;
4160                         default:
4161                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4162                                 break;
4163                         }
4164                         break;
4165                 case 5: /* D2 vblank/vline */
4166                         switch (src_data) {
4167                         case 0: /* D2 vblank */
4168                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4169                                         DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4170 
4171                                 if (rdev->irq.crtc_vblank_int[1]) {
4172                                         drm_handle_vblank(rdev->ddev, 1);
4173                                         rdev->pm.vblank_sync = true;
4174                                         wake_up(&rdev->irq.vblank_queue);
4175                                 }
4176                                 if (atomic_read(&rdev->irq.pflip[1]))
4177                                         radeon_crtc_handle_vblank(rdev, 1);
4178                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4179                                 DRM_DEBUG("IH: D2 vblank\n");
4180 
4181                                 break;
4182                         case 1: /* D1 vline */
4183                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4184                                         DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4185 
4186                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4187                                 DRM_DEBUG("IH: D2 vline\n");
4188 
4189                                 break;
4190                         default:
4191                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4192                                 break;
4193                         }
4194                         break;
4195                 case 9: /* D1 pflip */
4196                         DRM_DEBUG("IH: D1 flip\n");
4197                         if (radeon_use_pflipirq > 0)
4198                                 radeon_crtc_handle_flip(rdev, 0);
4199                         break;
4200                 case 11: /* D2 pflip */
4201                         DRM_DEBUG("IH: D2 flip\n");
4202                         if (radeon_use_pflipirq > 0)
4203                                 radeon_crtc_handle_flip(rdev, 1);
4204                         break;
4205                 case 19: /* HPD/DAC hotplug */
4206                         switch (src_data) {
4207                         case 0:
4208                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4209                                         DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4210 
4211                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4212                                 queue_hotplug = true;
4213                                 DRM_DEBUG("IH: HPD1\n");
4214                                 break;
4215                         case 1:
4216                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4217                                         DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4218 
4219                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4220                                 queue_hotplug = true;
4221                                 DRM_DEBUG("IH: HPD2\n");
4222                                 break;
4223                         case 4:
4224                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4225                                         DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4226 
4227                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4228                                 queue_hotplug = true;
4229                                 DRM_DEBUG("IH: HPD3\n");
4230                                 break;
4231                         case 5:
4232                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4233                                         DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4234 
4235                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4236                                 queue_hotplug = true;
4237                                 DRM_DEBUG("IH: HPD4\n");
4238                                 break;
4239                         case 10:
4240                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4241                                         DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4242 
4243                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4244                                 queue_hotplug = true;
4245                                 DRM_DEBUG("IH: HPD5\n");
4246                                 break;
4247                         case 12:
4248                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4249                                         DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4250 
4251                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4252                                 queue_hotplug = true;
4253                                 DRM_DEBUG("IH: HPD6\n");
4254 
4255                                 break;
4256                         default:
4257                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4258                                 break;
4259                         }
4260                         break;
4261                 case 21: /* hdmi */
4262                         switch (src_data) {
4263                         case 4:
4264                                 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4265                                         DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4266 
4267                                 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4268                                 queue_hdmi = true;
4269                                 DRM_DEBUG("IH: HDMI0\n");
4270 
4271                                 break;
4272                         case 5:
4273                                 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4274                                         DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4275 
4276                                 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4277                                 queue_hdmi = true;
4278                                 DRM_DEBUG("IH: HDMI1\n");
4279 
4280                                 break;
4281                         default:
4282                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4283                                 break;
4284                         }
4285                         break;
4286                 case 124: /* UVD */
4287                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4288                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4289                         break;
4290                 case 176: /* CP_INT in ring buffer */
4291                 case 177: /* CP_INT in IB1 */
4292                 case 178: /* CP_INT in IB2 */
4293                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4294                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4295                         break;
4296                 case 181: /* CP EOP event */
4297                         DRM_DEBUG("IH: CP EOP\n");
4298                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4299                         break;
4300                 case 224: /* DMA trap event */
4301                         DRM_DEBUG("IH: DMA trap\n");
4302                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4303                         break;
4304                 case 230: /* thermal low to high */
4305                         DRM_DEBUG("IH: thermal low to high\n");
4306                         rdev->pm.dpm.thermal.high_to_low = false;
4307                         queue_thermal = true;
4308                         break;
4309                 case 231: /* thermal high to low */
4310                         DRM_DEBUG("IH: thermal high to low\n");
4311                         rdev->pm.dpm.thermal.high_to_low = true;
4312                         queue_thermal = true;
4313                         break;
4314                 case 233: /* GUI IDLE */
4315                         DRM_DEBUG("IH: GUI idle\n");
4316                         break;
4317                 default:
4318                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4319                         break;
4320                 }
4321 
4322                 /* wptr/rptr are in bytes! */
4323                 rptr += 16;
4324                 rptr &= rdev->ih.ptr_mask;
4325                 WREG32(IH_RB_RPTR, rptr);
4326         }
4327         if (queue_hotplug)
4328                 schedule_delayed_work(&rdev->hotplug_work, 0);
4329         if (queue_hdmi)
4330                 schedule_work(&rdev->audio_work);
4331         if (queue_thermal && rdev->pm.dpm_enabled)
4332                 schedule_work(&rdev->pm.dpm.thermal.work);
4333         rdev->ih.rptr = rptr;
4334         atomic_set(&rdev->ih.lock, 0);
4335 
4336         /* make sure wptr hasn't changed while processing */
4337         wptr = r600_get_ih_wptr(rdev);
4338         if (wptr != rptr)
4339                 goto restart_ih;
4340 
4341         return IRQ_HANDLED;
4342 }
4343 
4344 /*
4345  * Debugfs info
4346  */
4347 #if defined(CONFIG_DEBUG_FS)
4348 
4349 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4350 {
4351         struct drm_info_node *node = (struct drm_info_node *) m->private;
4352         struct drm_device *dev = node->minor->dev;
4353         struct radeon_device *rdev = dev->dev_private;
4354 
4355         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4356         DREG32_SYS(m, rdev, VM_L2_STATUS);
4357         return 0;
4358 }
4359 
4360 static struct drm_info_list r600_mc_info_list[] = {
4361         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4362 };
4363 #endif
4364 
4365 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4366 {
4367 #if defined(CONFIG_DEBUG_FS)
4368         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4369 #else
4370         return 0;
4371 #endif
4372 }
4373 
4374 /**
4375  * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4376  * rdev: radeon device structure
4377  *
4378  * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4379  * through the ring buffer. This leads to corruption in rendering, see
4380  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4381  * directly perform the HDP flush by writing the register through MMIO.
4382  */
4383 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4384 {
4385         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4386          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4387          * This seems to cause problems on some AGP cards. Just use the old
4388          * method for them.
4389          */
4390         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4391             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4392                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4393                 u32 tmp;
4394 
4395                 WREG32(HDP_DEBUG1, 0);
4396                 tmp = readl((void __iomem *)ptr);
4397         } else
4398                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4399 }
4400 
4401 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4402 {
4403         u32 link_width_cntl, mask;
4404 
4405         if (rdev->flags & RADEON_IS_IGP)
4406                 return;
4407 
4408         if (!(rdev->flags & RADEON_IS_PCIE))
4409                 return;
4410 
4411         /* x2 cards have a special sequence */
4412         if (ASIC_IS_X2(rdev))
4413                 return;
4414 
4415         radeon_gui_idle(rdev);
4416 
4417         switch (lanes) {
4418         case 0:
4419                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4420                 break;
4421         case 1:
4422                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4423                 break;
4424         case 2:
4425                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4426                 break;
4427         case 4:
4428                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4429                 break;
4430         case 8:
4431                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4432                 break;
4433         case 12:
4434                 /* not actually supported */
4435                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4436                 break;
4437         case 16:
4438                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4439                 break;
4440         default:
4441                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4442                 return;
4443         }
4444 
4445         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4446         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4447         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4448         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4449                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4450 
4451         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4452 }
4453 
4454 int r600_get_pcie_lanes(struct radeon_device *rdev)
4455 {
4456         u32 link_width_cntl;
4457 
4458         if (rdev->flags & RADEON_IS_IGP)
4459                 return 0;
4460 
4461         if (!(rdev->flags & RADEON_IS_PCIE))
4462                 return 0;
4463 
4464         /* x2 cards have a special sequence */
4465         if (ASIC_IS_X2(rdev))
4466                 return 0;
4467 
4468         radeon_gui_idle(rdev);
4469 
4470         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4471 
4472         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4473         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4474                 return 1;
4475         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4476                 return 2;
4477         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4478                 return 4;
4479         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4480                 return 8;
4481         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4482                 /* not actually supported */
4483                 return 12;
4484         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4485         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4486         default:
4487                 return 16;
4488         }
4489 }
4490 
4491 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4492 {
4493         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4494         u16 link_cntl2;
4495 
4496         if (radeon_pcie_gen2 == 0)
4497                 return;
4498 
4499         if (rdev->flags & RADEON_IS_IGP)
4500                 return;
4501 
4502         if (!(rdev->flags & RADEON_IS_PCIE))
4503                 return;
4504 
4505         /* x2 cards have a special sequence */
4506         if (ASIC_IS_X2(rdev))
4507                 return;
4508 
4509         /* only RV6xx+ chips are supported */
4510         if (rdev->family <= CHIP_R600)
4511                 return;
4512 
4513         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4514                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4515                 return;
4516 
4517         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4518         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4519                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4520                 return;
4521         }
4522 
4523         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4524 
4525         /* 55 nm r6xx asics */
4526         if ((rdev->family == CHIP_RV670) ||
4527             (rdev->family == CHIP_RV620) ||
4528             (rdev->family == CHIP_RV635)) {
4529                 /* advertise upconfig capability */
4530                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4531                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4532                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4533                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4534                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4535                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4536                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4537                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4538                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4539                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4540                 } else {
4541                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4542                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4543                 }
4544         }
4545 
4546         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4547         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4548             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4549 
4550                 /* 55 nm r6xx asics */
4551                 if ((rdev->family == CHIP_RV670) ||
4552                     (rdev->family == CHIP_RV620) ||
4553                     (rdev->family == CHIP_RV635)) {
4554                         WREG32(MM_CFGREGS_CNTL, 0x8);
4555                         link_cntl2 = RREG32(0x4088);
4556                         WREG32(MM_CFGREGS_CNTL, 0);
4557                         /* not supported yet */
4558                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4559                                 return;
4560                 }
4561 
4562                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4563                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4564                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4565                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4566                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4567                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4568 
4569                 tmp = RREG32(0x541c);
4570                 WREG32(0x541c, tmp | 0x8);
4571                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4572                 link_cntl2 = RREG16(0x4088);
4573                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4574                 link_cntl2 |= 0x2;
4575                 WREG16(0x4088, link_cntl2);
4576                 WREG32(MM_CFGREGS_CNTL, 0);
4577 
4578                 if ((rdev->family == CHIP_RV670) ||
4579                     (rdev->family == CHIP_RV620) ||
4580                     (rdev->family == CHIP_RV635)) {
4581                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4582                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4583                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4584                 } else {
4585                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4586                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4587                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4588                 }
4589 
4590                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4591                 speed_cntl |= LC_GEN2_EN_STRAP;
4592                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4593 
4594         } else {
4595                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4596                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4597                 if (1)
4598                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4599                 else
4600                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4601                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4602         }
4603 }
4604 
4605 /**
4606  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4607  *
4608  * @rdev: radeon_device pointer
4609  *
4610  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4611  * Returns the 64 bit clock counter snapshot.
4612  */
4613 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4614 {
4615         uint64_t clock;
4616 
4617         mutex_lock(&rdev->gpu_clock_mutex);
4618         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4619         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4620                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4621         mutex_unlock(&rdev->gpu_clock_mutex);
4622         return clock;
4623 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/radeon/r600.c

DEFINITIONS
