drivers/gpu/drm/radeon/vce_v2

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This source file includes following definitions.
vce_v2_0_set_sw_cg
vce_v2_0_set_dyn_cg
vce_v2_0_disable_cg
vce_v2_0_enable_mgcg
vce_v2_0_init_cg
vce_v2_0_bo_size
vce_v2_0_resume
   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27 
  28 #include <linux/firmware.h>
  29 
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "cikd.h"
  33 
  34 #define VCE_V2_0_FW_SIZE        (256 * 1024)
  35 #define VCE_V2_0_STACK_SIZE     (64 * 1024)
  36 #define VCE_V2_0_DATA_SIZE      (23552 * RADEON_MAX_VCE_HANDLES)
  37 
  38 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
  39 {
  40         u32 tmp;
  41 
  42         if (gated) {
  43                 tmp = RREG32(VCE_CLOCK_GATING_B);
  44                 tmp |= 0xe70000;
  45                 WREG32(VCE_CLOCK_GATING_B, tmp);
  46 
  47                 tmp = RREG32(VCE_UENC_CLOCK_GATING);
  48                 tmp |= 0xff000000;
  49                 WREG32(VCE_UENC_CLOCK_GATING, tmp);
  50 
  51                 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
  52                 tmp &= ~0x3fc;
  53                 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
  54 
  55                 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
  56         } else {
  57                 tmp = RREG32(VCE_CLOCK_GATING_B);
  58                 tmp |= 0xe7;
  59                 tmp &= ~0xe70000;
  60                 WREG32(VCE_CLOCK_GATING_B, tmp);
  61 
  62                 tmp = RREG32(VCE_UENC_CLOCK_GATING);
  63                 tmp |= 0x1fe000;
  64                 tmp &= ~0xff000000;
  65                 WREG32(VCE_UENC_CLOCK_GATING, tmp);
  66 
  67                 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
  68                 tmp |= 0x3fc;
  69                 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
  70         }
  71 }
  72 
  73 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
  74 {
  75         u32 orig, tmp;
  76 
  77         tmp = RREG32(VCE_CLOCK_GATING_B);
  78         tmp &= ~0x00060006;
  79         if (gated) {
  80                 tmp |= 0xe10000;
  81         } else {
  82                 tmp |= 0xe1;
  83                 tmp &= ~0xe10000;
  84         }
  85         WREG32(VCE_CLOCK_GATING_B, tmp);
  86 
  87         orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
  88         tmp &= ~0x1fe000;
  89         tmp &= ~0xff000000;
  90         if (tmp != orig)
  91                 WREG32(VCE_UENC_CLOCK_GATING, tmp);
  92 
  93         orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
  94         tmp &= ~0x3fc;
  95         if (tmp != orig)
  96                 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
  97 
  98         if (gated)
  99                 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
 100 }
 101 
 102 static void vce_v2_0_disable_cg(struct radeon_device *rdev)
 103 {
 104         WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
 105 }
 106 
 107 /*
 108  * Local variable sw_cg is used for debugging purposes, in case we
 109  * ran into problems with dynamic clock gating. Don't remove it.
 110  */
 111 void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
 112 {
 113         bool sw_cg = false;
 114 
 115         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
 116                 if (sw_cg)
 117                         vce_v2_0_set_sw_cg(rdev, true);
 118                 else
 119                         vce_v2_0_set_dyn_cg(rdev, true);
 120         } else {
 121                 vce_v2_0_disable_cg(rdev);
 122 
 123                 if (sw_cg)
 124                         vce_v2_0_set_sw_cg(rdev, false);
 125                 else
 126                         vce_v2_0_set_dyn_cg(rdev, false);
 127         }
 128 }
 129 
 130 static void vce_v2_0_init_cg(struct radeon_device *rdev)
 131 {
 132         u32 tmp;
 133 
 134         tmp = RREG32(VCE_CLOCK_GATING_A);
 135         tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
 136         tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
 137         tmp |= CGC_UENC_WAIT_AWAKE;
 138         WREG32(VCE_CLOCK_GATING_A, tmp);
 139 
 140         tmp = RREG32(VCE_UENC_CLOCK_GATING);
 141         tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
 142         tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
 143         WREG32(VCE_UENC_CLOCK_GATING, tmp);
 144 
 145         tmp = RREG32(VCE_CLOCK_GATING_B);
 146         tmp |= 0x10;
 147         tmp &= ~0x100000;
 148         WREG32(VCE_CLOCK_GATING_B, tmp);
 149 }
 150 
 151 unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
 152 {
 153         WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
 154         return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
 155 }
 156 
 157 int vce_v2_0_resume(struct radeon_device *rdev)
 158 {
 159         uint64_t addr = rdev->vce.gpu_addr;
 160         uint32_t size;
 161 
 162         WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
 163         WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
 164         WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
 165         WREG32(VCE_CLOCK_GATING_B, 0xf7);
 166 
 167         WREG32(VCE_LMI_CTRL, 0x00398000);
 168         WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
 169         WREG32(VCE_LMI_SWAP_CNTL, 0);
 170         WREG32(VCE_LMI_SWAP_CNTL1, 0);
 171         WREG32(VCE_LMI_VM_CTRL, 0);
 172 
 173         WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
 174 
 175         addr &= 0xff;
 176         size = VCE_V2_0_FW_SIZE;
 177         WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
 178         WREG32(VCE_VCPU_CACHE_SIZE0, size);
 179 
 180         addr += size;
 181         size = VCE_V2_0_STACK_SIZE;
 182         WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
 183         WREG32(VCE_VCPU_CACHE_SIZE1, size);
 184 
 185         addr += size;
 186         size = VCE_V2_0_DATA_SIZE;
 187         WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
 188         WREG32(VCE_VCPU_CACHE_SIZE2, size);
 189 
 190         WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
 191 
 192         WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
 193                  ~VCE_SYS_INT_TRAP_INTERRUPT_EN);
 194 
 195         vce_v2_0_init_cg(rdev);
 196 
 197         return 0;
 198 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/radeon/vce_v2_0.c

DEFINITIONS
