drivers/gpu/drm/radeon/radeon

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This source file includes following definitions.
radeon_has_atpx_dgpu_power_cntl
radeon_is_atpx_hybrid
radeon_is_px
radeon_device_handle_px_quirks
radeon_program_register_sequence
radeon_pci_config_reset
radeon_surface_init
radeon_scratch_init
radeon_scratch_get
radeon_scratch_free
radeon_doorbell_init
radeon_doorbell_fini
radeon_doorbell_get
radeon_doorbell_free
radeon_wb_disable
radeon_wb_fini
radeon_wb_init
radeon_vram_location
radeon_gtt_location
radeon_device_is_virtual
radeon_card_posted
radeon_update_bandwidth_info
radeon_boot_test_post_card
radeon_dummy_page_init
radeon_dummy_page_fini
cail_pll_read
cail_pll_write
cail_mc_read
cail_mc_write
cail_reg_write
cail_reg_read
cail_ioreg_write
cail_ioreg_read
radeon_atombios_init
radeon_atombios_fini
radeon_combios_init
radeon_combios_fini
radeon_vga_set_decode
radeon_check_pot_argument
radeon_gart_size_auto
radeon_check_arguments
radeon_switcheroo_set_state
radeon_switcheroo_can_switch
radeon_device_init
radeon_device_fini
radeon_suspend_kms
radeon_resume_kms
radeon_gpu_reset
radeon_debugfs_add_files
   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 
  29 #include <linux/console.h>
  30 #include <linux/efi.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/slab.h>
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/vgaarb.h>
  35 
  36 #include <drm/drm_cache.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_debugfs.h>
  39 #include <drm/drm_device.h>
  40 #include <drm/drm_file.h>
  41 #include <drm/drm_pci.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/radeon_drm.h>
  44 
  45 #include "radeon_reg.h"
  46 #include "radeon.h"
  47 #include "atom.h"
  48 
  49 static const char radeon_family_name[][16] = {
  50         "R100",
  51         "RV100",
  52         "RS100",
  53         "RV200",
  54         "RS200",
  55         "R200",
  56         "RV250",
  57         "RS300",
  58         "RV280",
  59         "R300",
  60         "R350",
  61         "RV350",
  62         "RV380",
  63         "R420",
  64         "R423",
  65         "RV410",
  66         "RS400",
  67         "RS480",
  68         "RS600",
  69         "RS690",
  70         "RS740",
  71         "RV515",
  72         "R520",
  73         "RV530",
  74         "RV560",
  75         "RV570",
  76         "R580",
  77         "R600",
  78         "RV610",
  79         "RV630",
  80         "RV670",
  81         "RV620",
  82         "RV635",
  83         "RS780",
  84         "RS880",
  85         "RV770",
  86         "RV730",
  87         "RV710",
  88         "RV740",
  89         "CEDAR",
  90         "REDWOOD",
  91         "JUNIPER",
  92         "CYPRESS",
  93         "HEMLOCK",
  94         "PALM",
  95         "SUMO",
  96         "SUMO2",
  97         "BARTS",
  98         "TURKS",
  99         "CAICOS",
 100         "CAYMAN",
 101         "ARUBA",
 102         "TAHITI",
 103         "PITCAIRN",
 104         "VERDE",
 105         "OLAND",
 106         "HAINAN",
 107         "BONAIRE",
 108         "KAVERI",
 109         "KABINI",
 110         "HAWAII",
 111         "MULLINS",
 112         "LAST",
 113 };
 114 
 115 #if defined(CONFIG_VGA_SWITCHEROO)
 116 bool radeon_has_atpx_dgpu_power_cntl(void);
 117 bool radeon_is_atpx_hybrid(void);
 118 #else
 119 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
 120 static inline bool radeon_is_atpx_hybrid(void) { return false; }
 121 #endif
 122 
 123 #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
 124 
 125 struct radeon_px_quirk {
 126         u32 chip_vendor;
 127         u32 chip_device;
 128         u32 subsys_vendor;
 129         u32 subsys_device;
 130         u32 px_quirk_flags;
 131 };
 132 
 133 static struct radeon_px_quirk radeon_px_quirk_list[] = {
 134         /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
 135          * https://bugzilla.kernel.org/show_bug.cgi?id=74551
 136          */
 137         { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
 138         /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
 139          * https://bugzilla.kernel.org/show_bug.cgi?id=51381
 140          */
 141         { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
 142         /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
 143          * https://bugzilla.kernel.org/show_bug.cgi?id=51381
 144          */
 145         { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
 146         /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
 147          * https://bugs.freedesktop.org/show_bug.cgi?id=101491
 148          */
 149         { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
 150         /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
 151          * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52
 152          */
 153         { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX },
 154         { 0, 0, 0, 0, 0 },
 155 };
 156 
 157 bool radeon_is_px(struct drm_device *dev)
 158 {
 159         struct radeon_device *rdev = dev->dev_private;
 160 
 161         if (rdev->flags & RADEON_IS_PX)
 162                 return true;
 163         return false;
 164 }
 165 
 166 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
 167 {
 168         struct radeon_px_quirk *p = radeon_px_quirk_list;
 169 
 170         /* Apply PX quirks */
 171         while (p && p->chip_device != 0) {
 172                 if (rdev->pdev->vendor == p->chip_vendor &&
 173                     rdev->pdev->device == p->chip_device &&
 174                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
 175                     rdev->pdev->subsystem_device == p->subsys_device) {
 176                         rdev->px_quirk_flags = p->px_quirk_flags;
 177                         break;
 178                 }
 179                 ++p;
 180         }
 181 
 182         if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
 183                 rdev->flags &= ~RADEON_IS_PX;
 184 
 185         /* disable PX is the system doesn't support dGPU power control or hybrid gfx */
 186         if (!radeon_is_atpx_hybrid() &&
 187             !radeon_has_atpx_dgpu_power_cntl())
 188                 rdev->flags &= ~RADEON_IS_PX;
 189 }
 190 
 191 /**
 192  * radeon_program_register_sequence - program an array of registers.
 193  *
 194  * @rdev: radeon_device pointer
 195  * @registers: pointer to the register array
 196  * @array_size: size of the register array
 197  *
 198  * Programs an array or registers with and and or masks.
 199  * This is a helper for setting golden registers.
 200  */
 201 void radeon_program_register_sequence(struct radeon_device *rdev,
 202                                       const u32 *registers,
 203                                       const u32 array_size)
 204 {
 205         u32 tmp, reg, and_mask, or_mask;
 206         int i;
 207 
 208         if (array_size % 3)
 209                 return;
 210 
 211         for (i = 0; i < array_size; i +=3) {
 212                 reg = registers[i + 0];
 213                 and_mask = registers[i + 1];
 214                 or_mask = registers[i + 2];
 215 
 216                 if (and_mask == 0xffffffff) {
 217                         tmp = or_mask;
 218                 } else {
 219                         tmp = RREG32(reg);
 220                         tmp &= ~and_mask;
 221                         tmp |= or_mask;
 222                 }
 223                 WREG32(reg, tmp);
 224         }
 225 }
 226 
 227 void radeon_pci_config_reset(struct radeon_device *rdev)
 228 {
 229         pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
 230 }
 231 
 232 /**
 233  * radeon_surface_init - Clear GPU surface registers.
 234  *
 235  * @rdev: radeon_device pointer
 236  *
 237  * Clear GPU surface registers (r1xx-r5xx).
 238  */
 239 void radeon_surface_init(struct radeon_device *rdev)
 240 {
 241         /* FIXME: check this out */
 242         if (rdev->family < CHIP_R600) {
 243                 int i;
 244 
 245                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 246                         if (rdev->surface_regs[i].bo)
 247                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 248                         else
 249                                 radeon_clear_surface_reg(rdev, i);
 250                 }
 251                 /* enable surfaces */
 252                 WREG32(RADEON_SURFACE_CNTL, 0);
 253         }
 254 }
 255 
 256 /*
 257  * GPU scratch registers helpers function.
 258  */
 259 /**
 260  * radeon_scratch_init - Init scratch register driver information.
 261  *
 262  * @rdev: radeon_device pointer
 263  *
 264  * Init CP scratch register driver information (r1xx-r5xx)
 265  */
 266 void radeon_scratch_init(struct radeon_device *rdev)
 267 {
 268         int i;
 269 
 270         /* FIXME: check this out */
 271         if (rdev->family < CHIP_R300) {
 272                 rdev->scratch.num_reg = 5;
 273         } else {
 274                 rdev->scratch.num_reg = 7;
 275         }
 276         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 277         for (i = 0; i < rdev->scratch.num_reg; i++) {
 278                 rdev->scratch.free[i] = true;
 279                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 280         }
 281 }
 282 
 283 /**
 284  * radeon_scratch_get - Allocate a scratch register
 285  *
 286  * @rdev: radeon_device pointer
 287  * @reg: scratch register mmio offset
 288  *
 289  * Allocate a CP scratch register for use by the driver (all asics).
 290  * Returns 0 on success or -EINVAL on failure.
 291  */
 292 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 293 {
 294         int i;
 295 
 296         for (i = 0; i < rdev->scratch.num_reg; i++) {
 297                 if (rdev->scratch.free[i]) {
 298                         rdev->scratch.free[i] = false;
 299                         *reg = rdev->scratch.reg[i];
 300                         return 0;
 301                 }
 302         }
 303         return -EINVAL;
 304 }
 305 
 306 /**
 307  * radeon_scratch_free - Free a scratch register
 308  *
 309  * @rdev: radeon_device pointer
 310  * @reg: scratch register mmio offset
 311  *
 312  * Free a CP scratch register allocated for use by the driver (all asics)
 313  */
 314 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 315 {
 316         int i;
 317 
 318         for (i = 0; i < rdev->scratch.num_reg; i++) {
 319                 if (rdev->scratch.reg[i] == reg) {
 320                         rdev->scratch.free[i] = true;
 321                         return;
 322                 }
 323         }
 324 }
 325 
 326 /*
 327  * GPU doorbell aperture helpers function.
 328  */
 329 /**
 330  * radeon_doorbell_init - Init doorbell driver information.
 331  *
 332  * @rdev: radeon_device pointer
 333  *
 334  * Init doorbell driver information (CIK)
 335  * Returns 0 on success, error on failure.
 336  */
 337 static int radeon_doorbell_init(struct radeon_device *rdev)
 338 {
 339         /* doorbell bar mapping */
 340         rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
 341         rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
 342 
 343         rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
 344         if (rdev->doorbell.num_doorbells == 0)
 345                 return -EINVAL;
 346 
 347         rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
 348         if (rdev->doorbell.ptr == NULL) {
 349                 return -ENOMEM;
 350         }
 351         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
 352         DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
 353 
 354         memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
 355 
 356         return 0;
 357 }
 358 
 359 /**
 360  * radeon_doorbell_fini - Tear down doorbell driver information.
 361  *
 362  * @rdev: radeon_device pointer
 363  *
 364  * Tear down doorbell driver information (CIK)
 365  */
 366 static void radeon_doorbell_fini(struct radeon_device *rdev)
 367 {
 368         iounmap(rdev->doorbell.ptr);
 369         rdev->doorbell.ptr = NULL;
 370 }
 371 
 372 /**
 373  * radeon_doorbell_get - Allocate a doorbell entry
 374  *
 375  * @rdev: radeon_device pointer
 376  * @doorbell: doorbell index
 377  *
 378  * Allocate a doorbell for use by the driver (all asics).
 379  * Returns 0 on success or -EINVAL on failure.
 380  */
 381 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
 382 {
 383         unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
 384         if (offset < rdev->doorbell.num_doorbells) {
 385                 __set_bit(offset, rdev->doorbell.used);
 386                 *doorbell = offset;
 387                 return 0;
 388         } else {
 389                 return -EINVAL;
 390         }
 391 }
 392 
 393 /**
 394  * radeon_doorbell_free - Free a doorbell entry
 395  *
 396  * @rdev: radeon_device pointer
 397  * @doorbell: doorbell index
 398  *
 399  * Free a doorbell allocated for use by the driver (all asics)
 400  */
 401 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
 402 {
 403         if (doorbell < rdev->doorbell.num_doorbells)
 404                 __clear_bit(doorbell, rdev->doorbell.used);
 405 }
 406 
 407 /*
 408  * radeon_wb_*()
 409  * Writeback is the the method by which the the GPU updates special pages
 410  * in memory with the status of certain GPU events (fences, ring pointers,
 411  * etc.).
 412  */
 413 
 414 /**
 415  * radeon_wb_disable - Disable Writeback
 416  *
 417  * @rdev: radeon_device pointer
 418  *
 419  * Disables Writeback (all asics).  Used for suspend.
 420  */
 421 void radeon_wb_disable(struct radeon_device *rdev)
 422 {
 423         rdev->wb.enabled = false;
 424 }
 425 
 426 /**
 427  * radeon_wb_fini - Disable Writeback and free memory
 428  *
 429  * @rdev: radeon_device pointer
 430  *
 431  * Disables Writeback and frees the Writeback memory (all asics).
 432  * Used at driver shutdown.
 433  */
 434 void radeon_wb_fini(struct radeon_device *rdev)
 435 {
 436         radeon_wb_disable(rdev);
 437         if (rdev->wb.wb_obj) {
 438                 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
 439                         radeon_bo_kunmap(rdev->wb.wb_obj);
 440                         radeon_bo_unpin(rdev->wb.wb_obj);
 441                         radeon_bo_unreserve(rdev->wb.wb_obj);
 442                 }
 443                 radeon_bo_unref(&rdev->wb.wb_obj);
 444                 rdev->wb.wb = NULL;
 445                 rdev->wb.wb_obj = NULL;
 446         }
 447 }
 448 
 449 /**
 450  * radeon_wb_init- Init Writeback driver info and allocate memory
 451  *
 452  * @rdev: radeon_device pointer
 453  *
 454  * Disables Writeback and frees the Writeback memory (all asics).
 455  * Used at driver startup.
 456  * Returns 0 on success or an -error on failure.
 457  */
 458 int radeon_wb_init(struct radeon_device *rdev)
 459 {
 460         int r;
 461 
 462         if (rdev->wb.wb_obj == NULL) {
 463                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 464                                      RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
 465                                      &rdev->wb.wb_obj);
 466                 if (r) {
 467                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 468                         return r;
 469                 }
 470                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 471                 if (unlikely(r != 0)) {
 472                         radeon_wb_fini(rdev);
 473                         return r;
 474                 }
 475                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 476                                 &rdev->wb.gpu_addr);
 477                 if (r) {
 478                         radeon_bo_unreserve(rdev->wb.wb_obj);
 479                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 480                         radeon_wb_fini(rdev);
 481                         return r;
 482                 }
 483                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 484                 radeon_bo_unreserve(rdev->wb.wb_obj);
 485                 if (r) {
 486                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 487                         radeon_wb_fini(rdev);
 488                         return r;
 489                 }
 490         }
 491 
 492         /* clear wb memory */
 493         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 494         /* disable event_write fences */
 495         rdev->wb.use_event = false;
 496         /* disabled via module param */
 497         if (radeon_no_wb == 1) {
 498                 rdev->wb.enabled = false;
 499         } else {
 500                 if (rdev->flags & RADEON_IS_AGP) {
 501                         /* often unreliable on AGP */
 502                         rdev->wb.enabled = false;
 503                 } else if (rdev->family < CHIP_R300) {
 504                         /* often unreliable on pre-r300 */
 505                         rdev->wb.enabled = false;
 506                 } else {
 507                         rdev->wb.enabled = true;
 508                         /* event_write fences are only available on r600+ */
 509                         if (rdev->family >= CHIP_R600) {
 510                                 rdev->wb.use_event = true;
 511                         }
 512                 }
 513         }
 514         /* always use writeback/events on NI, APUs */
 515         if (rdev->family >= CHIP_PALM) {
 516                 rdev->wb.enabled = true;
 517                 rdev->wb.use_event = true;
 518         }
 519 
 520         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 521 
 522         return 0;
 523 }
 524 
 525 /**
 526  * radeon_vram_location - try to find VRAM location
 527  * @rdev: radeon device structure holding all necessary informations
 528  * @mc: memory controller structure holding memory informations
 529  * @base: base address at which to put VRAM
 530  *
 531  * Function will place try to place VRAM at base address provided
 532  * as parameter (which is so far either PCI aperture address or
 533  * for IGP TOM base address).
 534  *
 535  * If there is not enough space to fit the unvisible VRAM in the 32bits
 536  * address space then we limit the VRAM size to the aperture.
 537  *
 538  * If we are using AGP and if the AGP aperture doesn't allow us to have
 539  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 540  * size and print a warning.
 541  *
 542  * This function will never fails, worst case are limiting VRAM.
 543  *
 544  * Note: GTT start, end, size should be initialized before calling this
 545  * function on AGP platform.
 546  *
 547  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 548  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 549  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 550  * not IGP.
 551  *
 552  * Note: we use mc_vram_size as on some board we need to program the mc to
 553  * cover the whole aperture even if VRAM size is inferior to aperture size
 554  * Novell bug 204882 + along with lots of ubuntu ones
 555  *
 556  * Note: when limiting vram it's safe to overwritte real_vram_size because
 557  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 558  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 559  * ones)
 560  *
 561  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 562  * explicitly check for that thought.
 563  *
 564  * FIXME: when reducing VRAM size align new size on power of 2.
 565  */
 566 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 567 {
 568         uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 569 
 570         mc->vram_start = base;
 571         if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
 572                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 573                 mc->real_vram_size = mc->aper_size;
 574                 mc->mc_vram_size = mc->aper_size;
 575         }
 576         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 577         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 578                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 579                 mc->real_vram_size = mc->aper_size;
 580                 mc->mc_vram_size = mc->aper_size;
 581         }
 582         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 583         if (limit && limit < mc->real_vram_size)
 584                 mc->real_vram_size = limit;
 585         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 586                         mc->mc_vram_size >> 20, mc->vram_start,
 587                         mc->vram_end, mc->real_vram_size >> 20);
 588 }
 589 
 590 /**
 591  * radeon_gtt_location - try to find GTT location
 592  * @rdev: radeon device structure holding all necessary informations
 593  * @mc: memory controller structure holding memory informations
 594  *
 595  * Function will place try to place GTT before or after VRAM.
 596  *
 597  * If GTT size is bigger than space left then we ajust GTT size.
 598  * Thus function will never fails.
 599  *
 600  * FIXME: when reducing GTT size align new size on power of 2.
 601  */
 602 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 603 {
 604         u64 size_af, size_bf;
 605 
 606         size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 607         size_bf = mc->vram_start & ~mc->gtt_base_align;
 608         if (size_bf > size_af) {
 609                 if (mc->gtt_size > size_bf) {
 610                         dev_warn(rdev->dev, "limiting GTT\n");
 611                         mc->gtt_size = size_bf;
 612                 }
 613                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 614         } else {
 615                 if (mc->gtt_size > size_af) {
 616                         dev_warn(rdev->dev, "limiting GTT\n");
 617                         mc->gtt_size = size_af;
 618                 }
 619                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 620         }
 621         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 622         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 623                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 624 }
 625 
 626 /*
 627  * GPU helpers function.
 628  */
 629 
 630 /**
 631  * radeon_device_is_virtual - check if we are running is a virtual environment
 632  *
 633  * Check if the asic has been passed through to a VM (all asics).
 634  * Used at driver startup.
 635  * Returns true if virtual or false if not.
 636  */
 637 bool radeon_device_is_virtual(void)
 638 {
 639 #ifdef CONFIG_X86
 640         return boot_cpu_has(X86_FEATURE_HYPERVISOR);
 641 #else
 642         return false;
 643 #endif
 644 }
 645 
 646 /**
 647  * radeon_card_posted - check if the hw has already been initialized
 648  *
 649  * @rdev: radeon_device pointer
 650  *
 651  * Check if the asic has been initialized (all asics).
 652  * Used at driver startup.
 653  * Returns true if initialized or false if not.
 654  */
 655 bool radeon_card_posted(struct radeon_device *rdev)
 656 {
 657         uint32_t reg;
 658 
 659         /* for pass through, always force asic_init for CI */
 660         if (rdev->family >= CHIP_BONAIRE &&
 661             radeon_device_is_virtual())
 662                 return false;
 663 
 664         /* required for EFI mode on macbook2,1 which uses an r5xx asic */
 665         if (efi_enabled(EFI_BOOT) &&
 666             (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 667             (rdev->family < CHIP_R600))
 668                 return false;
 669 
 670         if (ASIC_IS_NODCE(rdev))
 671                 goto check_memsize;
 672 
 673         /* first check CRTCs */
 674         if (ASIC_IS_DCE4(rdev)) {
 675                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 676                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 677                         if (rdev->num_crtc >= 4) {
 678                                 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 679                                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 680                         }
 681                         if (rdev->num_crtc >= 6) {
 682                                 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 683                                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 684                         }
 685                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 686                         return true;
 687         } else if (ASIC_IS_AVIVO(rdev)) {
 688                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 689                       RREG32(AVIVO_D2CRTC_CONTROL);
 690                 if (reg & AVIVO_CRTC_EN) {
 691                         return true;
 692                 }
 693         } else {
 694                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 695                       RREG32(RADEON_CRTC2_GEN_CNTL);
 696                 if (reg & RADEON_CRTC_EN) {
 697                         return true;
 698                 }
 699         }
 700 
 701 check_memsize:
 702         /* then check MEM_SIZE, in case the crtcs are off */
 703         if (rdev->family >= CHIP_R600)
 704                 reg = RREG32(R600_CONFIG_MEMSIZE);
 705         else
 706                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 707 
 708         if (reg)
 709                 return true;
 710 
 711         return false;
 712 
 713 }
 714 
 715 /**
 716  * radeon_update_bandwidth_info - update display bandwidth params
 717  *
 718  * @rdev: radeon_device pointer
 719  *
 720  * Used when sclk/mclk are switched or display modes are set.
 721  * params are used to calculate display watermarks (all asics)
 722  */
 723 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 724 {
 725         fixed20_12 a;
 726         u32 sclk = rdev->pm.current_sclk;
 727         u32 mclk = rdev->pm.current_mclk;
 728 
 729         /* sclk/mclk in Mhz */
 730         a.full = dfixed_const(100);
 731         rdev->pm.sclk.full = dfixed_const(sclk);
 732         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 733         rdev->pm.mclk.full = dfixed_const(mclk);
 734         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 735 
 736         if (rdev->flags & RADEON_IS_IGP) {
 737                 a.full = dfixed_const(16);
 738                 /* core_bandwidth = sclk(Mhz) * 16 */
 739                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 740         }
 741 }
 742 
 743 /**
 744  * radeon_boot_test_post_card - check and possibly initialize the hw
 745  *
 746  * @rdev: radeon_device pointer
 747  *
 748  * Check if the asic is initialized and if not, attempt to initialize
 749  * it (all asics).
 750  * Returns true if initialized or false if not.
 751  */
 752 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 753 {
 754         if (radeon_card_posted(rdev))
 755                 return true;
 756 
 757         if (rdev->bios) {
 758                 DRM_INFO("GPU not posted. posting now...\n");
 759                 if (rdev->is_atom_bios)
 760                         atom_asic_init(rdev->mode_info.atom_context);
 761                 else
 762                         radeon_combios_asic_init(rdev->ddev);
 763                 return true;
 764         } else {
 765                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 766                 return false;
 767         }
 768 }
 769 
 770 /**
 771  * radeon_dummy_page_init - init dummy page used by the driver
 772  *
 773  * @rdev: radeon_device pointer
 774  *
 775  * Allocate the dummy page used by the driver (all asics).
 776  * This dummy page is used by the driver as a filler for gart entries
 777  * when pages are taken out of the GART
 778  * Returns 0 on sucess, -ENOMEM on failure.
 779  */
 780 int radeon_dummy_page_init(struct radeon_device *rdev)
 781 {
 782         if (rdev->dummy_page.page)
 783                 return 0;
 784         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 785         if (rdev->dummy_page.page == NULL)
 786                 return -ENOMEM;
 787         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 788                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 789         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 790                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 791                 __free_page(rdev->dummy_page.page);
 792                 rdev->dummy_page.page = NULL;
 793                 return -ENOMEM;
 794         }
 795         rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
 796                                                             RADEON_GART_PAGE_DUMMY);
 797         return 0;
 798 }
 799 
 800 /**
 801  * radeon_dummy_page_fini - free dummy page used by the driver
 802  *
 803  * @rdev: radeon_device pointer
 804  *
 805  * Frees the dummy page used by the driver (all asics).
 806  */
 807 void radeon_dummy_page_fini(struct radeon_device *rdev)
 808 {
 809         if (rdev->dummy_page.page == NULL)
 810                 return;
 811         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 812                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 813         __free_page(rdev->dummy_page.page);
 814         rdev->dummy_page.page = NULL;
 815 }
 816 
 817 
 818 /* ATOM accessor methods */
 819 /*
 820  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 821  * driver registers callbacks to access registers and the interpreter
 822  * in the driver parses the tables and executes then to program specific
 823  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 824  * atombios.h, and atom.c
 825  */
 826 
 827 /**
 828  * cail_pll_read - read PLL register
 829  *
 830  * @info: atom card_info pointer
 831  * @reg: PLL register offset
 832  *
 833  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 834  * Returns the value of the PLL register.
 835  */
 836 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 837 {
 838         struct radeon_device *rdev = info->dev->dev_private;
 839         uint32_t r;
 840 
 841         r = rdev->pll_rreg(rdev, reg);
 842         return r;
 843 }
 844 
 845 /**
 846  * cail_pll_write - write PLL register
 847  *
 848  * @info: atom card_info pointer
 849  * @reg: PLL register offset
 850  * @val: value to write to the pll register
 851  *
 852  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 853  */
 854 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 855 {
 856         struct radeon_device *rdev = info->dev->dev_private;
 857 
 858         rdev->pll_wreg(rdev, reg, val);
 859 }
 860 
 861 /**
 862  * cail_mc_read - read MC (Memory Controller) register
 863  *
 864  * @info: atom card_info pointer
 865  * @reg: MC register offset
 866  *
 867  * Provides an MC register accessor for the atom interpreter (r4xx+).
 868  * Returns the value of the MC register.
 869  */
 870 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 871 {
 872         struct radeon_device *rdev = info->dev->dev_private;
 873         uint32_t r;
 874 
 875         r = rdev->mc_rreg(rdev, reg);
 876         return r;
 877 }
 878 
 879 /**
 880  * cail_mc_write - write MC (Memory Controller) register
 881  *
 882  * @info: atom card_info pointer
 883  * @reg: MC register offset
 884  * @val: value to write to the pll register
 885  *
 886  * Provides a MC register accessor for the atom interpreter (r4xx+).
 887  */
 888 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 889 {
 890         struct radeon_device *rdev = info->dev->dev_private;
 891 
 892         rdev->mc_wreg(rdev, reg, val);
 893 }
 894 
 895 /**
 896  * cail_reg_write - write MMIO register
 897  *
 898  * @info: atom card_info pointer
 899  * @reg: MMIO register offset
 900  * @val: value to write to the pll register
 901  *
 902  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 903  */
 904 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 905 {
 906         struct radeon_device *rdev = info->dev->dev_private;
 907 
 908         WREG32(reg*4, val);
 909 }
 910 
 911 /**
 912  * cail_reg_read - read MMIO register
 913  *
 914  * @info: atom card_info pointer
 915  * @reg: MMIO register offset
 916  *
 917  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 918  * Returns the value of the MMIO register.
 919  */
 920 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 921 {
 922         struct radeon_device *rdev = info->dev->dev_private;
 923         uint32_t r;
 924 
 925         r = RREG32(reg*4);
 926         return r;
 927 }
 928 
 929 /**
 930  * cail_ioreg_write - write IO register
 931  *
 932  * @info: atom card_info pointer
 933  * @reg: IO register offset
 934  * @val: value to write to the pll register
 935  *
 936  * Provides a IO register accessor for the atom interpreter (r4xx+).
 937  */
 938 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 939 {
 940         struct radeon_device *rdev = info->dev->dev_private;
 941 
 942         WREG32_IO(reg*4, val);
 943 }
 944 
 945 /**
 946  * cail_ioreg_read - read IO register
 947  *
 948  * @info: atom card_info pointer
 949  * @reg: IO register offset
 950  *
 951  * Provides an IO register accessor for the atom interpreter (r4xx+).
 952  * Returns the value of the IO register.
 953  */
 954 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 955 {
 956         struct radeon_device *rdev = info->dev->dev_private;
 957         uint32_t r;
 958 
 959         r = RREG32_IO(reg*4);
 960         return r;
 961 }
 962 
 963 /**
 964  * radeon_atombios_init - init the driver info and callbacks for atombios
 965  *
 966  * @rdev: radeon_device pointer
 967  *
 968  * Initializes the driver info and register access callbacks for the
 969  * ATOM interpreter (r4xx+).
 970  * Returns 0 on sucess, -ENOMEM on failure.
 971  * Called at driver startup.
 972  */
 973 int radeon_atombios_init(struct radeon_device *rdev)
 974 {
 975         struct card_info *atom_card_info =
 976             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 977 
 978         if (!atom_card_info)
 979                 return -ENOMEM;
 980 
 981         rdev->mode_info.atom_card_info = atom_card_info;
 982         atom_card_info->dev = rdev->ddev;
 983         atom_card_info->reg_read = cail_reg_read;
 984         atom_card_info->reg_write = cail_reg_write;
 985         /* needed for iio ops */
 986         if (rdev->rio_mem) {
 987                 atom_card_info->ioreg_read = cail_ioreg_read;
 988                 atom_card_info->ioreg_write = cail_ioreg_write;
 989         } else {
 990                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 991                 atom_card_info->ioreg_read = cail_reg_read;
 992                 atom_card_info->ioreg_write = cail_reg_write;
 993         }
 994         atom_card_info->mc_read = cail_mc_read;
 995         atom_card_info->mc_write = cail_mc_write;
 996         atom_card_info->pll_read = cail_pll_read;
 997         atom_card_info->pll_write = cail_pll_write;
 998 
 999         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1000         if (!rdev->mode_info.atom_context) {
1001                 radeon_atombios_fini(rdev);
1002                 return -ENOMEM;
1003         }
1004 
1005         mutex_init(&rdev->mode_info.atom_context->mutex);
1006         mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1007         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1008         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1009         return 0;
1010 }
1011 
1012 /**
1013  * radeon_atombios_fini - free the driver info and callbacks for atombios
1014  *
1015  * @rdev: radeon_device pointer
1016  *
1017  * Frees the driver info and register access callbacks for the ATOM
1018  * interpreter (r4xx+).
1019  * Called at driver shutdown.
1020  */
1021 void radeon_atombios_fini(struct radeon_device *rdev)
1022 {
1023         if (rdev->mode_info.atom_context) {
1024                 kfree(rdev->mode_info.atom_context->scratch);
1025         }
1026         kfree(rdev->mode_info.atom_context);
1027         rdev->mode_info.atom_context = NULL;
1028         kfree(rdev->mode_info.atom_card_info);
1029         rdev->mode_info.atom_card_info = NULL;
1030 }
1031 
1032 /* COMBIOS */
1033 /*
1034  * COMBIOS is the bios format prior to ATOM. It provides
1035  * command tables similar to ATOM, but doesn't have a unified
1036  * parser.  See radeon_combios.c
1037  */
1038 
1039 /**
1040  * radeon_combios_init - init the driver info for combios
1041  *
1042  * @rdev: radeon_device pointer
1043  *
1044  * Initializes the driver info for combios (r1xx-r3xx).
1045  * Returns 0 on sucess.
1046  * Called at driver startup.
1047  */
1048 int radeon_combios_init(struct radeon_device *rdev)
1049 {
1050         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1051         return 0;
1052 }
1053 
1054 /**
1055  * radeon_combios_fini - free the driver info for combios
1056  *
1057  * @rdev: radeon_device pointer
1058  *
1059  * Frees the driver info for combios (r1xx-r3xx).
1060  * Called at driver shutdown.
1061  */
1062 void radeon_combios_fini(struct radeon_device *rdev)
1063 {
1064 }
1065 
1066 /* if we get transitioned to only one device, take VGA back */
1067 /**
1068  * radeon_vga_set_decode - enable/disable vga decode
1069  *
1070  * @cookie: radeon_device pointer
1071  * @state: enable/disable vga decode
1072  *
1073  * Enable/disable vga decode (all asics).
1074  * Returns VGA resource flags.
1075  */
1076 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1077 {
1078         struct radeon_device *rdev = cookie;
1079         radeon_vga_set_state(rdev, state);
1080         if (state)
1081                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1082                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1083         else
1084                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1085 }
1086 
1087 /**
1088  * radeon_check_pot_argument - check that argument is a power of two
1089  *
1090  * @arg: value to check
1091  *
1092  * Validates that a certain argument is a power of two (all asics).
1093  * Returns true if argument is valid.
1094  */
1095 static bool radeon_check_pot_argument(int arg)
1096 {
1097         return (arg & (arg - 1)) == 0;
1098 }
1099 
1100 /**
1101  * Determine a sensible default GART size according to ASIC family.
1102  *
1103  * @family ASIC family name
1104  */
1105 static int radeon_gart_size_auto(enum radeon_family family)
1106 {
1107         /* default to a larger gart size on newer asics */
1108         if (family >= CHIP_TAHITI)
1109                 return 2048;
1110         else if (family >= CHIP_RV770)
1111                 return 1024;
1112         else
1113                 return 512;
1114 }
1115 
1116 /**
1117  * radeon_check_arguments - validate module params
1118  *
1119  * @rdev: radeon_device pointer
1120  *
1121  * Validates certain module parameters and updates
1122  * the associated values used by the driver (all asics).
1123  */
1124 static void radeon_check_arguments(struct radeon_device *rdev)
1125 {
1126         /* vramlimit must be a power of two */
1127         if (!radeon_check_pot_argument(radeon_vram_limit)) {
1128                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1129                                 radeon_vram_limit);
1130                 radeon_vram_limit = 0;
1131         }
1132 
1133         if (radeon_gart_size == -1) {
1134                 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1135         }
1136         /* gtt size must be power of two and greater or equal to 32M */
1137         if (radeon_gart_size < 32) {
1138                 dev_warn(rdev->dev, "gart size (%d) too small\n",
1139                                 radeon_gart_size);
1140                 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1141         } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1142                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1143                                 radeon_gart_size);
1144                 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1145         }
1146         rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1147 
1148         /* AGP mode can only be -1, 1, 2, 4, 8 */
1149         switch (radeon_agpmode) {
1150         case -1:
1151         case 0:
1152         case 1:
1153         case 2:
1154         case 4:
1155         case 8:
1156                 break;
1157         default:
1158                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1159                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1160                 radeon_agpmode = 0;
1161                 break;
1162         }
1163 
1164         if (!radeon_check_pot_argument(radeon_vm_size)) {
1165                 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1166                          radeon_vm_size);
1167                 radeon_vm_size = 4;
1168         }
1169 
1170         if (radeon_vm_size < 1) {
1171                 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1172                          radeon_vm_size);
1173                 radeon_vm_size = 4;
1174         }
1175 
1176         /*
1177          * Max GPUVM size for Cayman, SI and CI are 40 bits.
1178          */
1179         if (radeon_vm_size > 1024) {
1180                 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1181                          radeon_vm_size);
1182                 radeon_vm_size = 4;
1183         }
1184 
1185         /* defines number of bits in page table versus page directory,
1186          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1187          * page table and the remaining bits are in the page directory */
1188         if (radeon_vm_block_size == -1) {
1189 
1190                 /* Total bits covered by PD + PTs */
1191                 unsigned bits = ilog2(radeon_vm_size) + 18;
1192 
1193                 /* Make sure the PD is 4K in size up to 8GB address space.
1194                    Above that split equal between PD and PTs */
1195                 if (radeon_vm_size <= 8)
1196                         radeon_vm_block_size = bits - 9;
1197                 else
1198                         radeon_vm_block_size = (bits + 3) / 2;
1199 
1200         } else if (radeon_vm_block_size < 9) {
1201                 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1202                          radeon_vm_block_size);
1203                 radeon_vm_block_size = 9;
1204         }
1205 
1206         if (radeon_vm_block_size > 24 ||
1207             (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1208                 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1209                          radeon_vm_block_size);
1210                 radeon_vm_block_size = 9;
1211         }
1212 }
1213 
1214 /**
1215  * radeon_switcheroo_set_state - set switcheroo state
1216  *
1217  * @pdev: pci dev pointer
1218  * @state: vga_switcheroo state
1219  *
1220  * Callback for the switcheroo driver.  Suspends or resumes the
1221  * the asics before or after it is powered up using ACPI methods.
1222  */
1223 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1224 {
1225         struct drm_device *dev = pci_get_drvdata(pdev);
1226 
1227         if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1228                 return;
1229 
1230         if (state == VGA_SWITCHEROO_ON) {
1231                 pr_info("radeon: switched on\n");
1232                 /* don't suspend or resume card normally */
1233                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1234 
1235                 radeon_resume_kms(dev, true, true);
1236 
1237                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1238                 drm_kms_helper_poll_enable(dev);
1239         } else {
1240                 pr_info("radeon: switched off\n");
1241                 drm_kms_helper_poll_disable(dev);
1242                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1243                 radeon_suspend_kms(dev, true, true, false);
1244                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1245         }
1246 }
1247 
1248 /**
1249  * radeon_switcheroo_can_switch - see if switcheroo state can change
1250  *
1251  * @pdev: pci dev pointer
1252  *
1253  * Callback for the switcheroo driver.  Check of the switcheroo
1254  * state can be changed.
1255  * Returns true if the state can be changed, false if not.
1256  */
1257 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1258 {
1259         struct drm_device *dev = pci_get_drvdata(pdev);
1260 
1261         /*
1262          * FIXME: open_count is protected by drm_global_mutex but that would lead to
1263          * locking inversion with the driver load path. And the access here is
1264          * completely racy anyway. So don't bother with locking for now.
1265          */
1266         return dev->open_count == 0;
1267 }
1268 
1269 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1270         .set_gpu_state = radeon_switcheroo_set_state,
1271         .reprobe = NULL,
1272         .can_switch = radeon_switcheroo_can_switch,
1273 };
1274 
1275 /**
1276  * radeon_device_init - initialize the driver
1277  *
1278  * @rdev: radeon_device pointer
1279  * @pdev: drm dev pointer
1280  * @pdev: pci dev pointer
1281  * @flags: driver flags
1282  *
1283  * Initializes the driver info and hw (all asics).
1284  * Returns 0 for success or an error on failure.
1285  * Called at driver startup.
1286  */
1287 int radeon_device_init(struct radeon_device *rdev,
1288                        struct drm_device *ddev,
1289                        struct pci_dev *pdev,
1290                        uint32_t flags)
1291 {
1292         int r, i;
1293         int dma_bits;
1294         bool runtime = false;
1295 
1296         rdev->shutdown = false;
1297         rdev->dev = &pdev->dev;
1298         rdev->ddev = ddev;
1299         rdev->pdev = pdev;
1300         rdev->flags = flags;
1301         rdev->family = flags & RADEON_FAMILY_MASK;
1302         rdev->is_atom_bios = false;
1303         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1304         rdev->mc.gtt_size = 512 * 1024 * 1024;
1305         rdev->accel_working = false;
1306         /* set up ring ids */
1307         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1308                 rdev->ring[i].idx = i;
1309         }
1310         rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1311 
1312         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1313                  radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1314                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1315 
1316         /* mutex initialization are all done here so we
1317          * can recall function without having locking issues */
1318         mutex_init(&rdev->ring_lock);
1319         mutex_init(&rdev->dc_hw_i2c_mutex);
1320         atomic_set(&rdev->ih.lock, 0);
1321         mutex_init(&rdev->gem.mutex);
1322         mutex_init(&rdev->pm.mutex);
1323         mutex_init(&rdev->gpu_clock_mutex);
1324         mutex_init(&rdev->srbm_mutex);
1325         init_rwsem(&rdev->pm.mclk_lock);
1326         init_rwsem(&rdev->exclusive_lock);
1327         init_waitqueue_head(&rdev->irq.vblank_queue);
1328         r = radeon_gem_init(rdev);
1329         if (r)
1330                 return r;
1331 
1332         radeon_check_arguments(rdev);
1333         /* Adjust VM size here.
1334          * Max GPUVM size for cayman+ is 40 bits.
1335          */
1336         rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1337 
1338         /* Set asic functions */
1339         r = radeon_asic_init(rdev);
1340         if (r)
1341                 return r;
1342 
1343         /* all of the newer IGP chips have an internal gart
1344          * However some rs4xx report as AGP, so remove that here.
1345          */
1346         if ((rdev->family >= CHIP_RS400) &&
1347             (rdev->flags & RADEON_IS_IGP)) {
1348                 rdev->flags &= ~RADEON_IS_AGP;
1349         }
1350 
1351         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1352                 radeon_agp_disable(rdev);
1353         }
1354 
1355         /* Set the internal MC address mask
1356          * This is the max address of the GPU's
1357          * internal address space.
1358          */
1359         if (rdev->family >= CHIP_CAYMAN)
1360                 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1361         else if (rdev->family >= CHIP_CEDAR)
1362                 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1363         else
1364                 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1365 
1366         /* set DMA mask.
1367          * PCIE - can handle 40-bits.
1368          * IGP - can handle 40-bits
1369          * AGP - generally dma32 is safest
1370          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1371          */
1372         dma_bits = 40;
1373         if (rdev->flags & RADEON_IS_AGP)
1374                 dma_bits = 32;
1375         if ((rdev->flags & RADEON_IS_PCI) &&
1376             (rdev->family <= CHIP_RS740))
1377                 dma_bits = 32;
1378 #ifdef CONFIG_PPC64
1379         if (rdev->family == CHIP_CEDAR)
1380                 dma_bits = 32;
1381 #endif
1382 
1383         r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
1384         if (r) {
1385                 pr_warn("radeon: No suitable DMA available\n");
1386                 return r;
1387         }
1388         rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
1389 
1390         /* Registers mapping */
1391         /* TODO: block userspace mapping of io register */
1392         spin_lock_init(&rdev->mmio_idx_lock);
1393         spin_lock_init(&rdev->smc_idx_lock);
1394         spin_lock_init(&rdev->pll_idx_lock);
1395         spin_lock_init(&rdev->mc_idx_lock);
1396         spin_lock_init(&rdev->pcie_idx_lock);
1397         spin_lock_init(&rdev->pciep_idx_lock);
1398         spin_lock_init(&rdev->pif_idx_lock);
1399         spin_lock_init(&rdev->cg_idx_lock);
1400         spin_lock_init(&rdev->uvd_idx_lock);
1401         spin_lock_init(&rdev->rcu_idx_lock);
1402         spin_lock_init(&rdev->didt_idx_lock);
1403         spin_lock_init(&rdev->end_idx_lock);
1404         if (rdev->family >= CHIP_BONAIRE) {
1405                 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1406                 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1407         } else {
1408                 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1409                 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1410         }
1411         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1412         if (rdev->rmmio == NULL)
1413                 return -ENOMEM;
1414 
1415         /* doorbell bar mapping */
1416         if (rdev->family >= CHIP_BONAIRE)
1417                 radeon_doorbell_init(rdev);
1418 
1419         /* io port mapping */
1420         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1421                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1422                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1423                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1424                         break;
1425                 }
1426         }
1427         if (rdev->rio_mem == NULL)
1428                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1429 
1430         if (rdev->flags & RADEON_IS_PX)
1431                 radeon_device_handle_px_quirks(rdev);
1432 
1433         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1434         /* this will fail for cards that aren't VGA class devices, just
1435          * ignore it */
1436         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1437 
1438         if (rdev->flags & RADEON_IS_PX)
1439                 runtime = true;
1440         if (!pci_is_thunderbolt_attached(rdev->pdev))
1441                 vga_switcheroo_register_client(rdev->pdev,
1442                                                &radeon_switcheroo_ops, runtime);
1443         if (runtime)
1444                 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1445 
1446         r = radeon_init(rdev);
1447         if (r)
1448                 goto failed;
1449 
1450         r = radeon_gem_debugfs_init(rdev);
1451         if (r) {
1452                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1453         }
1454 
1455         r = radeon_mst_debugfs_init(rdev);
1456         if (r) {
1457                 DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1458         }
1459 
1460         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1461                 /* Acceleration not working on AGP card try again
1462                  * with fallback to PCI or PCIE GART
1463                  */
1464                 radeon_asic_reset(rdev);
1465                 radeon_fini(rdev);
1466                 radeon_agp_disable(rdev);
1467                 r = radeon_init(rdev);
1468                 if (r)
1469                         goto failed;
1470         }
1471 
1472         r = radeon_ib_ring_tests(rdev);
1473         if (r)
1474                 DRM_ERROR("ib ring test failed (%d).\n", r);
1475 
1476         /*
1477          * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1478          * after the CP ring have chew one packet at least. Hence here we stop
1479          * and restart DPM after the radeon_ib_ring_tests().
1480          */
1481         if (rdev->pm.dpm_enabled &&
1482             (rdev->pm.pm_method == PM_METHOD_DPM) &&
1483             (rdev->family == CHIP_TURKS) &&
1484             (rdev->flags & RADEON_IS_MOBILITY)) {
1485                 mutex_lock(&rdev->pm.mutex);
1486                 radeon_dpm_disable(rdev);
1487                 radeon_dpm_enable(rdev);
1488                 mutex_unlock(&rdev->pm.mutex);
1489         }
1490 
1491         if ((radeon_testing & 1)) {
1492                 if (rdev->accel_working)
1493                         radeon_test_moves(rdev);
1494                 else
1495                         DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1496         }
1497         if ((radeon_testing & 2)) {
1498                 if (rdev->accel_working)
1499                         radeon_test_syncing(rdev);
1500                 else
1501                         DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1502         }
1503         if (radeon_benchmarking) {
1504                 if (rdev->accel_working)
1505                         radeon_benchmark(rdev, radeon_benchmarking);
1506                 else
1507                         DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1508         }
1509         return 0;
1510 
1511 failed:
1512         /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1513         if (radeon_is_px(ddev))
1514                 pm_runtime_put_noidle(ddev->dev);
1515         if (runtime)
1516                 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1517         return r;
1518 }
1519 
1520 /**
1521  * radeon_device_fini - tear down the driver
1522  *
1523  * @rdev: radeon_device pointer
1524  *
1525  * Tear down the driver info (all asics).
1526  * Called at driver shutdown.
1527  */
1528 void radeon_device_fini(struct radeon_device *rdev)
1529 {
1530         DRM_INFO("radeon: finishing device.\n");
1531         rdev->shutdown = true;
1532         /* evict vram memory */
1533         radeon_bo_evict_vram(rdev);
1534         radeon_fini(rdev);
1535         if (!pci_is_thunderbolt_attached(rdev->pdev))
1536                 vga_switcheroo_unregister_client(rdev->pdev);
1537         if (rdev->flags & RADEON_IS_PX)
1538                 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1539         vga_client_register(rdev->pdev, NULL, NULL, NULL);
1540         if (rdev->rio_mem)
1541                 pci_iounmap(rdev->pdev, rdev->rio_mem);
1542         rdev->rio_mem = NULL;
1543         iounmap(rdev->rmmio);
1544         rdev->rmmio = NULL;
1545         if (rdev->family >= CHIP_BONAIRE)
1546                 radeon_doorbell_fini(rdev);
1547 }
1548 
1549 
1550 /*
1551  * Suspend & resume.
1552  */
1553 /**
1554  * radeon_suspend_kms - initiate device suspend
1555  *
1556  * @pdev: drm dev pointer
1557  * @state: suspend state
1558  *
1559  * Puts the hw in the suspend state (all asics).
1560  * Returns 0 for success or an error on failure.
1561  * Called at driver suspend.
1562  */
1563 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1564                        bool fbcon, bool freeze)
1565 {
1566         struct radeon_device *rdev;
1567         struct drm_crtc *crtc;
1568         struct drm_connector *connector;
1569         int i, r;
1570 
1571         if (dev == NULL || dev->dev_private == NULL) {
1572                 return -ENODEV;
1573         }
1574 
1575         rdev = dev->dev_private;
1576 
1577         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1578                 return 0;
1579 
1580         drm_kms_helper_poll_disable(dev);
1581 
1582         drm_modeset_lock_all(dev);
1583         /* turn off display hw */
1584         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1585                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1586         }
1587         drm_modeset_unlock_all(dev);
1588 
1589         /* unpin the front buffers and cursors */
1590         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1591                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1592                 struct drm_framebuffer *fb = crtc->primary->fb;
1593                 struct radeon_bo *robj;
1594 
1595                 if (radeon_crtc->cursor_bo) {
1596                         struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1597                         r = radeon_bo_reserve(robj, false);
1598                         if (r == 0) {
1599                                 radeon_bo_unpin(robj);
1600                                 radeon_bo_unreserve(robj);
1601                         }
1602                 }
1603 
1604                 if (fb == NULL || fb->obj[0] == NULL) {
1605                         continue;
1606                 }
1607                 robj = gem_to_radeon_bo(fb->obj[0]);
1608                 /* don't unpin kernel fb objects */
1609                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1610                         r = radeon_bo_reserve(robj, false);
1611                         if (r == 0) {
1612                                 radeon_bo_unpin(robj);
1613                                 radeon_bo_unreserve(robj);
1614                         }
1615                 }
1616         }
1617         /* evict vram memory */
1618         radeon_bo_evict_vram(rdev);
1619 
1620         /* wait for gpu to finish processing current batch */
1621         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1622                 r = radeon_fence_wait_empty(rdev, i);
1623                 if (r) {
1624                         /* delay GPU reset to resume */
1625                         radeon_fence_driver_force_completion(rdev, i);
1626                 }
1627         }
1628 
1629         radeon_save_bios_scratch_regs(rdev);
1630 
1631         radeon_suspend(rdev);
1632         radeon_hpd_fini(rdev);
1633         /* evict remaining vram memory
1634          * This second call to evict vram is to evict the gart page table
1635          * using the CPU.
1636          */
1637         radeon_bo_evict_vram(rdev);
1638 
1639         radeon_agp_suspend(rdev);
1640 
1641         pci_save_state(dev->pdev);
1642         if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1643                 rdev->asic->asic_reset(rdev, true);
1644                 pci_restore_state(dev->pdev);
1645         } else if (suspend) {
1646                 /* Shut down the device */
1647                 pci_disable_device(dev->pdev);
1648                 pci_set_power_state(dev->pdev, PCI_D3hot);
1649         }
1650 
1651         if (fbcon) {
1652                 console_lock();
1653                 radeon_fbdev_set_suspend(rdev, 1);
1654                 console_unlock();
1655         }
1656         return 0;
1657 }
1658 
1659 /**
1660  * radeon_resume_kms - initiate device resume
1661  *
1662  * @pdev: drm dev pointer
1663  *
1664  * Bring the hw back to operating state (all asics).
1665  * Returns 0 for success or an error on failure.
1666  * Called at driver resume.
1667  */
1668 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1669 {
1670         struct drm_connector *connector;
1671         struct radeon_device *rdev = dev->dev_private;
1672         struct drm_crtc *crtc;
1673         int r;
1674 
1675         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1676                 return 0;
1677 
1678         if (fbcon) {
1679                 console_lock();
1680         }
1681         if (resume) {
1682                 pci_set_power_state(dev->pdev, PCI_D0);
1683                 pci_restore_state(dev->pdev);
1684                 if (pci_enable_device(dev->pdev)) {
1685                         if (fbcon)
1686                                 console_unlock();
1687                         return -1;
1688                 }
1689         }
1690         /* resume AGP if in use */
1691         radeon_agp_resume(rdev);
1692         radeon_resume(rdev);
1693 
1694         r = radeon_ib_ring_tests(rdev);
1695         if (r)
1696                 DRM_ERROR("ib ring test failed (%d).\n", r);
1697 
1698         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1699                 /* do dpm late init */
1700                 r = radeon_pm_late_init(rdev);
1701                 if (r) {
1702                         rdev->pm.dpm_enabled = false;
1703                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1704                 }
1705         } else {
1706                 /* resume old pm late */
1707                 radeon_pm_resume(rdev);
1708         }
1709 
1710         radeon_restore_bios_scratch_regs(rdev);
1711 
1712         /* pin cursors */
1713         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1714                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1715 
1716                 if (radeon_crtc->cursor_bo) {
1717                         struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1718                         r = radeon_bo_reserve(robj, false);
1719                         if (r == 0) {
1720                                 /* Only 27 bit offset for legacy cursor */
1721                                 r = radeon_bo_pin_restricted(robj,
1722                                                              RADEON_GEM_DOMAIN_VRAM,
1723                                                              ASIC_IS_AVIVO(rdev) ?
1724                                                              0 : 1 << 27,
1725                                                              &radeon_crtc->cursor_addr);
1726                                 if (r != 0)
1727                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1728                                 radeon_bo_unreserve(robj);
1729                         }
1730                 }
1731         }
1732 
1733         /* init dig PHYs, disp eng pll */
1734         if (rdev->is_atom_bios) {
1735                 radeon_atom_encoder_init(rdev);
1736                 radeon_atom_disp_eng_pll_init(rdev);
1737                 /* turn on the BL */
1738                 if (rdev->mode_info.bl_encoder) {
1739                         u8 bl_level = radeon_get_backlight_level(rdev,
1740                                                                  rdev->mode_info.bl_encoder);
1741                         radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1742                                                    bl_level);
1743                 }
1744         }
1745         /* reset hpd state */
1746         radeon_hpd_init(rdev);
1747         /* blat the mode back in */
1748         if (fbcon) {
1749                 drm_helper_resume_force_mode(dev);
1750                 /* turn on display hw */
1751                 drm_modeset_lock_all(dev);
1752                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1753                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1754                 }
1755                 drm_modeset_unlock_all(dev);
1756         }
1757 
1758         drm_kms_helper_poll_enable(dev);
1759 
1760         /* set the power state here in case we are a PX system or headless */
1761         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1762                 radeon_pm_compute_clocks(rdev);
1763 
1764         if (fbcon) {
1765                 radeon_fbdev_set_suspend(rdev, 0);
1766                 console_unlock();
1767         }
1768 
1769         return 0;
1770 }
1771 
1772 /**
1773  * radeon_gpu_reset - reset the asic
1774  *
1775  * @rdev: radeon device pointer
1776  *
1777  * Attempt the reset the GPU if it has hung (all asics).
1778  * Returns 0 for success or an error on failure.
1779  */
1780 int radeon_gpu_reset(struct radeon_device *rdev)
1781 {
1782         unsigned ring_sizes[RADEON_NUM_RINGS];
1783         uint32_t *ring_data[RADEON_NUM_RINGS];
1784 
1785         bool saved = false;
1786 
1787         int i, r;
1788         int resched;
1789 
1790         down_write(&rdev->exclusive_lock);
1791 
1792         if (!rdev->needs_reset) {
1793                 up_write(&rdev->exclusive_lock);
1794                 return 0;
1795         }
1796 
1797         atomic_inc(&rdev->gpu_reset_counter);
1798 
1799         radeon_save_bios_scratch_regs(rdev);
1800         /* block TTM */
1801         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1802         radeon_suspend(rdev);
1803         radeon_hpd_fini(rdev);
1804 
1805         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1806                 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1807                                                    &ring_data[i]);
1808                 if (ring_sizes[i]) {
1809                         saved = true;
1810                         dev_info(rdev->dev, "Saved %d dwords of commands "
1811                                  "on ring %d.\n", ring_sizes[i], i);
1812                 }
1813         }
1814 
1815         r = radeon_asic_reset(rdev);
1816         if (!r) {
1817                 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1818                 radeon_resume(rdev);
1819         }
1820 
1821         radeon_restore_bios_scratch_regs(rdev);
1822 
1823         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1824                 if (!r && ring_data[i]) {
1825                         radeon_ring_restore(rdev, &rdev->ring[i],
1826                                             ring_sizes[i], ring_data[i]);
1827                 } else {
1828                         radeon_fence_driver_force_completion(rdev, i);
1829                         kfree(ring_data[i]);
1830                 }
1831         }
1832 
1833         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1834                 /* do dpm late init */
1835                 r = radeon_pm_late_init(rdev);
1836                 if (r) {
1837                         rdev->pm.dpm_enabled = false;
1838                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1839                 }
1840         } else {
1841                 /* resume old pm late */
1842                 radeon_pm_resume(rdev);
1843         }
1844 
1845         /* init dig PHYs, disp eng pll */
1846         if (rdev->is_atom_bios) {
1847                 radeon_atom_encoder_init(rdev);
1848                 radeon_atom_disp_eng_pll_init(rdev);
1849                 /* turn on the BL */
1850                 if (rdev->mode_info.bl_encoder) {
1851                         u8 bl_level = radeon_get_backlight_level(rdev,
1852                                                                  rdev->mode_info.bl_encoder);
1853                         radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1854                                                    bl_level);
1855                 }
1856         }
1857         /* reset hpd state */
1858         radeon_hpd_init(rdev);
1859 
1860         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1861 
1862         rdev->in_reset = true;
1863         rdev->needs_reset = false;
1864 
1865         downgrade_write(&rdev->exclusive_lock);
1866 
1867         drm_helper_resume_force_mode(rdev->ddev);
1868 
1869         /* set the power state here in case we are a PX system or headless */
1870         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1871                 radeon_pm_compute_clocks(rdev);
1872 
1873         if (!r) {
1874                 r = radeon_ib_ring_tests(rdev);
1875                 if (r && saved)
1876                         r = -EAGAIN;
1877         } else {
1878                 /* bad news, how to tell it to userspace ? */
1879                 dev_info(rdev->dev, "GPU reset failed\n");
1880         }
1881 
1882         rdev->needs_reset = r == -EAGAIN;
1883         rdev->in_reset = false;
1884 
1885         up_read(&rdev->exclusive_lock);
1886         return r;
1887 }
1888 
1889 
1890 /*
1891  * Debugfs
1892  */
1893 int radeon_debugfs_add_files(struct radeon_device *rdev,
1894                              struct drm_info_list *files,
1895                              unsigned nfiles)
1896 {
1897         unsigned i;
1898 
1899         for (i = 0; i < rdev->debugfs_count; i++) {
1900                 if (rdev->debugfs[i].files == files) {
1901                         /* Already registered */
1902                         return 0;
1903                 }
1904         }
1905 
1906         i = rdev->debugfs_count + 1;
1907         if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1908                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1909                 DRM_ERROR("Report so we increase "
1910                           "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1911                 return -EINVAL;
1912         }
1913         rdev->debugfs[rdev->debugfs_count].files = files;
1914         rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1915         rdev->debugfs_count = i;
1916 #if defined(CONFIG_DEBUG_FS)
1917         drm_debugfs_create_files(files, nfiles,
1918                                  rdev->ddev->primary->debugfs_root,
1919                                  rdev->ddev->primary);
1920 #endif
1921         return 0;
1922 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/radeon/radeon_device.c

DEFINITIONS
