root/drivers/gpu/drm/radeon/rv740d.h

INCLUDED FROM

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef RV740_H
  24 #define RV740_H
  25 
  26 #define CG_SPLL_FUNC_CNTL                               0x600
  27 #define         SPLL_RESET                              (1 << 0)
  28 #define         SPLL_SLEEP                              (1 << 1)
  29 #define         SPLL_BYPASS_EN                          (1 << 3)
  30 #define         SPLL_REF_DIV(x)                         ((x) << 4)
  31 #define         SPLL_REF_DIV_MASK                       (0x3f << 4)
  32 #define         SPLL_PDIV_A(x)                          ((x) << 20)
  33 #define         SPLL_PDIV_A_MASK                        (0x7f << 20)
  34 #define CG_SPLL_FUNC_CNTL_2                             0x604
  35 #define         SCLK_MUX_SEL(x)                         ((x) << 0)
  36 #define         SCLK_MUX_SEL_MASK                       (0x1ff << 0)
  37 #define CG_SPLL_FUNC_CNTL_3                             0x608
  38 #define         SPLL_FB_DIV(x)                          ((x) << 0)
  39 #define         SPLL_FB_DIV_MASK                        (0x3ffffff << 0)
  40 #define         SPLL_DITHEN                             (1 << 28)
  41 
  42 #define MPLL_CNTL_MODE                                  0x61c
  43 #define         SS_SSEN                                 (1 << 24)
  44 
  45 #define MPLL_AD_FUNC_CNTL                               0x624
  46 #define         CLKF(x)                                 ((x) << 0)
  47 #define         CLKF_MASK                               (0x7f << 0)
  48 #define         CLKR(x)                                 ((x) << 7)
  49 #define         CLKR_MASK                               (0x1f << 7)
  50 #define         CLKFRAC(x)                              ((x) << 12)
  51 #define         CLKFRAC_MASK                            (0x1f << 12)
  52 #define         YCLK_POST_DIV(x)                        ((x) << 17)
  53 #define         YCLK_POST_DIV_MASK                      (3 << 17)
  54 #define         IBIAS(x)                                ((x) << 20)
  55 #define         IBIAS_MASK                              (0x3ff << 20)
  56 #define         RESET                                   (1 << 30)
  57 #define         PDNB                                    (1 << 31)
  58 #define MPLL_AD_FUNC_CNTL_2                             0x628
  59 #define         BYPASS                                  (1 << 19)
  60 #define         BIAS_GEN_PDNB                           (1 << 24)
  61 #define         RESET_EN                                (1 << 25)
  62 #define         VCO_MODE                                (1 << 29)
  63 #define MPLL_DQ_FUNC_CNTL                               0x62c
  64 #define MPLL_DQ_FUNC_CNTL_2                             0x630
  65 
  66 #define MCLK_PWRMGT_CNTL                                0x648
  67 #define         DLL_SPEED(x)                            ((x) << 0)
  68 #define         DLL_SPEED_MASK                          (0x1f << 0)
  69 #       define MPLL_PWRMGT_OFF                          (1 << 5)
  70 #       define DLL_READY                                (1 << 6)
  71 #       define MC_INT_CNTL                              (1 << 7)
  72 #       define MRDCKA0_SLEEP                            (1 << 8)
  73 #       define MRDCKA1_SLEEP                            (1 << 9)
  74 #       define MRDCKB0_SLEEP                            (1 << 10)
  75 #       define MRDCKB1_SLEEP                            (1 << 11)
  76 #       define MRDCKC0_SLEEP                            (1 << 12)
  77 #       define MRDCKC1_SLEEP                            (1 << 13)
  78 #       define MRDCKD0_SLEEP                            (1 << 14)
  79 #       define MRDCKD1_SLEEP                            (1 << 15)
  80 #       define MRDCKA0_RESET                            (1 << 16)
  81 #       define MRDCKA1_RESET                            (1 << 17)
  82 #       define MRDCKB0_RESET                            (1 << 18)
  83 #       define MRDCKB1_RESET                            (1 << 19)
  84 #       define MRDCKC0_RESET                            (1 << 20)
  85 #       define MRDCKC1_RESET                            (1 << 21)
  86 #       define MRDCKD0_RESET                            (1 << 22)
  87 #       define MRDCKD1_RESET                            (1 << 23)
  88 #       define DLL_READY_READ                           (1 << 24)
  89 #       define USE_DISPLAY_GAP                          (1 << 25)
  90 #       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
  91 #       define MPLL_TURNOFF_D2                          (1 << 28)
  92 #define DLL_CNTL                                        0x64c
  93 #       define MRDCKA0_BYPASS                           (1 << 24)
  94 #       define MRDCKA1_BYPASS                           (1 << 25)
  95 #       define MRDCKB0_BYPASS                           (1 << 26)
  96 #       define MRDCKB1_BYPASS                           (1 << 27)
  97 #       define MRDCKC0_BYPASS                           (1 << 28)
  98 #       define MRDCKC1_BYPASS                           (1 << 29)
  99 #       define MRDCKD0_BYPASS                           (1 << 30)
 100 #       define MRDCKD1_BYPASS                           (1 << 31)
 101 
 102 #define CG_SPLL_SPREAD_SPECTRUM                         0x790
 103 #define         SSEN                                    (1 << 0)
 104 #define         CLK_S(x)                                ((x) << 4)
 105 #define         CLK_S_MASK                              (0xfff << 4)
 106 #define CG_SPLL_SPREAD_SPECTRUM_2                       0x794
 107 #define         CLK_V(x)                                ((x) << 0)
 108 #define         CLK_V_MASK                              (0x3ffffff << 0)
 109 
 110 #define MPLL_SS1                                        0x85c
 111 #define         CLKV(x)                                 ((x) << 0)
 112 #define         CLKV_MASK                               (0x3ffffff << 0)
 113 #define MPLL_SS2                                        0x860
 114 #define         CLKS(x)                                 ((x) << 0)
 115 #define         CLKS_MASK                               (0xfff << 0)
 116 
 117 #endif